Instruction Set

Table II is a symbol table providing internal architecture, struction operand and operation symbols used in the in-struction set table.

Instruction Operand Symbols

d 4-bit operand field, 0-15 binary (RAM digit select) 3(2)-bit operand field, 0-7(3) binary

TABLE II. Instruction Set Table Symbols Symbol Definition

Internal Architecture Symbols A 4-bit accumulator

(RAM register select)

11-bit operand field, 0-2047 (1023) 4-bit operand field, 0-15 (immediate data) RAM addressed by variable x

B 7-bit RAM address register (6-bit for COP224C) y RAM(x)

ROM(x) ROM addressed by variable x Br Upper 3 bits of B (register address)

(2-bit for COP224C)

Bd Lower 4 bits of B (digit address) C 1-bit carry register

D 4-bit data output port EN 4-bit enable register G 4-bit general purpose I/O port IL two 1-bit (INO and IN3) latches IN 4-bitinput port

L a-bitTRI-STATE I/O port

M 4-bit contents of RAM addressed by B PC 11-bit ROM address program counter Q a-bit latch for L port

SA,SB,SC 11-bit 3-level subroutine stack SIO 4-bit shift register and counter SK Logic-controlled clock output SKL 1-bit latch for SK output T a-bit timer

Operational Symbols

+ Plus

-

^Minus

~ Replaces

~ Is exchanged with

= Is equal to

A

One's complement of A ED Exclusive-or

: Range of values

Table III provides the mnemonic, operand, machine code data flow, skip conditions and description of each instruc-tion.

TABLE III. COP244C/245C Instruction Set Machine

Mnemonic Operand Hex Language

Data Flow Skip

Description

Code Codo Conditions

(Binary) ARITHMETIC INSTRUCTIONS

ASC 30 10011100001 A+C+RAM(B) ~ A Carry Add with Carry, Skip on

Carry~C Carry

ADD 31 1001110001

I

A+RAM(B)~A None Add RAMtoA

ADT 4A 10100110101 A+1010~A None Add Ten to A

AISC Y ^5- 10101

I y. I

^A+y~A ^Carry Add Immediate. Skip on

Carry (y =1= 0)

CASC 10 10001100001 A+RAM(B)+C~A Carry Complement and Add with

Carry~C Carry, Skip on Carry

CLRA 00 10000100001 ^O~A None Clear A

COMP 40 10100100001 ^A~A None Ones complement of A to A

NOP 44 10100101001 None None No Operation

RC 32 10011100101 "O"~C None ResetC

SC 22 10010100101 "1"~C None Sete

XOR 02 10000100101 A ED RAM (B) ~ A None Exclusive-OR RAM with A

o

N N 0I:loo

o

...

o o

N N U'I

o

...

o o

N N

en o

...

o o

N 0I:loo 0I:loo

o

...

o o

N 0I:loo U'I

o

a

(.) It)

D. C\I

o

(.)

...

(.)

~ ~ C\I D.

o

(.) ...

(.) C\I CD C\I D.

o

(.)

...

(.) It) C\I C\I D.

o

(.)

...

(.)

C\I C\I D.

o

(.)

(Continued)

TABLE III. COP244C/245C Instruction Set (Continued) Machine

Mnemonic Operand Hex Language

Data Flow Skip

Code Code Conditions

(Binary) TRANSFER CONTROL INSTRUCTIONS

JID FF 11111111111 ROM (PC10:a A,M) ~ PC7:0 None

JMP a 6- 10110

I

alQ'e

I

^a~PC ^None

--

JP a - - ~ ^a~^PC6:0 ^None

(pages 2, 3 only) or

- - ₁₁₁

I

as'Q

I

^a~^PC5:0

(all other pages)

JSRP a

- -

_{110 1}_a~'Q

I

^PC+1^~SA~SB~SC^None

00010 ~ PC10:6 a~PC5:0

JSR a 6- 10110111alQ'ei PC+1 ~SA~SB~SC None

- - ~ ^a~PC

RET 48 10100110001 SC ~ SB ~ SA ~ PC None

RETSK 49 10100110011 SC~SB~SA~PC Always Skip

on Return

HALT 33 1001110011

I

^None

38 10011 11000

I

IT 33 10011100111

39 10011110011 None

MEMORY REFERENCE INSTRUCTIONS

CAMT 33 1001110011

I

A~T7:4

3F 10011111111 RAM (B) ~ T 3:0 None

CTMA 33 1001110011

I

T 7:4 ~ RAM (B)

2F 1001011111 1 T3:0~A None

CAMQ 33 10011100111 A~07:4 None

3C 10011111001 RAM(B) ~ 03:0

COMA 33 10011100111 07:4 ~ RAM(B) None

2C 10010111001 03:0~A

LD r -5 100 Ir 10101 1 RAM(B)~A None

(r=0:3) Brer~ Br

LDD r,d 23 10010100111 RAM(r,d)~A None

--

10 1 r 1 d 1

LOID BF 11011 11111 1 ROM(PC10:a.A.M) ~ 0 None

SB~SC

RMB 0 4C 10100111001 O~ RAM(B)o None

1 45 10100101011 0~RAM(B)1

2 42 10100100101 0~RAM(B)2

3 43 10100100111 O~ RAM(B)3

5MB 0 40 10100111011 1 ~RAM(B)o None

1 47 10100101111 1 ~ RAM(Bh

2 46 10100101101 1 ~RAM(B)2

3 48 10100110111 1 ~ RAM(8)3

Description

Jump Indirect (Notes 1, 3) Jump

Jump within Page (Note 4)

Jump to Subroutine Page (Note 5)

Jump to Subroutine

Return from Subroutine Return from Subroutine then Skip

HALT Processor IDLE till Timer

Overflows then Continues

Copy A, RAM to T CopyTto RAM, A Copy A, RAM to 0

Copy 0 to RAM, A Load RAM into A, Exclusive-OR Br with r Load A with RAM pointed to directly by r,d Load 0 Indirect (Note 3)

Reset RAM Bit

Set RAM Bit

Instruction Set

(Continued)

TABLE III. COP244C/245C Instruction Set (Continued) Machine

Mnemonic Operand Hex Language

Data Flow Skip

Code Code Conditions

(Binary) MEMORY REFERENCE INSTRUCTIONS (Continued)

STII y 7- _{10111 1}_Y..

I

^y~^{RAM (B)} ^None

Bd+ 1 ~Bd

X r -6 1001 r 101101 RAM(B)~A None

(r=0:3) Br Ell r ~ Br

XAD r,d 23 10010100111 RAM(r,d)~A None

--

I

^{d 1}

XDS r -7 ₁₀₀

I

0111 1 ^RAM(B)~A Bd

(r=0:3) Bd-1 ~ Bd decrements Br Ell r ~ Br past 0

XIS r -4 100

I

r 10100 1 ^RAM(B)~A Bd

(r=0:3) Bd+1 ~ Bd increments Br Ell r ~ Br past 15 REGISTER REFERENCE INSTRUCTIONS

CAB 50 10101100001 A~Bd None

CBA 4E 10100111101 Bd~A None

LBI r,d - - 100

I

rl (d-1) 1 r,d~B Skip until

(r=0:3: not a LBI

d=O,9:15) or 33 10011100111

--

111 r i d 1 (any r, any d)

LEI y 33 1001110011

I

^y~EN ^None

6- 10110 1 y 1

XABR 12 10001100101 ^A~Br None

TEST INSTRUCTIONS

SKC 20 1001010000 C="1"

SKE 21 1001010001 A=RAM(B)

SKGZ 33 1001110011 G3:0=0

21 1001010001

SKGBZ 33 1001110011 1st byte

0 01

I

0000

I

0001 } ^Go=O

1 11 1000110001 G1=0

2 03 1000010011 2nd byte G2=0

3 13 10001100111 G3=0

SKMBZ 0 01 10000100011 RAM(B)o=O

1 11 10001100011 RAM(B)1=0

2 03 1000010011

I

^RAM(B)2=0

3 13 10001100111 RAM(B)3=0

SKT 41 1010010001

I

A time-base

counter carry has occurred since last test

Description

Store Memory Immediate 1 and Increment Bd Exchange RAM with A, Exclusive-OR Br with r Exchange A with RAM Pointed to Directly by r,d Exchange RAM with A and Decrement Bd.

Exclusive-OR Br with r Exchange RAM with A and Increment Bd, Exclusive-OR Br with r

Copy A to Bd CopyBd to A

Load B Immediate with r,d (Note 6)

Load EN Immediate (Note 7)

Exchange A with Br (Note 8)

Skip if C is True Skip if A Equals RAM Skip if G is Zero (all 4 bits) Skip if G Bit is Zero

Skip if RAM Bit is Zero

Skip on Timer (Note 3)

o

"'0 N N 0l:Io

... o o o

"'0 N N U1

o ...

o o

"'0 N

m

o ...

o o

"'0 N 0l:Io 0l:Io

o ...

o o

"'0 N 0l:Io

o

II

0 II)

~ N

a. 0

...

0 ~

a.

0 ...

0 CD N N

a. 0

...

0 II) N N

0 a.

...

0 ~ N N

0 a.

Instruction Set

(Continued)

TABLE III. COP244C/245C Instruction Set (Continued) Machine

Hex Language Skip

Mnemonic Operand DataFlow

Code Code Conditions

(Binary) INPUT IOUTPUT INSTRUCTIONS

ING 33 10011100111 G-+A None

2A 10010110101

ININ 33 10011100111 IN-+A None

28 10010110001

INIL 33 10011100111 IL3, CKO,"O", ILa -+ A None

29 10010 11001 1

INL 33 10011100111 L7:4 -+ RAM (B) None

2E 10010111101 L3:0 -+ A

OBO 33 10011100111 ^Bd-+O None

3E 10011111101

OGI y 33 10011100111 y-+G None

5- 10101 1

'i.

OMG 33 10011100111 RAM(B)-+G None

3A 1 0011 11010 1

XAS 4F 10100111111 A~SIO,C-+SKL None

Description

Input G Ports to A

Input IN Inputs to A (Note 2)

Input IL Latches to A (Note 3)

Input L Ports to RAM,A

Output Bd to 0 Outputs

Output to G Ports Immediate

Output RAM to G Ports

Exchange A with SIO (Note 3)

Not. 1: All subscripts for alphabet/cal symbols Indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where o signifies the least significant bit (Iow-order, right-most bit). For example, A3 Indicates the most significant (left-most) bit of the 4-bit A register.

Not. 2: The ININ Instruction Is not available on the 24-pln packages since these devices do not contain the IN Inputs.

Not. 3: For additional Information on the operation of the XAS, JID, LaiD, INIL, and SKT Instructions, see below.

Not. 4: The JP Instruction allows a Jump, while In subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP Instruction, otherwise, permits a Jump to a ROM location within the current 64-word page. JP may not Jump to the last word of a page.

Not. fi: A JSRP transfers program control to subroutine page 2 (0010 Is loaded Into the upper 4 bits of Pl. A JSRP may not be used when In pages 2 or 3. JSRP may not Jump to the last word In page 2.

Not. 8: LBlls a single-byte Instruction If d - 0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1, e.g., to load the lower four bits of B(Bd) with the value 9 (10012), the lower 4 bits of the LBllnstructlon equal 8 (10002). To load 0, the lower 4 bits of the LBI Instruction should equal 15 (11112).

Not. 7: Machine code for operand field y for LEI Instruction should equal the binary value to be latched Into EN, where a "1" or "0" In each bit of EN corresponds with the select/on or deselectlon of a particular function associated with each bit. (See Functional Description, EN Register.)

Not. 8: For 2K ROM devices, A - Br (0 - A3). For 1 K ROM devices, A - Br (0,0 - A3, A2).

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