Bus Considerations

False states may be generated on Lo-L7 during the execu-tion of the CAMQ instrucexecu-tion. The L-ports should not be used as clocks for edge sensitive devices such as flip-flops, counters, shift registers, etc. The following short program illustrates this situation.

START:

LOOP:

CLRA ;ENABLE THE Q

LEI 4 ;REGISTER TO L LINES

LBI TEST

STH 3

AISC 12

LBI TEST ;LOAD Q WITH X'C3 CAMQ

JP LOOP

In this program the internal Q register is enabled onto the L lines and a steady bit pattern of logic highs is output on Lo, L1, L6, L7, and logic lows on L2-LS via the two-byte CAMQ instruction. Timing constraints on the device are such that the Q register may be temporarily loaded with the second byte of the CAMQ opcode (X'3C) prior to receiving the valid data pattern. If this occurs, the opcode will ripple onto the L lines and cause negative-going glitches on Lo, L1, L6, L7, and positive glitches on L2-LS. Glitch durations are under 2 microseconds, although the exact value may vary due to data patterns, processing parameters, and L line loading.

These false states are peculiar only to the CAMQ instruction and the L lines.

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Typical Performance Characteristics

Output Sink Current

VOUT (VOLTS) DEVICE I

Standard Output Source Current

-1.75 1-+--+-+--+---<1---+---1

c-1.25

~ E -1.0

- -0.75 ~~-+~+-t'-+-I---+---i

- 0.5 l-...p.~--,~c+.HI--_+_--I - 0.25 1---p..C-+:~~~..3ooo,;Ir--t--i

-20 -18 -16 -14 1"-12

~-10 E-8 -8 -4 -2

VOUT (VOLTS) DEVICE 2

LED Output Source Current

/ ' -

I I

I

\ VCC" 8.3V (MAX)

I 1

1\

I I

""" ^\.

Vel" 4.5 V (MAX)

1\ ... I I

\ , \ _Y

VCC" 4.5V (MIN)

_{I I}

,

\ VCC" 8.3V (MIN)

---

^{~ /}

^{I L}

"..

'"

^{-~~ ' 1}

^I

VOUT (VOLTS) DEVICE 4AND 2

TRI·STATE Output Source Current

i

^-10 ~-l\--+--++-+--+--+~

!;

E

2 3 4 5 7

VOUT (VOLTS) DEVICE 5

-0.4

-0.3 C .!

~-0.2 -0.1

-18 -18 -14 -12 1-10

j

^-8

-8 -4 -2

L Output Depletion Load OFF Source Current

\ \

~MAX MIN

\

i'.... X

VOUT (VOLTS) DEVICE 2

Push·Pull Source Current

VOUT (VOLTS) DEVICE 3AND Z

LED Output Direct LED Drive

MAX

V·

",,"

VOUT" 2.0V ~

/"

..

^' ~

.' "-

~'t

... I--^~

o 4 u

u

VCC (VOLTS) DEVICE UND 2

Input Load Source Current

1

^-0.8 ~:+-~rl-ti'+1', I;

9

FIGURE 9b. COP420/COP4211nput/Output Characteristics

TL/OO/6921-23

Typical Performance Characteristics

(Continued)

10

! _...

§

2

YOUT (YOLTS) OEYICE 1 Standard Output Source Current -1.75 r-~-""""'-r---r-~---'-...,

!

^-1.0 t-''rV~-t---t--t---'r--+---I

~ ^{-0. 75} I---r~---Hr-I---+---+---if----I

-0.5

3 4

YOUT (YOLTS) DEYICE 2

LED Output Source Current

-24r-~-....,....-r---r-~---'

YOUT (YOLTS) DEYICE 4 AND 2 TRI-STATE Output Source Current -15 Ft--t---+t-I-f'-t--+_---<I----i

! _...

^-10

:::»

!:

-5

4

YOUT (YOLTS) DEYICE 5

L Output Depletion Load OFF Source Current

~ -0.4

~ -0.3

i"

1"

-0.2 -0.1

~N_~

2 3 4

YOUT (YOLTS) DEYICE 2 Push-Pull Source Current -3.0 r-~-n-""T"1r-r-""-""--'

- 2.0 I--t--t--tt--+lr-H

;: -1.5 1---+-\--+-\----i1f-i'-++-+---I

§

4

YOUT (YOLTS) DEYICE 2 AND 3 LED Output Direct LED Drive

I

-14

-12

/

/

MAX -10

<"

.I!

...

_-8

§

-6

II I

.1 I

I YOUT=2.0Y

I

-4 _I I

-2

--~

^~

....

o

4.0 4.5 5.0 5.5 6.0 Ycc (YOLTS) DEVICE 4 AND 2 Input Load Source Current -1.0 1--t--+----1I---t--+_-I

-0.2 1-'----\~-+_~~N:-+___1

2 4

YOUT (YOLTS) DEYICE 6 FIGURE 9c. COP320/COP321 Input/Output Characteristics

TL/DD/6921-24

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Instruction Set

Table I is a symbol table providing internal architecture, struction operand and operational symbols used in the in-struction set table.

Table " provides the mnemonic, operand, machine code, data flow, skip conditions and description associated with each instruction in the COP420/COP421/COP422 instruc-tion set.

TABLE I. COP420/421/422/320/321 1322 Instruction Set Table Symbols

Symbol Definition Symbol Definition

INTERNAL ARCHITECTURE SYMBOLS INSTRUCTION OPERAND SYMBOLS

A 4-bit Accumulator d 4·bit Operand Field, 0-15 binary (RAM Digit Select)

B 6-bit RAM Address Register r 2-bit Operand Field, 0-3 binary (RAM Register

Br Upper 2 bits of B (register address) Select)

Bd Lower 4 bits of B (digit address) a 1 O-bit Operand Field, 0-1023 binary (ROM Address)

C 1-bit Carry Register y 4-bit Operand Field, 0-15 binary (Immediate Data)

o

4-bit Data Output Port RAM(s) Contents of RAM location addressed by s

EN 4-bit Enable Register ROM(t) Contents of ROM location addressed by t

G 4-bit Register to latch data for G I/O Port IL Two 1-bit latches associated with the IN3 or

INo inputs OPERATIONAL SYMBOLS

IN 4-bit Input Port + Plus

L a-bit TRI·STATE 1/0 Port - Minus

M 4-bit contents of RAM Memory pointed to by ^~ Replaces

B Register ^~ Is exchanged with

PC 9-bit ROM Address Register (program counter) ⁼ Is equal to

Q a-bit Register to latch data for L 1/0 Port A The one's complement of A SA 1 O-bit Subroutine Save Register A ^EI:l Exclusive-OR

SB 1 O-bit Subroutine Save Register B : Range of values

SC 10 Subroutine Save Register A SIO 4-bit Shift Register and Counter SK Logic-Controlled Clock Output

TABLE II. COP420/421/422/320/321 1322 Instruction Set

Hex Machine

Mnemonic Operand

Code Language Code DataFlow Skip Conditions Description

(Binary) ARITHMETIC INSTRUCTIONS

ASC 30 10011100001 A + C + RAM (B) ~ A Carry Add with Carry, Skip on

Carry ~ C Carry

ADD 31 1001110001

I

A + RAM (B) ~ A None AddRAMtoA

ADT 4A 1010011010

I

A + 1010 ~ A None Add Ten to A

AISC y 5- 10101

I

^y

I

^{A+y ~ A Carry} Add immediate, Skip on

Carry (y =1= 0)

CASC 10 10001100001 A + RAM (B) + C ~ A Carry Complement and Add with

Carry ~ C Carry, Skip on Carry

CLRA 00 10000100001 ^O~A None Clear A

COMP 40 10100100001 ^A~A None One's complement of A to A

NOP 44 10100101001 None None No Operation

RC 32 10011100101 "0" ~ C None ResetC

SC 22 10010100101 "1" ~ C None SetC

XOR 02 10000100101 A EI:l RAM (B) ~ A None Exclusive-OR RAM with A

Instruction Set

(Continued)

TABLE II. COP420/421/422/320/321/322 Instruction Set (Continued)

Hex Machine

Mnemonic Operand

Code Language Code Data Flow Skip Conditions

(Binary) TRANSFER OF CONTROL INSTRUCTIONS

JID FF 11111111111 ROM (PCs, A,M) -+ None

PC7:0

JMP a 6- 1011O lOOlaai a -+ PC None

- -

1 a7:0 1

JP a

- -

111 Ci6:0 1 a -+ PC6:0 None

(pages 2,3 only)

- ^-

¹¹¹¹ or ^a5:0 1 a -+ PC5:0 (all other pages)

JSRP a

- -

110 1 a5:0 1 PC

+

1 -+ SA -+ SB -+ SC None 010 -+ PCS:6

a -+ PC5:0

JSR a 6- 101101101 ag:sl PC

+

1 -+ SA -+ SB -+ SC None

- - I

^a7:0

^I

^{a -+ PC}

RET 48 10100110001 SC -+ SB -+ SA -+ PC None

RETSK 49 10100110011 SC -+ SB -+ SA -+ PC Always Skip

on Return MEMORY REFERENCE INSTRUCTIONS

CAMO 33 10011100111 A -+ 07:4 None

3C 10011111001 RAM (B) -+ 03:0

COMA 33 10011100111 07:4 -+ RAM (B) None

2C 10010111001 03:0 -+ A

LD r -5 100lrl01011 RAM(B) -+ A None

Br Ell r -+ Br

LDD r,d 23 10010100111 RAM(r,d) -+ A None

--

100 1 r 1 d 1

LOID BF 11011111111 ROM(PCg:s,A,M) -+ 0 None

SB -+ SC

RMB 0 4C 10100111001

o

-+ RAM(B)o None

1 45 10100101011

o

-+ RAM(B)1 2 42 10100100101

o

-+ RAM(B)2 3 43 10100100111

o

-+ RAM(Bb

5MB 0 40 10100111011 1 -+ RAM(B)o None

1 47 10100111011 1 -+ RAM(Bh 2 46 10100101101 1 -+ RAM(B)2 3 4B 1010011011 1 1 -+ RAM(Bb

STII y 7- 10111 1 y 1 y -+ RAM (B) None

Bd

+

1 -+ Bd

X r -6 100 1 r 101101 RAM (B)

+-+

A None

Br Ell r -+ Br

XAD r,d 23 10010100111 RAM (r,d)

+-+

A None

- -

110 1 r 1 d 1

Description

Jump Indirect (Note 3)

Jump

Jump within Page (Note 4)

Jump to Subroutine Page (Note 5)

Jump to Subroutine

Return from Subroutine Return from Subroutine then Skip

Copy A, RAM to 0

Copy 0 to RAM, A

Load RAM into A Exclusive-OR Br with r Load A with RAM pOinted to directly by r,d Load 0 Indirect (Note 3)

Reset RAM Bit

Set RAM Bit

Store Memory Immediate and Increment Bd Exchange RAM with A, Exclusive-OR Br with r Exchange A with RAM pointed to directly by r,d

o -a

oI:Ito

o

N

...

o o

-a

oI:Ito N

...

~

o o

-a

oI:Ito N

...

N

o o

-a w

N

o

...

o o

-a w

N

...

~

o o

-a w

N N

II

N N

~ ~

-N C")

a.. ~

N

~

o ~

N

l o u ...

-~ a..

o u

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