TRAP SYSTEM
FIXED-POIITOVERFLOW TRAP
Overflow can occur for any of the fol lowing instructions:
Operation
Instruction Mnemonic Code
Load Absol ute Word LAW X'3B'
Load Absolute Doubleword LAD X'1B'
Load Complement Word LCW X'3A'
Load Complement Doubleword LCD X'1A'
Add Ha I fword AH X'50'
Subtract Halfword SH Xt5S'
Divide Haffword DH X'56'
Add Immediate AI X'20'
Add Word AW X'30'
Subtract Word SW X'3S'
Divide Word DW X'36'
Add Doubl eword AD X'lO'
Subtract Doubl eword SD X'lS'
Modify and Test Halfword MTH X'531
Modify and Test Word MTW X'33'
Add Word to Memory AWM X'66'
Except for the instructions DIVIDE HALFWORD (DH) and DIVIDE WORD (DW), the instruction execution is allowed to proceed to completion. CC2 is set to 1 and CC3 and CC4 represent the actual result (0, -, or +) after overflow.
If the fixed-point arithmetic trap mask (bit 11 of PSD) is a 1, the CPU traps to Homespace location X'431 instead of executing the next instruction in sequence.
For DW and DH, the instruction execution is Qoorted with-out changing any register, and CC2 is set to 1; but CC1, CC3, and CC4 remain unchanged from their values at the end of the instruction immediately prior to the DW or DH.
If the fixed-point arithmetic trap mask is a 1, the CPU traps to location X'431 instead of executing the next instruc-tion in sequence.
The execution of XPSD in Homespace trap location X'431 is as follows:
1. Store the current PSD. If the instruction trapped was any instruction other than DW or DH, the stored con-dition code is interpreted as follows:
CC1t CC2 CC3
tt
o
o
o
CC4 Meaning
o
Result after overflow is zero.Resu I t after overflow is negative.
o
Result after overflow is positive.No carry out of bit 0 of the adder (add and subtract instructions only).
Carry out of bit 0 of the adder {add and subtract instructions only}.
If the instruction trapped was a DW or DH, the stored condition code is interpreted as follows:
CC1 CC2 CC3 CC4 Meaning
tt Overflow
tCCl remains unchanged for instructions
LCW~
LAW, LCD, and LAD.ttAhyphen indicates that the condition code bitsarenot af-fected by the condition given under the "Meaning" heading.
2. Load the new PS D. The conditi on code and instruction address portions of the PSD remain at the value loaded from memory.
FlOATING-POINT ARITHMETIC FAULT TRAP
Floating-point fault detection is performed after the opera-tion called for by the instrucopera-tion code is performed, but before any results are loaded into the general registers.
Thus, the floating-point operation that causes an arithmetic fault is not carried to completion in that the original con-tents of the general registers are unchanged.
Instead, the computer traps to Homespace location X '441 with the current condition code indicating the reason for the trap. A characteristic overflow or an attempt to divide by zero always results in a trap condition. A significance check or a characteristic underflow results in a trap condi-tion only if the floating-point mode controls {FS, FZ, and FN} in the current program status doubleword are set to the appropriate state.
If a floating-point instruction traps, the execution of XPSD in Homespace trap location X'441 is as follows:
1. Store the current PSD. If division is attempted with a zero divisor or if characteristic overflow occurs, the stored condition code is interpreted as follows:
CCl CC2 CC3 CC4 Meaning
0 0 0 Zero divisor.
0 0 Characteristic overflow,
negative result.
0 0 Characteristic overflow,
positive result.
If none of the above conditions occurred but charac-teristic underflow occurs with floating zero mode bit (FZ) = 1, the stored condition code is interpreted as follows:
CCl CC2 CC3 CC4 Meaning
o
Characteri sti c under-flow, negative result.o
Characteristic under-ffow, positive result.If none of the above conditions occurred but an addition or subtraction results in either a zero result (with FS = 1 and FN = 0), or a postnormalization shift of more than two hexadecimal places {with FS
=
1 and FN=
O}, the stored condition code is interpreted as follows:CCl CC2 CC3 CC4 Meaning
o o o
Zero result of additionor subtraction.
T rap System 39
CCl
ee2
CC3 CC4 Meaning1
o o
o
1
o
More than two post-normal i zing shifts, negative result.
More than two post-normatizing. shifts, positive result.
2. load the new PSD. The condition code and instruc-tion address porinstruc-tions of the PSD remain at the values loaded from memory.
DECIMAL ARITHMEnc FAUll TRAP
When either of two decimal fault conditions occurs (see
II Decimal Instructionsll) , the normal sequencing of instruc-tion execuinstruc-tion is hafted,
ec
land CC2 are set according to the reason for the fault condition, and CeJ, CC4, mem-ory, and the decimal accumulator remain unchanged by the instruction. If the decimal arithmetic trap mask (bit posi-tion 10 of PSWl) -is a 0, the instruction execution sequence continues with the next instruction in sequence at the time of fault detection; however, if the decimal arithmetic trap mask contains a 1, the computer traps to Homespace loca-tion Xf45 f at the time of fault detection. The following are the fault conditions for decimal instructions:Instruction Name Mnemonic Fault
Decimal load Dl Illegal digit
Decimal Store OS Illegal digit
Decimal Add DA Overflow, illegal
digit
Decimal Subtract
DS
Overflow, Hlegaldigit
Decimal Multiply OM IHegal digit
Decimal Divide DO Overflow, illegal
digit
Decimal Compare DC fUegal digit
Dec imol Shift DSA II legal digit Arithmetic
Pock Decimal PACK Illegal digit
Digits
Unpack Decimal UNPK IUegal digit
Digits
Edit Byte String EBS Illegal digit
40 Trap System
The execution of XPSD in Homespace trap location X'451 is as follows:
1. Store the current PSD. The stored condition code is interpreted as follows:
CCI Ce2 CC3 CC4 Meaning
0 t AU digits legal and
overflow.
1" 0 Illegal digit detected.
2. Load the new PSD. The condition code and instruction address portions of the PSD remain at the values loaded from memory.
CALL IISTRUCllOl TRAP
The four CAll instructions (CAll, CAl2, CAl3, and CAL4) cause the computer to trap to Homespace location X'48' (for CAll), X'491 (for CAl2), Xf4Af (for CAl3), or X'4Bf (for CAl4). Execution of XPSD in the trap location is as foJ lows:
1. Store the current PSD. The stored condition code bits are those that existed prior to the CAll instruction.
2. Load the new PSD.
3. Modify the new PSD.
a. The R Field of the CAll instruction is logically ORed with the condition code register as loaded from memory.
b. If bit 9 of XPSD contains a 1, the R field of the CALL instruction is added to the program counter.
If bit 9 of XPSD contains a 0, the program counter remains unchanged from the value loaded from memory.
Note: Return from a CAll trap will be to the trapping instruction + 1.
PROCESSOR DmClED fAULlS
The Processor Detected Fault (PDF) flag is ahardware flog used in the SIGMA 9 system to aid in solving the mul-tiple error problem. Most traps occur because of some dynamic programming consideration (i. e., overflow, at-tempted division by zero, incorrect use of an instruction or address, etc.) and recovery is easify handled by another software subroutine. However, with certain classes of errors, if a second error occurs white the computer is
t A hyphen indicates that the condition code bit is not affected by the condition given under the "Meaning"
heading.
attempting to recover from the first error, unpredictable memory fault interrupt, and count pulse interrupts are auto-matically inhibited. The other interrupts, with the excep-tion of power fai I-safe, mayor may not be inhibited as another CPU executing an RIO instruction.
If the operator wants to resume operation without recovery, or to stop and exami ne the current state of the system, he IDLE but repetitively reenters the trap sequence attempting to execute the invalid instruction. For this case, the inter-rupt generated flag is cleared.
3. The PSD is cleared to zero except that the instruction location X'461 occurs immediately after the instruction is completed. TCC1 is set to indicate successful completion of the instruction, and TCC2, 3, and 4 are set to zero.
TCC1 is set only if no other trap is pending at the end of the completed instruction, and indicates that the return address stored by the XPSD should point to the next
The instruction exception trap occurs whenever the CPU detects a set of operations that are co lied for in an i nstruc-tion but can not be executed because of either a hardware restriction or a previous event.
The different conditions that cause the instruction exception trap are: required. Note that instructions executed as a result of the interrupt or trap other than the instruction lo-cated at the interrupt or trap location are not consid-ered part of the entry sequence.
2. An illegal instruction is found in the trap (not XPSD) or interrupt (not XPSD, MTB, MTH, MTW) location when executing a trap or interrupt sequence.
3. The register pointer (bits 56-59) of the PSD is set to a nonexistent register block as a result of an LRP, LPSD, or XPSD.
Trap System 41
4. Bit positions 12-14 of the MOVE TO MEMORY CONTROL (MMC) instruction are interpreted as an illegal configuration. That is, any configuration other than 100, 010, 001, or 101.
5. The set of operations, primari Iy doubleword and byte-string instructions, that yield an unpredictable result when an incorrect register is specified; this type of fault is called lIinvalid register designationll and includes the following instructions: t
Register 0 Specified Edit Byte String (EBS) Odd Register Specified Add Doubleword (AD) Subtract Doubleword (SD) Floating Add Long (FAL) Floating Subtract Long (FSL) Floating Multiply Long (FMl) Floating Divide Long (FDL) Translate Byte String (TBS)
Translate and Test Byte String (TTBS) Edit Byte String (EBS)
Move to Memory Control (MMC)
Trap Condition Code. The Trap Condition Code (TCC) differentiates between the different fault types. Some of the fault conditions (as listed in Table 8) may occur and/or be detected during a trap or interrupt entry sequence. In this case, the trapped status field, bits 48-55 of the PSD, are set to equal the least significant eight bits of the ad-dress of the trap or interrupt instruction in whi ch the trap occurred; that is, the trapped status field wi" point to the trap or interrupt location that was in effect when the fault occurred. In the event that the fault occurs in a normal program instruction, the trapped status field has no meaning.
Table 5 shows the settings of the TCC and trapped status field for the various fault types.
PARITY ERROR TRAP
Three types of parity errors may be detected in the ad-dressing and memory logic.
1. Map Check. When the CPU is operating with the memory map, a parity check is made on the page
t"lnvalid register designation" faults do not set the PDF Hag.
42 Trap System
Table 8. TCC Setting for Instruction Exception Trap X'4D'
I
T rapped Status TCC Field (PSD bits
Fault Type 1 234 48-55)
XPSD in trap or 1 000 8 least significant interrupt location tries bits of trap or to set register pointer interrupt address.
to nonexistent register block.
XPSD, LPSD, or LRP 0000 No meaning.
not in a trap or inter-rupt sequence tries to set register pointer to nonexistent register block.
Trap or interrupt 1 1 1 1 8 least significant sequence and pro- b its of trap or cessor detected fault. interrupt address.
Trap or interrupt 1 1 00 8 least significant
sequence with bits of trap or
inval id instruction. interrupt address.
MMC configuration 001
a
No meaning.invalid.
Invalid register 0001 No meaning.
designation.
addresses retrieved from the map. If an error is found, this fault occurs. The CPU aborts the memory request, traps to Homespace location X'4C' and sets TCC2 to 1.
2. Data Bus Check. If the CPU detectst a parity error on data received from memory and the memory does not also indicate a parity error on the information sent, a data bus check occurs. The data bus check causes the CPU to trap to Homespace location X'4C', and sets TCC3 to 1.
3. Memory Parity Error. When a CPU receivest a signal from the memory indicating memory parity error, this fault occurs. The CPU traps to Homespace location
X'4C'. In addition, on a memory-detected parity error trap, the memory bank wi II "snapshot II the address causing the trap.
The memory parity error signal is generated:
1. When the memory is performing a read operation and a parity error is detected in the data as read from the memory elements.
t Note exceptions in IITrap Conditions During 'Anticipate' Operationsll•
90 17 33C-1(4/74)
2. When the memory is performing a partial write operation and a parity error is detected when reading the word to be changed. This is done before the new information is inserted and the data restored to memory;
memory is not changed.
3. When a parity error is detected in the memory on an address received on the memory bus. If the address bus check occurs on a write request, the memory is not accessed. On a read request, dummy data with incor-rect parity is sent to the processor.
4. When a parity error is detected on data received by the memory from the memory bus. The memory is not accessed and the data is not used.
5. If the memory has a port selection error in attempting to establish priority for requests received on two or more ports. The memory parity error signal is generated on the busses for a II ports affected by the se I ecti on error.
6. If the LOAD MEMORY STATUS instruction is used and the condition code set prior to execution of the instruc-tion is reserved (i. e., not implemented in the memory logic), the memory will interpret it as a read-type instruction, send back a parity error signal and all zeros on the data bus, and "snapshot" the address in the Memory Status Register.
In addition, any of these six conditions will always cause a Memory Fault Interrupt to occur.
TRAP CONDITIONS DURING "ANnCIPATE"
OPERAnONS
During the time that the SIGMA 9 is executing a current instruction, it is also performing operations in anticipation of the next instruction, as specified by the instruction ad-dress. These operations (accessing the next instruction, the associated operand, and/or indirect address, etc.) may encounter trapping conditions. Whether a corresponding trap wi II occur is contingent on the current instruction.
Traps due to the current instruction and traps due to branch operations wi II inhibit traps due to operations performed in anticipation of the next instruction.
If the current instruction is a successful branch instruction, the instruction sequence is changed. Therefore, operations performed in anticipation of the next instruction are no longer valid, and any traps associated with these operations are disregarded.
If the current instruction encounters a trap, it takes prece-dence over the next instruction and any anticipated trap.
At the end of the trap routine these operations 'wi II be reper-formed and the proper trap action wi II occur at this time.
At the end of the execution of current (nonbranching) in-structions, trap conditions detected during "anticipate"
operations have priority over an interrupt. These trap con-ditions include nonexistent memory, access protection vio-lation, nonexistent instruction, privi leged instruction in slave mode, and parity error.