The EXECUTE instruction can be used to insert another in-struction into the program sequence, and the branch instruc-tions can be used to al ter the program sequence, either
tFor real extended mode of addressing this is a 22-bit field (10-31); for real and virtual addressing modes it is a 17-bit field (15-31).
unconditionally or conditionally. If a branch is uncondi-tional (or conditiona I and the branch condition is satisfied), the instruction pointed to by the effective address of the branch instruction is normally the next instruction to be exe-cuted. If a branch is conditional and the condition for the branch is not satisfied, the next instruction is normally taken from the next location, in ascending sequence, after the branch instruction.
BRANCHES IN REAL EXTENDED ADDRESSING MODE The extension address field of the PSD wiil be modified automatically by branch instructions. If the effective address of a branch instruction is outside the first 64K of real memory (region 0 is defined as the first 64K of real memory), the high-order bits of this full effective address will automatically be loaded into the Extension Address field of the PSD if the branch is taken. The remaining part of the effective branch address will, of course, be loaded into bit positions 16-31 of the PSD. In addition, bit posi-tion 15 of the PSD, the Extension Selector, will be set to 1.
If the effective branch address is to a location within the first 64K of memory, then the Extension Address field of the'PSD will not be modified. The effective address will be loaded into the 16 low-order positions of the instruction address field and the Extension Selector (bit 15) will be cleared (set equal to zero). This means that once the Extension Address field has been set, it will remain set until it is either changed by the loading of a new PSD or by actually branching into another 64K region of memory (excluding region 0).
A BRANCH AND LINK instruction in real extended ad-dressing wi II store the full address of the next instruction in the link register. If the Extension Selector in the PSD at the time BRANCH AND LINK is executed is zero, then the address stored in the link register will be the in-cremented 16-bit displacement from positions 16-31 of the PSD and zeros in the high-order address positions. If the Extension Selector in the PSD is one, then the address stored will be the incremented 16-bit displacement (PSD 16-31) concatenated with the contents of the Extension Address field (PSD 42-47), which are loaded into bit tions 10-15 of the link register. In both cases, posi-tions 0-9 of the I ink register will be cleared.
NONALLOWED OPERATION TRAP DURING EXECUTION
-OF
BRANCH INSTRUCTIONA branch instruction has two possible places from which the next instruction may be taken: the location following the branch instruction or the location that may be branched to.
It is possible that either of these two locations may be in a protected memory region or in a region that is physi cally nonexistent. The execution of the branch does not cause a trap unless the instruction that is actually to follow the branch instruction is in a protected or nonexistent memory region. Traps do not occur because of any anticipation on the part of the hardware.
Execute/Branch Instructions 97
A nonaUowed operation trap condition during execution of a branch instruction will occur for the following reasons:
1. The branch instruction is indirectly addressed and the branch conditions are satisfied, but the address of the location containing the direct address is either non-existent or unava i lable for read access to the program in the slave mode.
2. The branch instruction is unconditional (or the branch is conditionar and the condition for the branch is sat-isfied), but the effective address of the branch instruc-tion is either nonexistent or unavailable for instrucinstruc-tion or read access to the program (in slave or master-protected mode).
If either of the above situations occurs, the computer aborts execution of the branch instruction and executes a non-aHowed operation trap.
Prior to the time that an instruction is accessed from mem-ory for execution, bit positions 15-31 of the program status doubleword contain the virtual address of the instruction, referred to as the instruction address. At this time, the computer traps to Homespace location X'40' if the actual address of the instruction is nonexistent or instruction-access protected. If the instruction address is existent and is not instruction-access protected, the instruction is ac-cessed and the instruction address portion of the program status doubleword is incremented by 1, so that it now contains the virtual address of the next instruction in sequence (referred to as the updated instruction address).
If a trap condition occurs during the execution sequence of any instruction, the computer decrements the updated in-struction address by 1 and then traps to the location assigned to the trap condition. If neither a trap condition nor a satisfied branch condition occurs during the execution of an instruction, the next instruction' is accessed from the
location pointed to by the updated instruction address. If a satisfied branch condition occurs during the execution of a branch instruction (and no trap condition occurs), the next instruction is accessed from the location pointed to by the effective address of the branch instruction.
EXU EXECUTE
(Word index alignment)
EXECUTE causes the computer to access the instruction in the location pointed to by the effective address of EXU and execute the subject instruction. The execution of the sub-ject instruction, including the processing of trap and in-terrupt conditions, is performed exactly as if the subject instruction were initially accessed instead of the EXU instruction. If the subject instruction is another EXU, the computer executes the subject instruction pointed to by the effective address of the second EXU as described above.
Such "chains" of EXECUTE instructions may be of any length, and are processed (without affecting the updated instruction address) until an instruction other than EXU is
98 Execute/Branch Instructions
encountered. After the final subject instruction is executed, instruction execution proceeds with the next instruct:on in sequence after the initial EXU (unless the subject instruction is an LPSD or XPSD instruction, or is a branch instruction and the branch condition is satisfied).
If an interrupt activation occurs between the beginning of an EXU instruction (or chain of EXU instructions) and the last interruptible point in the subject instruction, the com-puter processes the interrupt-servicing routine for the active interrupt level and then returns program control to the EXU instruction (or the initial instruction of a chain of EXU instructions), which is started anew. Note that a program is interruptible after every instruction access, including accesses made with the EXU instruction, and the inter-ruptibility of the subject instruction is the same as the nor-mal interruptibility for that instruction.
If a trap condition occurs betwe~n the beginning of an EXU instruction (or chain of EXU instructions) and the completion of the subject instructi on, the computer traps to the appro-priate trap location. The instruction address stored by the XPSD instruction in the trap location is the address of the EXU instruction (or the initial instruction of a chain of EXU instructions).
Affected: Determ i ned by subject instruction
Traps: Determined by subject instruction Condition code settings: Determined by subject instruction
BCS BRANCH ON CONDITIONS SET (Word index alignment)
o 1 2
BRANCH ON CONDITIONS SET forms the logical product (AND) of the R field of the instruction word and the cur-rent condition code. If the logical product is nonzero, the branch condition is satisfied and instruction execution pro-ceeds with the instruction pointed to by the effective ad-dresst of the BCS instruction. However, if the logical product is zero, the branch condition is unsatisfied and instruction execution then proceeds with the next instruc-tion in normal sequence.
Affected: (IA) if CC n R
f
0If CC n (1)8-11
f
0, EVA15_31-IA If CC n (1)8-11=
0, IA not affectedIf the R field of BCS is 0, the next instruction to be exe-cuted after BCS is always the next instruction in ascending sequence, thus effectively producing a IIno operation"
instruction.
t See" Branches in Rea I Extended Addressing Mode" in the in-troductory description under "Execute/Branch Instructionsll•
8eR
BRANCH ON CONDITIONS RESET (Word index alignment)BRANCH ON CONDITIONS RESET forms the logical pro-duct (AND) of the R field of the instruction word and the current condition code. If the logi cal product is zero, the branch condition is satisfied and instruction execution then proceeds with the instruction pointed to by the effective addresst of the BCR instruction. However, if the logical product is non:z:ero, the branch condition is unsatisfied and instruction execution then proceeds with the next instruc-tion in normal sequence.
Affected: (lA) if CC n R
= °
If CC n (1)8-11 = 0, EVA 15_
31- IA If CC n (1)8-11
10,
IA not affectedIf the R field of BCR is 0, the next instruction to be exe-cuted after BCR is always the instruction located at the effective address of BeR, thus effectively producing a
"branch unconditional Iii instruction.
BIR BRANCH ON INCREMENTING REGISTER (Word index al ignment)
BRANCH ON INCREMENTING REGISTER computes the effective virtual address and then increments the contents of general register R by 1. If the result is a negative value, the branch condition is satisfied and instruction execution then proceeds with the instruction pointed to by the effec-tive addresst of the BIR instruction. However, if the result is zero or a positive value, the branch condition is not satisfied and instruction execution proceeds with the next instruction in normal sequence.
Affected: (R), (IA) (R) + 1 - R If (R)O = 1, EVA
15_
31- - IA If (R)O --, 0, I~ not affected
If the branch condition is satisfied and if the effective ad-dress of BIR is either unavailable to the program (slave or master-protected mode) for instruct i on access or is non-existent, the computer aborts execution of the BIR instruc-tion and traps to Homespace locainstruc-tion X' 40' . In this case, the instruction address stored by the XPSD instruction in location X'40 ' is the virtual address of the aborted BIR in-struction. If the computer traps because of instruction access protection, register R will contain the value that existed just before the BIR execution (i .e., updated instruction address).
If a memory parity error occurs due to the accessing of the instruction to which the program is branching, the computer aborts execution of the SIR and traps to Home-space location X' 4C with reg ister R unchanged.
BDR BRANCH ON DECREMENTING REGISTER (Word index al ignment)
o 1 2
BRANCH ON DECREMENTING REGISTER computes the effective virtual address and then decrements the contents of general register R by 1. If the result is a positive value, the branch condition is satisfied and instruction execution then proceeds with the instruction pointed to by the effec-tive addresst of the BDR instruction. - However, if the result is zero or
a
negotive va I ue, the branch condition is unsatis-fied and instruction execution proceeds with the next in-struction in norma I sequence.Affected: (R), (IA) (R) - 1 - R
If (R)O =0 and (R)1-31
10,
EVA 15_31- - I A If (R)O = 1 or (R) = 0, IA not affected
If the effective address of BDR is unavai lable to the pro-gram (sl ave or master-protected mode) for i nstructi on access and the branch condition is satisfied, or if the effective address of BDR is nonexistent, the computer aborts execu-tion of the BDR instrucexecu-tion and traps to Homespace locaexecu-tion X '40' . In this case, the instruction address stored by the XPSD instruction in location X'40' is the virtual address of the aborted BDR instruction. If the computer traps because of instruction access protection, register R will contain the value that existed just before the BDR instruction. If a memory parity error occurs due to the accessing of the in-struction to which the program is branching, the computer aborts execution of the BDR and traps to Homespace loca-tion X' 4C with register R unchanged.
BAL
o 1 2
BRANCH AND LINK (Word index alignment)
BRANCH AND LINK determines the effective virtual ad-dress, loads the updated instruction address (the virtual address of the next instruction in normal sequence after the BAL instruction) into bit positions 15-31 of general reg-ister R, clears bit positions 0-14 of regreg-ister R to OIS and then replaces the updated instruction address with the ef-fective virtual address. Instruction execution proceeds with the instruction pointed to by the effective address of the BAL instruction.
t See II Branches in Real Extended Addressing Mode" in the in-troductory description under "Execute/Branch Instructionsll•
Execute/Branch Instructions 99
The SAL instruction in real extended addressing wi" store the full address of the next instruction in the specified R register. If the Extension Selector in the PSD at the time SAL is executed is equal to zero, then the address stored in the specified R register will be the incremented 16-bit dis-placement from positions 16-31 of the PSD, and zeros in the high-order address positions. If the Extension Selector in the PSD is equal to one, then the address stored wi II be the incremented 16-bit displacement (PSD 16-31) concate-nated with the contents of the Extension Address (PSD 42-47).
In both cases, positions 0-9 of the specified R register will be set equal to zero.
Affected: (R), (IA)
IA - R
15
-31; 0 - -
RO-14; EVA
15_31- I A
If the effective address of SAL is unavai labre to the program (slave or master-protected mode) for instruction access and the branch condition is satisfied, or if the effective address of BAL is nonexistent, the computer aborts execution of the SAL instruction and traps to Homespace location X'40' (non-allowed operation trap). In this case, the instruction address stored by the XPSD instruction in location X'40' is the virtual address of the aborted SAL instruction. If the computer traps because of instruction access protection, register R will con-tain the updated instruction address. If a memory parity error occurs due to the accessing of the instruction to which the program is branching, the computer aborts execution of the BAL and traps to Homespace location X'4C' with regis-ter R changed to the updated instruction address.