Ctl SS's 04.20.04.1
,
Set Man Ctl Tgr 04.20.05.1
AO (D1)
+
Set Enter MQ Tgr 04.20.08.1 (3D)
,
Reset Man Ctl Tgr 04.20.05.1 (4B)
•
A2 (D1) Op Keys-SR 04.20.14.1 (2C)
t
A3 (D1) SR-MQ 02.12.40.1 (4B)
A7 (D1)
+
Reset Enter MQ Tgr 04.20.08.1 (4E) Figure 101. Enter MQ
alter the program counter. The key is effective only in manual status (Figure 102). Overlap mode is inhibited.
Load Cards
With the automatic-manual key in automatic, the com-puter in ready status (ready light may be off), and chan-nel A not in manual status, depressing the load cards key: gives an interlock reset to the CPU and all chan-nels not in manual status, selects the card reader on channel A, and turns on indicator S and sets the word counter to three (channel A).
Three words (9 row left and right, and 8 row left) from the first card enter storage location 0, 1, and 2.
Figure 102. Enter Instruction
The word entered in address 0 should be a control word. When the word counter goes to 0, the channel asks for another control word from location O. The CPU
gets its next instruction from location 1. See Figure 103.
~
Fire Man Cards Key•
on channel A instead of the card reader. See Figure 104.®
Tape Key1
Customer Engineering Test Panel
In addition to the indicators and manual controls on the operator's panel, the CE has the indicators and con-trols on the customer engineering test panel.
The indicators provide a means for checking the ad-dress register contents, the tally counter, various test triggers, and the cycle time. The switches and jacks provide means to continually execute any instruction, control I/O operation, suppress overlap, and step through instructions cycle-by-cycle.
Figure 105 shows the layout of indicators and con-trols for this panel.
Indicators
Indicators on the customer engineering test panel are incandescent. Indicators connected to triggers are on when the trigger is on. Indicators concerned with the
Multiple Time Error
This lamp will come on if: both single- and double-precision floating-divide in-structions. The tally counter indicators also reflect the status of the fact triggers. The fact triggers are used for single-precision floating add, subtract, and multi-ply, and for all double-precision floating-point instruc-tions. The indicators are read as a three-position counter. Tally counter indicators two and three on in-dicate fact three. Indicator one only on inin-dicates fact four (Systems 02.13.61.1 and 02.10.21.1).
DPS
The DPS indicators reflect the status of the double-precision sync triggers one through three. The DPS
steps, zero through three, control operations during double-precision floating-point operations (Systems 02.13.63.1).
104
Carry
This lamp indicates a
Q
carry during POD 30 and POD40 instructions (fixed and floating point add and sub-tract). See Systems 02.02.40.1.
FP 9P register position (Systems 02.03.09.1).
Q Carry is on (Systems 08.00.09.2).
Diagnostic Mode
This lamp is on whenever the diagnostic mode trigger is on (Systems 03.08.17.3).
Overlap Mode
This lamp is on whenever the computer is in overlap mode (Systems 03.08.17.3).
Switches
Switches on the customer engineering test panel aid in trouble shooting machine failures, and in testing the computer in various modes of operation.
I/O Interlock Switch
This switch is effective only with the system in manual.
When both the auto-manual and I/O interlock switches are set to manual, the computer will stop after execut-ing each instruction. When the r/o interlock switches are set to automatic, the machine will not stop if an r/o device is selected to allow normal operation of the r/o unit, but will stop when the channel disconnects.
• •
1!>..
• I'
11"
1 It...
'4~ .,
<J..
Figure 105. CE Panel
Continuous Enter Instruction
This switch is effective in automatic or in manual status. With this switch on, all instructions are ob-tained from the operator's panel keys. If CPU is in auto-matic, pressing the start key causes the instruction in the keys to perform continuously at computer speed.
If CPU is in manual, pressing and holding the multiple step key causes the instruction in the keys to perform at the rate of one every 24 or 104 milliseconds, depend-ing on the settdepend-ing of the multiple-step high-speed low-speed switch. See Figure 106.
Multiple-Step High-Speed L.ow-Speed
With this switch in the high speed position, depressing and holding the multiple step key results in instruc-tions being performed at the rate of one every 24 milli-seconds. With the switch in the low speed position, the rate is one instruction every 104 milliseconds.
Machine Cycle Key
The machine cycle receptacle on the customer engi-neering test panel accepts the machine cycle key (Figure 107). This key is used to step through indi-vidual cycles one at a time. When the machine cycle key is pressed, the machine cycle and cycle gate
trig-Fire Man CtlSS's 04.20.04.1
Set Man Ctl Tgr 04.20.05.1
Reset at A6
CPU in Automatic
Gate I Time
MST Trigger stays off unless:
1. HPR,HTR instruction 2. Divide and Halt instruction
with divide check 3. Mult time error
Figure 106. Continuous Enter Instruction
gers are set (Systems 04.20.10.1). The machine cycle trigger resets the MST trigger, allows the proper cycle time, then sets the MST trigger.
The machine cycle gate trigger allows two shifts per cycle on a shift operation (Systems 02.10.46.1). It also forces a wait until the shift counter equals zero before ending operation in L time (Systems 08.00.02.2),
Bring Up Man I Time Ctl 04.20.10.1 (IG)
A2 (Dl) Reset MST Tgr
Next A3 Reset Mach Cycle Gate Tgr 04.20.10.1 (5G)
End Op Tgr Set at Previous 15.
Retum to "A"
CPU in Manual
End Op Tgr On
No
End Op Tgr Off
Figure 107. Machine Cycle Key
Set Mach Cycle Gate Tgr 04.20.10.1 (3F)
Bring Up Man I Time Ctl
and is used to hold up "manual I-time control" (Sys-tems 08.00.18.2).
When the key is not in use, a plug (sent with the system) that shorts pins one and three must be inserted.
Memory-Diagnostic
This switch, when turned on (up), does not place the computer in diagnostic mode but permits the use of the instructions Enter Diagnostic Mode and Transfer
(EDAT) , and Leave Diagnostic Mode and Transfer
(LDAT). When the computer is in diagnostic mode, ad-dress position three instead of 17 determines which memory is addressed. Diagnostic mode also blocks
XAD to MAR gating (Systems 03.06.28.8). Consequently, only one instruction is fetched from memory during an I cycle. The IBR-Ioaded trigger is not set, and the II cycle following an I cycle must also fetch its instruc-tion from memory. The . switch, when down (off), un-conditionally takes the computer out of diagnostic mode and makes EDAT and LDAT act like a NOP (Sys-tems 03.08.17.3).
No Overlap Switch
This switch when turned up (on) does not take the computer out of overlap mode but permits the use of the instructions Enter Overlap Mode and Transfer
(ELAP), and Leave Overlap Mode and Transfer (LLAP).
The switch, when down (off), places the computer in
Figure 108. Display IBR
Memory Bias
This switch will select either the odd or even memory
Phone Jack
The phone jack, in conjunction with the phone jacks on other units in the system, provides a means of com-munication between customer engineers working at different units.
Memory Nullify
This switch is used with the compatibility package.
When it is in the 16K position, 16K core storage posi-tions are available to the 704 program; in the 24K position, 8K core storage positions are available to the 704 program.
De On
The De on switch controls the 400-cycle power sup-plied only to the 7151 Model 2. Putting this switch in the off position removes all power to the console except the convenience outlets and the reset motor for the operator's keys. All voltages should be normal about ten seconds after turning this switch to the on position.