The Program Counter relative modes refer to a memory address in terms of its distance from the instruction. At execution time, the Program Counter will contain a value 2 greater than the beginning of the instruction, that is, the address of the first byte of extension.
The 68000, 68H C001, 68008, 68302, 68010, 68331, and 68332 microprocessors may address odd memory locations only when the instruction is operating on a single byte. Neither the assembler nor the loader checks for this and in many cases (such as indexed address modes), neither the assembler nor the loader is capable of checking for this situation. The 68020/30/40 have no such
restriction. However, all chips do require that every instruction begin at an even address, and the assembler enforces this. Data may begin at an even or odd address.
The remaining subsections briefly explain the particulars of both the 68000 model modes that apply to all 68000 family processors and the 68020 model modes that apply to the 68020 and later processors.
Register Direct Modes (I & II)
Depending upon the mode, the R egister Direct Modes act directly on the contents of either a data register or an address register.
All other modes specify an address in memory; the contents of this address are used as the instruction operand.
Address Register Indirect (III)
The Address Register Indirect Mode provides the memory address in an address register.
Address Register Indirect with Postincrement (IV)
The Address Register Indirect with Postincrement Mode provides the memory address in an Address R egister and, after using the address, increments the register by one, two, or four, depending upon whether the scope of the operation is byte (.B), word (.W), or longword (.L).
Address Modes
Address Register Indirect with Predecrement (V)
The Address Register Indirect with Predecrement Mode decrements an Address R egister by one, two or four, depending upon whether the size of the operand is byte (.B), word (.W), or longword (.L), and then uses the resulting contents of the register as the memory address. None of the preceding modes require any extension bytes.
Address Register Indirect with (16-bit) Displacement (VI)
In Address Register Indirect with Displacement Mode, the address is the sum of the contents of an address register and a sign-extended 16-bit displacement;
it requires 2 bytes of extension.
Address Reg. Indirect with 8-Bit Displacement and Index (VII, 68000 model)
In Address Register Indirect with Displacement and Index Mode the address is the sum of the contents of an Address R egister, the contents of an Index R egister (which may be an Address or a Data R egister) and a sign-extended 8-bit displacement. It requires 2 bytes of extension. The Index R egister involved may use either all 32 bits or 16 bits sign-extended.
Address Reg. Indirect with 8-Bit Displacement and Index (VIIa, 68332/020 model)
In addition to the capabilities of the 68000 model, the 68332 model and the 68020 model allow the Index R egister contents to be multiplied by a scale factor of 1, 2, 4, or 8 before being added to the Address R egister contents. The scale factor is coded into bits 9 and 10 of the specially formatted extension word. In the 68000 model mode (VII), the scale factor is always 1.
Address Reg. Ind. with Base Displ. and Index (VIIb, 68332/020 model)
The Address Register Indirect with Base Displacement and Index Mode calculates the memory address as the sum of the contents of an Address R egister, the contents of an Index R egister (which may be an Address or a Data R egister) and a sign-extended base displacement which may be either 16 or 32 bits. This mode requires at least 2 bytes of extension, plus 2 more for a 16-bit displacement or 4 more for a 32-bit displacement. The Index R egister involved may use either all 32 bits or 16 bits sign-extended. The Index R egister Address Modes
contents may be multiplied by a scale factor of 1, 2, 4, or 8 before being added to the Address R egister contents. Any or all of the Address R egister, Index R egister and displacement may be specified to be null, in which case they are taken to have a value of 0. A null displacement does not require any extension bytes.
Memory Indirect Post-Indexed (VIIc, 68020 model)
The Memory Indirect Post-Indexed Mode first calculates an intermediate address as the sum of the contents of an Address R egister and a sign-extended base displacement which may be either 16 or 32 bits. The final memory address is then calculated as the sum of the contents of the intermediate address, the contents of an Index R egister (which may be an Address or a Data R egister), and an outer displacement which may be either 16 or 32 bits. This mode requires at least 2 bytes of extension, plus 2 more for each displacement which is 16 bits and 4 more for each displacement which is 32 bits. The Index
R egister involved may use either all 32 bits or 16 bits sign-extended. The Index R egister contents may be multiplied by a scale factor of 1, 2, 4, or 8 before being added to the intermediate address contents and the outer displacement.
Any or all of the Address R egister, Index R egister, base displacement and outer displacement may be specified to be null, in which case they are taken to have a value of 0. Null displacements do not require any extension bytes.
Memory Indirect Pre-Indexed (VIId, 68020 model)
The Memory Indirect Pre-Indexed Mode first calculates an intermediate address as the sum of the contents of an Address R egister, an Index R egister (which may be an Address or a Data R egister), and a sign-extended base displacement which may be either 16 or 32 bits. The final memory address is then calculated as the sum of the contents of the intermediate address and an outer displacement which may be either 16 or 32 bits. This mode requires at least 2 bytes of extension, plus 2 more for each displacement which is 16 bits and 4 more for each displacement which is 32 bits. The Index R egister
involved may use either all 32 bits or 16 bits sign-extended. The Index R egister contents may be multiplied by a scale factor of 1, 2, 4, or 8 before being added to the Address R egister contents and the base displacement. Any or all of the Address R egister, Index R egister, base displacement and outer displacement may be specified to be null, in which case they are taken to have a value of 0.
Null displacements do not require any extension bytes.
Address Modes
Absolute Short (VIII)
The Absolute Modes provide an actual memory address right in the
instruction. For Absolute Short Mode this address is 16 bits sign-extended (2 bytes of extension). Because 16-bit addresses are sign-extended, the areas of memory addressable by Absolute Short Mode are from 0 to $7FFF plus an area in high memory, the address range of which is dependent on the target chip (from $FF8000 to $FFFFFF for the 68000 and 68010, from $F8000 to
$FFFFF for the 68008, and from $FFFF8000 to $FFFFFFFF for the 68020/30/40).
R egardless of the target chip, the assembler recognizes only the absolute addresses from $FFFF8000 to $FFFFFFFF as being in the high
short-addressable area of memory. (If it is necessary to use Absolute Short Mode on the actual area of high memory that is short-addressable on the target chip, any absolute code should be placed in a separate module and referenced as XR EF.S from other modules, which technique causes the use of Absolute Short address mode in most cases. Alternatively such code could be made relocatable and placed in a SECTION.S, then located correctly at link time; in this case the high-short-addressable code need not be in a separate module.)
Absolute Long (IX)
The Absolute Modes provide an actual memory address right in the instruction. Absolute Long Mode contains a full 32-bit address in the
instruction and can thus address any memory location on any chip (4 bytes of extension).
Program Counter with Displacement (X)
The Program Counter Indirect with Displacement Mode calculates the memory address by adding the value of the Program Counter to a sign-extended 16-bit displacement; it requires 2 bytes of extension.
Program Counter with 8-Bit Displacement and Index (XI, 68000 model)
The Program Counter Indirect with 8-bit Displacement and Index Mode calculates the memory address by adding the value of the Program Counter, the contents of an Index R egister (which may be Address or Data, and may use Address Modes
the entire 32 bits or the low order 16 bits, sign-extended), and a sign-extended 8-bit displacement; it requires 2 bytes of extension.
Program Counter with 8-Bit Displacement and Index (XIa, 68332/020 model)
The 68332 model and 68020 model allow the Index R egister contents to be multiplied by a scale factor of 1, 2, 4, or 8 before being added to the other components. The scale factor is coded into bits 9 and 10 of the specially formatted extension word. In the 68000 model mode (XI), the scale factor is always 1.
PC with Base Displacement and Index (XIb, 68332/020 model) The Program Counter Indirect with Base Displacement and Index Mode calculates the memory address by adding the value of the Program Counter, the contents of an Index R egister (which may be Address or Data, and may use the entire 32 bits or the low order 16 bits, sign-extended), and a sign-extended displacement, which may be either 16 or 32 bits. This mode requires at least 2 bytes of extension, plus 2 more for a 16-bit displacement or 4 more for a 32-bit displacement. The Index R egister may be multiplied by a scale factor of 1, 2, 4, or 8 before being added to the other components. Any or all of the Address R egister, Index R egister, and displacement may be specified to be null, in which case they are taken to have a value of 0. A null displacement does not require any extension bytes.
PC Memory Indirect Post-Indexed (XIc, 68020 model)
The Program Counter Memory Indirect Post-Indexed Mode first calculates an Intermediate address as the sum of the contents of the Program Counter and a sign-extended base displacement which may be either 16 or 32 bits. The final memory address is then calculated as the sum of the contents of the
Intermediate address, the contents of an Index R egister (which may be an Address or a Data R egister), and a sign-extended outer displacement which may be either 16 or 32 bits. This mode requires at least 2 bytes of extension, plus 2 more for each displacement which is 16 bits and 4 more for each displacement which is 32 bits. The Index R egister involved may use either all 32 bits or 16 bits sign-extended. The Index R egister contents may be
multiplied by a scale factor of 1, 2, 4, or 8 before being added to the
Intermediate address contents and the outer displacement. Any or all of the Program Counter, Index R egister, base displacement and outer displacement
Address Modes
may be specified to be null, in which case they are taken to have a value of 0.
Null displacements do not require any extension bytes.
PC Memory Indirect Pre-Indexed (XId, 68020 model)
The Program Counter Memory Indirect Pre-Indexed Mode first calculates an Intermediate address as the sum of the contents of the Program Counter, an Index R egister (which may be an Address or a Data R egister), and a
sign-extended base displacement which may be either 16 or 32 bits. The final memory address is then calculated as the sum of the contents of the
Intermediate address and a sign-extended outer displacement which may be either 16 or 32 bits. This mode requires at least 2 bytes of extension, plus 2 more for each displacement which is 16 bits and 4 more for each displacement which is 32 bits. The Index R egister involved may use either all 32 bits or 16 bits sign-extended. The Index R egister contents may be multiplied by a scale factor of 1, 2, 4, or 8 before being added to the Program Counter contents and the base displacement. Any or all of the Program Counter, Index R egister, base displacement and outer displacement may be specified to be null, in which case they are taken to have a value of 0. Null displacements do not require any extension bytes.
Immediate (XII)
The final address mode provides data directly in the instruction (Immediate Mode). The number of bits used and the number of bytes of extension varies with the instruction and with the qualifier. Immediate data is always evaluated first as a 32-bit unsigned two’s complement value. If the instruction requires fewer than 32 bits, the most significant bits are checked and discarded. If the bits discarded are all 0 or all 1, the instruction assembles normally, while if the bits discarded are mixed zeros and ones, a warning is printed. The immediate operands of ADDQ, SU BQ , TR AP, BKPT and all Shifts (which are smaller than a byte) may not be relocatable or external. All other immediate operands may be relocatable or external.