Installation and Configuration
2.5 H3602-SA CPU Cover Panel
3.1.4 Exception Handling Registers
Exceptions are handled through the use of six coprocessor zero (CPO) registers and one module specific interrupt status register. Software uses these registers during exception handling to determine the cause of the exception. These registers are described in the following sections.
3.1.4.1 Cause Register
The cause register (CR) is a 32-bit register used when servicing exceptions. It describes why the last exception was taken. All bits in this register are read only except for the SW bit. The format for the cause register is shown in Figure 3-8.
SO ZERO
3130 2928 27
ZEROS
Figure 3-8 Cause Register Data Bit Definition
16 15 10 9 8 7 6 5 2 1 0
ZEROS - - - '
MA-X0656-8V
CR<31> (BD) Branch delay. Set to 1 if last exception was taken while executing in a branch delay slot.
CR<30> Unused. Read as zero.
CR<29:28> CE<1:0> Coprocessor error. Indicates the unit number referenced when a coprocessor unusable exception is taken.
CR<27:16> Unused. Read as D's.
Data Bit CR<15:10>
CR<7:6>
CR<5:2>
CR<1:0>
Architecture 3-13
Definition
IP<5:0> Interrupt pending. Indicates which of the external interrupts are pending. Table 3-2 shows the mapping of physical interrupt requests to the cause register IP<5:0> status bits. Figure 3-9 shows the flow of the interrupt acknowledge daisy chain.
SW <1:0> Software interrupts. Indicates which software interrupts are pending. These bits are read/write.
Unused. Read as O's.
(EC) Exception code. The exception code field is described in the following table.
Number Name Description 0(10) INT External interrupt
1 MOD TLB modification exception 2 TLBL TLB miss exception Ooad or fetch) 3 TLBS TLB miss exception (store)
4 ADEL Address error exception (load or fetch) 5 ADES Address error exception (store) 6 IBE Bus error exception (fetch) 7 DBE Bus error exception Ooad or fetch)
8 SYS Syscall exception
9 BP Breakpoint exception
10 RI Reserved instruction exception 11 CPU Coprocessor unusable exception 12 OVF Arithmetic overflow exception 13-15 Reserved
Unused. Read as O's.
Table 3-2 R3000 Interrupt Mapping
Vector Bit Priority Interrupt Request Register IP<5> 2 FPU
IP<4> 1 HALT
IP<3> 3 PWRFL, MER1, MERO, WEAR
IP<2> 4 100 Hz ->BIRQ7 VRR3 IP<l> 5 nSSI ->NI ->BIRQ6 VRR2 IP<O> 6 BIRQ5 ->Console ->Timers VRR1
->BIRQ4
PROCESSOR MODULE
R3000
VRRO
100 Hz CLOCK
NO 110 ~ MODULE / '
-I
Q22·bu.
Figure 3-9 Interrupt Acknowledge Daisy Chain
Corresponding Diagnostic Processor IPL
IPL17 IPL16 IPL15 IPL14
110 MODULE
IoIA-XO,,8.88
Architecture 3-15
3.1.4.2 Exception Program Counter
The exception program counter (EPC) contains the virtual address of the instruction which caused the exception to be taken. If the instruction is in a branch delay slot, the EPC will contain the virtual address of the preceding branch or jump instruction.
3.1.4.3 Status Register
The status register (SR) is a 32-bit register containing various processor status. The format for the status register is shown in Figure 3-10.
31 29 27 23 22 21 20 1 9 18 17 16 15 8 7 6 5 4 3 2 o
MA-X062&-18
Figure 3-10 Status Register Data Bit Definition
SR<31:28> CU<3:0> Coprocessor usability. CU<3:0> controls the availability of the four possible coprocessors. Setting a CU bit to 1 enables the coprocessor.
SR<27:23> Unused_ Read as O's.
SR<22> (BEV) Bootstrap exception vector. When set to 1 causes the R3000 to use the alternate bootstrap vectors for UTLB miss and general exceptions.
SR<21> (TS) Translation buffer shutdown. Set to 1 if the RaOOO has disabled the translation buffer due to error.
SR<20> (FE) Parity error. Set to 1 if a cache parity error occurs.
Cleared by writing a 1.
SR<19> (CM) Cache miss. Set to 1 if most recent D-cache load resulted in a miss when the D-cache is isolated.
SR<18> (PZ) Parity zero. Setting to 1 forces parity bits to
o.
SR<17> (SWC) Swap caches. Swaps I-cache and D-cache.
Data Bit
SR<15:10>
SR<7:6>
SR<5>
SR<4>
SR<3>
SR<2>
Definition
(lSC) Isolate cache. Isolates the D-cache from the memory system.
INTR<7 :2> Interrupt mask. Setting these INTR bits to 1 enables their corresponding hardware interrupt.
INTR<1:0> Interrupt mask. Setting these INTR bits to 1 enables their corresponding software interrupt.
Unused. Read as O's.
(KUO) Kernel/user mode, old. Set to 0 if kernel, 1 if user.
(lEO) Interrupt enable, old. Set to 1 to enable, 0 to disable.
(KUP) Kernel/user mode, previous. Set to 0 if kernel, 1 if user.
(IEP) Interrupt enable, previous. Set to 1 to enable, 0 to disable.
(KUC) Kernel/user mode, current. Set to 0 if kernel, 1 if user.
(IEC) Interrupt enable, current. Set to 1 to enable, 0 to disable.
3.1.4.4 BadVaddr Register
The BadVaddr register (BVA) saves the virtual address for any addressing exception.
3.1.4.5 Context Register
The context register (CR) is used by the UTLB miss handler. The CR saves some of the same information as the BadVaddr register. The format for the context register is shown in Figure 3-11.
31 21 20 2 1 0
PTEBase BadVPN
MA-X0627-80
Figure 3-11 Context Register
Architecture 3-17
Data Bit CR<31:21>
CR<20:2>
Definition
(PTEBase) Page table entry base. Holds the base for the page table entry.
(BadVPN) Bad virtual page number. Holds the failing virtual page number. Read only. Set by hardware.
Unused. Read as O's.
3.1.4.6 Processor Revision Identifier Register
The processor revision identifier register (PRR) contains implementation and revision numbers for the RaOOO chip. The format for the processor revision identification register is shown in Figure 3-12.
31 16 15 8 7
PTEBase IMP REV
o
MA-X0652-811
Figure 3-12 Processor Revision Identifier Register Data Bit Definition
PRR<31:16> Unused. Read as O's.
PRR<15:8> IMP<7:0> Implementation identifier.
PRR<7:0> REV<7:0> Revision identifier.
3.1.4.7 Interrupt Status Register
The interrupt status register, (RaOOO address 1008 4000; diagnostic processor address 2008 4000) returns information concerning the four conditions which can cause an INTRa interrupt. It can be accessed by either processor but only has meaning for the RaOOO. The diagnostic processor must make sure ISR<2:0> are 0 before transferring control to the RaOOO. The format for the interrupt status register is shown in Figure 3-13.
31
READ AS ONES
Figure 3-13 Interrupt Status Register Data Bit Definition
18R<31:4> Unused. Read as 1's.
HALT PRFL
3 2 1 0
MER1 _ _ _ ....
M E R O - - - '
MA-X0628-8Q
18R<3> (HALT) Halt interrupt. Indicates a halt interrupt request is posted.
18R<2> (PRFL) Power fail interrupt. Indicates an impending power fail condition. Must be written zero (0) to enable subsequent power fail interrupts. Cleared on powerup.
18R<1> (MER1) Memory error one. Indicates a memory error interrupt has been generated either by the CQBIC or the CMCTL. Must be written as zero (0) to enable subsequent CQBIC or CMCTL memory error interrupts. Cleared on powerup.
18R<0> (MERO) Memory error zero. Indicates a write error has occurred and that the address contained in the WEAR register is valid. Must be written as 0 to enable subsequent MERO interrupts. Cleared on powerup.
3.1.4.8 Vector Read Registers
The RaOOO uses the vector read registers when servicing IRQ<2:0>
interrupt requests. Reading any of these registers generates an interrupt acknowledge cycle on the peripheral bus (CP bus). Bits <15:0> of the data returned will be a unique vector from the device responding to the interrupt acknowledge. If no device responds, a BUS ERROR EXCEPTION will be taken by the RaOOO.
Architecture 3-19
System software must guarantee interrupt requests from higher priority devices service before lower priority devices. This can be accomplished by reading the VRR register corresponding to the highest IRQ<2:0> pending in the cause/status register. The diagnostic processor has no access to these registers.
Register VRRO VRRI VRR2 VRR3 NOTE
JPL Generated 14 (lowest priority) 15
16
17 (highest priority)
Because of the way interrupt requests are posted on the Q22-bus, interrupts at high priorities will also assert interrupt requests at lower levels. It is important that software read the VRR register corresponding to the highest IRQ pending in the CAUSE register.
Lower level requests pending because of higher level interrupts will deassert at the same time the high level request deasserts.
Vector Read Register 0
Vector read register 0 (VRRO) cannot be accessed by the diagnostic processor. The format for VRRO (R3000 address 1600 0050) is shown in Figure 3-14.
31 16 15
READ AS ONES IPL 14 VECTOR INFORMATION
o
MA-XOS29-89
Figure 3-14 Vector Read Register 0
Vector Read Register 1
Vector read register 1 (VRR1) cannot be accessed by the diagnostic processor. The format for VRRI (R3000 address 1600 0054) is shown in Figure 3-15.
31 1615
READ AS ONES IPL 15 VECTOR INFORMATION
o
MA-X0647-SI1
Figure 3-15 Vector Read Register 1 Vector Read Register 2
Vector read register 2 (VRR2) cannot be accessed by the diagnostic processor. The format for VRR2 (R3000 address 1600 0058) is shown in Figure 3-16.
31 16 15
READ AS ONES IPL 16 VECTOR INFORMATION
o
MA-X0648-SI1
Figure 3-16 Vector Read Register 2 Vector Read Register 3
Vector read register 3 (VRR3) cannot be accessed by the diagnostic processor. The format for VRR3 (R3000 address 1600 005e) is shown in Figure 3-17.
31 16 15
READ AS ONES IPL 17 VECTOR INFORMATION
o
MA-X084I1-SI1
Figure 3-17 Vector Read Register 3
Architecture 3-21
3.1.5 Exceptions
The R3000 handles exceptions through the use of three different exception vectors. These exception vectors are the following:
• BFCO 0000 virtual - RESET exception vector.
• 8000 0000 virtual - UTLB miss exception vector.
• 8000 0080 virtual - General exception vector.
If the bootstrap exception vector (BEV) bit is set in the status register then the UTLB and general exception vector addresses will be changed, putting them in the ROM address space.
• BFCO 0100 virtual- UTLB miss exception vector.
• BFCO 0180 virtual - General exception vector.
3.1.5.1 General Exception Vector
The general exception vector handles the following exceptions:
•
Address error•
Breakpoint•
Bus error•
Coprocessor unusable•
Interrupt•
Overflow•
Reserved instruction•
TLB miss•
TLB modified3.1.5.2 Reset Exception Vector
The reset exception is taken on power up when the R3000 RESET signal is deasserted. The reset vector (BFCO 0000 virtual) resides in Kseg1 which is unmapped and uncached. It is also the first location in the ROM (physical IFCO 0000).
When the reset exception occurs, the contents of all R3000 registers are undefined except for the following:
• The TS, SWc, KUc, and IEc bits of the status register are cleared.
• The BEV bit of the status register is set.
• The random register is cleared.
3.2 Floating-Point Accelerator
The KN210 floating-point accelerator (FPA) is implemented by a single VLSI chip called the RaOIO. The R3010 FPA operates as a coprocessor for the RaOOO RISe processor and extends the R3000's instruction set to perform arithmetic operations on values in floating-point representations.
The R3010 FPA features 16 64-bit registers that can each be used to hold single-precision or double-precision values. The FPA also includes a 32-bit status/control register.
The 3010 FPA connects to the R3000 RISe processor to form a tightly-coupled unit with complete integration of floating-point and fixed-point instruction sets. Since each unit receives and executes instructions in parallel, some floating-point instructions can execute at the same single-cycle per instruction rate as fixed-point instructions.