One of the ideas behind irnplementing oscillators along the sides of the die was to allow an interpolation of process variations for regions at the core of the die, based on measured values at die sides. The four sides were chosen because they provide a linear coverage of
the two plane dimensions, X and Y. The hope was to be able to interpolate a surface repre- sentation of the plane based on linear measurements. Our experimental results show that this is unfortunately not possible, based on two main observations:
i. A pattern of period variations seem to repeat itself throughout the wafer. Figure 13 shows the variations of clock penod along 5 adjacent dies in the X & Y directions, for two different wafers. Measured periods of 20 cells per die (one side) are represented in both directions. One can clearly notice the "periodicity" of the dock period vaIues with the position in both directions. An intuitive a prion explanation of such a perio- dicity is proposed in the following. If we recall that inside the die, several unrelated designs of other users are implemented in a multi-project fabrication run (Fig. 5.7), it becomes clear that the electrical environment dong a given die side varies when we move from end to end. However, since it is obvious that oscillation cells located at the same position in al1 dies have identical electrical environrnents (dies are replicated over the wafer), moving along an orthogonal direction, such as X-mis or Y-axis, over more than one die, will lead to the same environment every 20 cells (total number of cells implemented along one die side). Indeed, the clock period behaves as if it was modulated or shaped by the electrical devices in the immediate environment of the oscillation cells along the die side. However, it tends to return back to approximately the same value every 20 positions, and the sudden increases and decreases happen approximately at the same positions within the period over the 5 die sides. The pres- ence of a pattern is confirmed by the values of the correlation coefficients between the
5 spatial periods (consecutive groups of 20 observations) taken two by two in X direc- tion. We obtain correlation values as high as 0.61 (first and second periods), 0.76 (sec- ond and third periods), 0.77 (third and fourth periods), and 0.73 (fourth and fifth periods). Consequently, interpolating the intemal regions from the die borders, which might have different electrical environments, seems to be unfeasible in presence of an environmental component of this nature and magnitude.
ii. Important variations occur even for oscillators that are immediate neighbors. This phenomenon is shown in Fig. 5.14, where the clock periods of oscillators implemented along adjacent sides of two neighbor dies across scribe lines2 are compared. The mag- nitude of period variations, when moving across the scribe line, exceeds 20% of the average period. This can again be explained by the difference in environment of any couple of neighbors. This shows how sudden the spatial process variation can be even over short distances (700pm ). Note that the distance between two neighbors along the same die side is comparable to that between two neighbors (each belonging to a differ- ent die) across the scribe line. Calculation of correlation coefficients shows in fact that imrnediate neighbors across scribe lines are not as highly correlated (as low as 0.55 for horizontal sides). This observation reinforces the conclusion that it is unfeasible to interpolate the amplitude of process variations, from a region to another one over a die.
2. These are pre-deterrnined virtual Iines along which cuts are made in the wafer to separate the dies.
There is a scribe line between any adjacent pair of dies (along their adjacent sides).
With current design strategies, the presence of the environmental variation described above seems to be inevitable. Indeed, it is intrinsic to the fact that a clock distribution net- work, for instance, is always surrounded by the logic it feeds. The dock period "periodic- ity" mentioned earlier leaves little doubts about the direct influence of environment variability on the time period of oscillation cells. This variability is due to the fact that inside the square ring (Fig. 5.5) of oscillation cells (delirniting the die), designs of other users are implemented (Fig. 5.7). Consequently, each ce11 faces a region with different electrical characteristics. Depending on which electronic devices the designer implements in the surroundings of a clock distribution network, some regions of the tree will be faster than others. Note that even though a chip designer has the knowledge of the nature and position of the devices he implements, the effect of these devices on the close neighbor active logic of the clock distribution network, when fabricated under a real manufacturing process, remains unknown. In this paper, this effect is calIed the "environment" phenom- enon. Therefore, in absence of knowledge, considering the transistor time constant (or other similar characteristics influencing parametric performances of digital or analog inte- grated circuits) as a random variable (as we did in Table 5. l ) , seems realistic.
The "environment" effect c m be understood as a gencralization of the "edge" effect mentioned by Pavasovic et al. [ I l ] and Andreou et al. [12]. This "edge" effect was observed as occuring only at the edges of a transistor array [ I l , 121. According to these authors, a probable cause of this effect is strain induced shifts in the characteristics of the devices. During the annealing processes, stress in the middle of the transistor array tends
to propagate outward and accumulates in the periphery. Based on our findings, an alterna- tive to the above explanation would be again the environmental variation. In fact, "edge"
effects were observed in [ I l , 121 both at the inner borders of a cluster of arrays as well as at the outer borders of the arrays. In their experiment, transistors in an array have the same size, and they are directly abutted to each other. Moreover, transistors in different arrays have different sizes. Therefore, the arnount of inter-space between transistors varies only at the borders between the arrays. Also, transistors at outer array borders face open areas, while transistors inside the array have other transistors acting as their environment. Note that such an effect was not observed inside the arrays [ I l , 121, again because of the uni- forrnity of transistor environment in those regions.