AC Characteristics and Timing Diagrams of MK4116·3
R EAD-WR ITE/R EAD-MOD I FY -WR ITE CYCLE
1 C - - - t R W C /t R I o t W - - - . ;
RAS
t RSH
t CSH
----+'_----:--
t CAS - - - tCAS
DOUT
"RAS-ONLY" REFRESH CYCLE
NOTE: CAS = VIHC, WRITE = Don't Care
1 - + - - - -l R C - - - . . . ,
1 - + - - - - l R A S
-RAS V'HC--- - - ,
IL
"""'" :,~:W;$$/~ '''':;;,:"'"k;$E;EEEE;~-!l/J;~lI~ffi
VOH-_ _ _ _ _ _ _ _ OPEN _ _ _ _ _ _ _ _ _ _
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PAGE MODE READ CYCLE
(RAS
---~.~1~
I'---:--:---~---J'
.f-'-:-1~---~j~::J-RAS V1HC _
V,L
-CAS V1HC _
V,L-DOUT
I
( RAC ---~-~VOH-______________
-:-I_
0 PEN'0'- '"":I. L
~::W!ll!ll 1/
~tcAcl~
re-t OFF
~-(-O-F-F---,~J~
11l1li///////1;
PAGE MODE WRITE CYCLE
~---tRAS ---~
I
RAS
VIHCV1L
V1HC
-CAS VIL
-ADDRESSES VIH -VIL
-WRITE V1HC
V 1L
-DIN V 1H -V 1L
-V--63
DESCRIPTION (continued)
System oriented features include ± 10% tolerance on all power supplies, direct interfacing capability with high performance logic families such as Schottky TTL, maximum input noise immunity to minimize
"false triggering" of the inputs (a common cause of soft errors), on-ch ip address and data registers wh ich eliminate the need for interface registers, and two chip select methods. The MK 4332 also incorporates several flexible timing/operating modes. In addition to the usual read, write, and read-modify-write cycles, the MK 4332 is capable Ldelayed write cycles, page-mode operation and RAS-only-Efresh.
Proper control of the clock inputs( RAS, CAS and WRITE) allows common I/O capability, two dimen-sional chip selection,and extended page boundaries (when operating in page mode). latches by externally applying two negative going TTL-level clocks. The first clock, the Row Address se-quence are inhibited until the occurence of a delayed signal derived from the RAS clock chain. This "gated CAS" feature allows the CAS clock to be externally activated as soon as the Row Address Hold Time specification (tRAH) has been satisfied and the -ad-dress inputs have been changed from Row ad-ad-dress to Column address information.
Note that CAS can be activated at any time after throughout the portion of the memory cycle in wh ich CAS is active (low). Data read from the selected cell back to the inactive (high level) condition.
Since the outputs to both 16K devices are tied to-gether, care must be taken with the timing relatio~
ships of the two devices. Both devices cannot be acti-vated at the same time as a data output conflict can Onc.1.-having gone active, the output will. remain valid until CAS is taken to the precharge (logic
1)
state,whether or not RAS goes into precharge.l.L.1.b.Lcycle in progresLii an "earlx-write" cycle (WR ITE active before CAS goes active), then the memory cycle time (stretching the cycle).
This type of output operation results in some very significant system implications.
Common I/O Operation - If all write operations are
with lJQ..jJenaltyin cycle time. This also makes the RAS/CAS clock timing relationship very flexible.
Two Methods of Chip Selection - Since DOUT
Extended Page Boundary - Page-mode operation allows for successive memory cycles at mu Itiple column locations of the same row address. By de-coding
CAS
as a page cycle select signal, the page boundary can be extended beyond the 128 column locations in a single chip. (See page-mode operation).OUTPUT INTERFACE CHARACTERISTICS The three state data output buffer presents the data output pin with a low impedance to VCC for a logic 1 and a low impedance to VSS for a logic
O.
The effective resistance to V CC (logic 1 state) is 420 n maximum and 135n typically. The resistance to VSS (logic 0 state) is 95 n maximum and 35 n successive memory operations at mu Itiple column locations of the same row address with increased speed without an increase in power. This is done by strobing the row address into the chip and maintain-ing the RAS signal at a logic 0 throughout all success-ive memory cycles in which the row address is com-mon. This "page-mode" of operation will not dissi-pate the ...Q.Q..wer associated with the negative going edge of RAS. Also, the time required for strobing in a new row address is eliminated, thereby decreas-ing the access and cycle times.The page boundary of a single MK 4116 is limited to as a page cycle select signal. Only those devices which receive both RAS and CAS signals will execute a read or write cycle.
REFRESH
Refresh of the MK4116 is accomplished by perform-ing a memory cycle at each of the 128 row addresses within each 2 millisecond time interval. Each MK4116 in the MK4332 Assembly must receive all 128 refresh cycles within the 2ms time interval in order to completely refresh all 32,768 memory cells.
Although any normal memory cycle will perform the refresh . operation, this function is most easily accomplished with "RAS-only" cycles. RAS-only re-fresh resuls in a substantial reduction in operating address strobe edge. Consequently, the dynam ic power is primarily a function of operating frequency rather than active duty cycle (refer to the MK 4116
Although no particular power supply noise r~stri~ti~n exists other than the supply voltages remain within the specified tolerance limits, adequate decoupling should be provided to suppress high frequency noise resulting from the transient current of the device. This insures optimum system performance and reliability. Bulk capacitance requirements are minimal since the MK 4332 draws very little steady state (DC) current.
In system applications requiring lower power dissi-pation . the operating frequency (cycle rate). of th~ operating frequency, for example
1
microsecond cycle, results in a reduced maximum I DD 1 require-ment of under 20m A with an ambient temperature range from 0° to 70° C.NOTE:' Additional power supply tolerance has been included on the VSS supply to allow direct interface capability with both·-5V systems -5.2V ECl systems.
Fig. 5 Typical Current Waveforms for the MK 4116
"
50 NANOSECONDS I DIVISION
i
11
I
V-65
Although RAS and/or CAS can be decoded and used as a chip select signal for the MK 4116,overall system power. is minimized if the Row Address Strobe (RAS) is used for this purpose. Al.!...!!.riselected de-vices (those which do not receive a RAS) will remain in a lo~ower (standby) mode regardless of the state of CAS.
POWER UP
The MK 4332 requires no particular power supply sequencing so long as the Absolute Maximum Rating Conditions are observed; However, in order to insurE compliance with· the Absolute Maximum .Ratings, MOSTE K recommends sequencing of power supplies
such that VBB is applied first and removed last.
VBB should never be more positive than VSS when power is applied to VDD.
Under system failure conditions in which one or more supplies exceed the specified limits significant addi-tional marginagJlinst catastrophic device failure may be achievea by lorcing
RAS
and CAS to the inactive state (high level).After power is applied to the device, the MK 4332 requires several cycles before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose. Each MK 4116 device must receive the
8
initialization cycles.V-66
TYPICAL CHARACTERISTICS OF THE MK 4116
TYPICAL ACCESS TIME (NORMALIZED) vs. VOO
TJ=SO"C
--- ...
-...
r---10 11 12 13 14
Voo SUPPLY VOLTAGE (VOLTS)
TYPICAL ACCESS TIME (NORMALIZEO) \'S. VaB
TJ "SO"C
-4.0 -4.S 5.0 5.5 6.0
VaB SUPPLY VOLTAGE (VOLTS)
TYPICAL ACCESS TIME (NORMALIZEO) VI VCC
~ 1.1 TJ=SO'C
Vce SUPPLY VOLTAGE (VOLTS)
1.2
TYPICAL ACCESS TIME (NORMALIZED) s JUNCTION TEMPERATURE
,.
/
/ /
/ /
20 50 80 110
T J, JUNCTION TEMPERATURE (" C)
TYPICAL 1001 'IS. Voe
VOO SUPPLY VOLTAGE (VOLTS)
TYPICAL 1002 '1$ VOO
TJ= 50"C
-~
-I-0.4
10 11 12 13 14
VOO SUPPLY VOLTAGE (VOLTS)
TYPICAL 1003 vs. VOO
Voo SUPPLY VOLTAGE (VOLTS)
V-67
TYPICAL 1001 vs JUNCTION TEMPERATURE 5
TJ, JUNCTION TEMPERATURE (·e)
TYPICAL 1002 vsJUNCTION TEMPERATURE
Vee "13.2V
0.4 -10
-- r--- --
r--20 50 BO 110
TJ, JUNCTION TEMPERATURE ("cl
TYPICAL 1003 'IS JUNCTION TEMPERATURE
°lvOO
=13.2VTJ.JUNCTION TEMPERATURE ('C)
TYPICAL 1004 vs. JUNCTION TEMPERATURE 20
TJ,JUNCTION TEMPERATURE ("C.
3.0
TYPICAL CLOCK INPUT LEVELS vs. VOO TJ -50OC
VOO SUPP,L,YY.OLTAGE {Vt?LTSI
TYPICAL AOORESSANO DATA INPUT LEVELS ¥s. VDO 3.0
Voo SUPPLY VOLTAGE {VOL TSI
TYPICAL CLOCK INPUT LEVELS ¥S 'VSB
VSS SUPPLY VOLTAGE (VOL TSI
TYPICAL ADDRE.iS AND DATA INPUT LEVELS VI. VSS 3. 0 Vsa SUPPLY VOLTAGE (VOL TSJ
V-68
• TYPICAL CLOCK INPUT LEVELSvs; TJ 3.0 ,--'-:..:..::;:,:.:.=-'--,----,--"---,
TJ. JUNCTION TEMPERATURE {OCI
TYPICAL ADDRESS AND DATA INPUT LEVELS VI. TJ 3.0
TJ. JUNCTION TEMPERATURE loel
FEATURES
o Recognized industry standard 16-pin configuration from Mostek
o 120ns access time, 265ns cycle time (MK4164-12) 150ns access time, 325ns cycle time (MK4164-15) o Indefinite DOUT hold using CAS control
DESCRIPTION
The MK4164 is the new generation dynamic RAM, organized 65,536 words by 1 bit, it is the successor to the industry standard MK4116. The MK4164 utilizes Mostek's Scaled Poly 5 process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Per-formance previously unachieved will be the standard for this new generation device. The use of dynamic circuitry throughout, including the 512 sense amplifiers, assures that power dissipation is minimized without any sacrifice in speed or internal and external operating margins. Refresh characteristics have been chosen to maximize yield (low cost to user) while maintaining compatibility between dynamic RAM generations·.
Multiplexed address inputs (a feature dating back to the industry standard, MK4096, 1973) permits the MK4164 to be packaged in a standard 16-pin DIP with only 15 pins required for basic functionality. Mostek is utilizing this spare pin for a new refresh feature. The MK4164 is designed to be compatible with the JEDEC standards for the 64K x 1 dynamic RAM. The compatibility with the MK4516 (16K) will also permit a common board design to service both the MK4516 and MK4164 designs.
The output of the MK4164 can beheld valid indefinitely by holding CAS active low. This is quite useful since a refresh cycle can be performed while holding data valid from a previous cycle.