AUTO REFRESH MODE

- V 1H - DON'T CARE'

CE

v

_1L

-tCSRI~ __ ~ ~----+---tRDA---~ ~~~

____ VIH _ RFSH V _IL

-Internal Auto Refresh Mode

tARA ~--... ---- Single Refresh Cycle Approximately Every 15 }Jsec Only RFSH Input Recognized In Auto Refresh Mode

VII-6

-OPERATION ADDRESSING

The 11 address bits required to decode 8 of the 16,384 memory cell locations within the MK4816 are latched into the on-chip address latches by the high-to-Iow transition of Chip Enable (eE). Thus, the unique address specified by the 11 Address Inputs (An) define which 1 of 2048 bytes of data is to be accessed. Chip Enable also latches internally the state of Chip Select (CS). For a device to be selected, CS must be high during the high-to-low transition of CEo After the specified hold time, the Addresses and CS may be changed in anticipation ofthe next cycle.

ACTIVE CYCLES

The MK4816 can perform three types of active cycles, determined by user control of CE, OE, CS, WE, and RFSH. The cycles are READ, WRITE, and REFRESH. The MK4816 executes an automatic precharge atthe end of any active cycle in preparation for the next active cycle.

After the automatic precharge cycle is complete, the device will be in the standby mode until another active cycle is initiated.

READ CYCLE

A READ CYCLE is initiated by Chip Enable (CE) going low with Chip Select (CS) High and Write Enable (WE) high.

The cycle is complete when data is output(OE

=

^{LOW) or}

by CE going high. Completion of the cycle initiates the automatic precharge cycle.

Data Out will become valid at access time provided that Output Enable (OE) is low. If OE is high at access time valid data will not appear at the output terminals although the data will be available to the output data buffers. Access time from OE is approximately 36% of CE access time, allowing adequate time for system decode of OE.

At the end ofthe READ CYCLE, CE going high unlatches the output. The trailing edge of CE is non-critical in that it can be taken high any time after meeting the minimum CE pulse width (tCE).

After valid data is output (CE

=

OE

=

LOW t:2: tACCESS), the MK4816 will initiate an automatic precharge cycle in preparation for the next active cycle. If OE does not go low to permit valid data out, precharge will be initiated by CE going high. The next active cycle may be initiated after the minimum cycle time (T C) and the minimum precharge time (Tp) have been satisfied.

WRITE CYCLE

A WRITE CYCLE is initiated by Chip Enable

(CE)

going low with Chip Select (CS) High and Output Enable (OE) high. The cycle is complete when data is written into the memory array

(WE =

LOW) or by·~ going high.

Completion of the cycle initiates the automatic precharge cycle.

Data may be written into the memory locations specified by the address by either an EARLY WRITE CYCLE or a LATE WRITE CYCLE. The type of WRITE CYCLE is determined by the relative timing of the high-to-Iow transitions of CE and WE.

In an EARLY WRITE CYCLE, WE and Valid Data In must be true with the specified setup and hold times relative to the high-to-Iow transitions of CEo Upon completion of the WRITE operation, the MK4816 will initiate an automatic precharge cycle in preparation for the next active cycle. The next active cycle may be initiated after the minimum cycle time (T C) and the minimum precharge time (T p) have been satisfied.

In a LATE WRITE CYCLE, the high-to-Iow transition of CE will latch the Addresses and CS internally; however,

WE

may be delayed as much as 5~s to allow for more flexible system timing requirements. Valid Data In must be true with the specified setup and hold times relative to the high-to-Iow transition of

"WE.

In this case, the LATE WRITE CYCLE is initiated by the high-to-Iow transition of

WE.

Upon completion of the WRITE Operation (or upon ~ going high, should~ not make a transition) precharge will be initiated. The next active cycle may be initiated after the minimum cycle time (T

cl

and the minimum precharge time (Tp) have been satisfied.

REFRESH CYCLE

The MK4816 can perform several types of REFRESH cycles, depending upon system requirements and/or user preference. As in other dynamic RAMs any active cycle performs refresh. Independent of the type REFRESH cycle selected, 128· refresh cycles must executed during each 2msec refresh interval. The u may specify the Refresh Address, or the Address generated by the internal Refresh Counter be used.

EXTERNAL REFRESH ADDRESS (RFSH :2: VIH) This refresh mode is identical to the refresh mode of the MK4116. The Row address specified by Ao-A6 defines the memory locations to be refreshed. A READ CYCLE or WRITE CYCLE at each of the 128 unique ROW addresses specified by Ao-A6 must be executed during each 2msec refresh interval. These REFRESH CYCLES may be either distributed or burst mode.

VII-7

INTERNAL REFRESH ADDRESS (RFSH

=

PULSED LOW)

System refresh logic may be simplified or eliminated by utilizing the internal refresh control logic of the MK4816. This REFRESH CYCLE is initiated by an active low pulse applied to the Refresh pin (RFSH). The RFSH pulse may occur one cycle time (tc min) after CE initiates the cycle, or during Standby. In most microprocessor system!?, it may be conveniently generated with each Instruction Fetch Cycle. (The MK3880 provides a RFSH output signal that connects directly to the RFSH input of the MK4816. Thus, the RAM appears totally static to the system.)

If the RFSH pulse occurs during standby, the RFSH CYCLE will be initiated immediately.

During the internally controlled REFRESH cycle, the Refresh Address specified by the internal Refresh Counter will be multiplexed onto the ROW address, the

REFRESH CYCLE will be executed, and the internal Refresh Counter will be incremented. Upon completion of the REFRESH CYCLE, the MK4816 will initiate an automatic precharge cycle in preparation for the next active cycle. Another active cycle may begin after the minimum cycle time (tC) if RFSH is generated during standby. These REFRESH cycles may be either distributed or burst mode.

POWER DOWN AUTO REFRESH (RFSH

:s;

VIL) For either power down (battery back-up) operation or microprocessor single-step operation, it is convenient to utilize the AUTO REFRESH mode ofthe MK4816. The AUTO REFRESH mode is initiated by maintaining RFSH in the low state. If RFSH remains low longer than 20IlS, the MK4816 will automatically initiate a single Internal Refresh Address REFRESH CYCLE approximately every 151ls until the AUTO REFRESH mode is terminated by RFSH going high. During the AUTO REFRESH mode, all inputs except RFSH are inhibited. .

VII-8

1980 MEMORY DATA BOOK

MILITARY IHI-REL

Sections VIII and IX

MILITARY IHI-RELlABILlTY PRODUCTS Table of Contents

Introduction ...•... VIII-1 Applications Guide •... VIII-3 Screening and Lot Conformance Comparison ...•...•... VIII-5 Military (MKB) Products Guide ...•... VIII-7 Commercial Hi-Reliability (MKM) Products Guide ... , ... VIII-9 MKM Screening Chart ...•... VIII-11 Chip Carrier Packaging ...•... VIII-13 MKB Quality Specification ...•... VIII-15 MIL-M38510 Sampling Plan ... VIII-25 MILITARY IHI-REL DATA SHEETS

MKB36000(P I J)-80/83/84 MKB2716(T I J)-87/88/90 MKB4027(J)-83/84 MKB4116(P I J)-82/83/84

MKB4116(E/F)-83/84 MKB41 04(P I J/E)-84/85 MKB4118(P I J)-82/83

65,536 x 1-Bit ... IX-1 2048 x 8-Bit ...•...•... IX-5 4096 x 1-Bit ...•...••... IX-9 16,384 x 1-Bit ...•... IX-13 4096 x 1-Bit ... : ... IX-17 1024x8-Bit ... IX-21

I

Military and High Reliability Products

Dans le document Memory 1980 (Page 173-180)