Up to 30 peripheral devices may be attached to a channel.
Each of these devices has a unique, 6-bit unit address by which it is selected for an input/output operation. To se-lect the peripheral device, the program loads the proper unit address into the 6-bit unit address register (UAR) in the chan-nel buffer. This address selects both the device and, if appropriate, the function to be performed. When any non-zero unit address is placed in the UAR, the peripheral unit been connected, the channel must have information pertain-ing to the location in memory of the data to be transmitted disconnects from the peripheral device and becomes inactive.
The starting memory destination (or source address) for the word assembly register (WAR) and the single-character reg-ister (SCR). The WAR is a 24-bit buffer that contains the word of data actively being received or transmitted during an input or output operation. During input, 6-bit characters are received into the SCR and assembled one at a time into chan-nel, the channel automatically disconnects from the device and is then "ready" for another operation. The channel
logic is reset, except that the state of the channel error in-dicator is maintained and the last word of the input is still
Communication Channel Description 33
6-Bit+Parity
(12-, 24-Bit Optional)
I
Parity
Error Signal
Error
6-Bit Unit I UAR
Function Address
I
t i
Device Control
SCR Input
~
I I
J- --t
I I
I I
I I
I I
L ...J
Output
~ +
Control Logic
WAR
24-Bit Data
MAR Address
Lines
Request Line
TMCC Control
Unit
Address Data
To Memory via CPU
Figure 6. Typical SDS 940 Time-Multiplexed Communication Channel, Block Diagram in the word assembly register. If the number of characters
in the input record was not a multiple of the number of characters assembled into each computer word, then zeros are automatically forced into the least significant positions of the last word. This last word can then be stored in mem-ory by a CHANNEL W INTO MEMORY (WIM) instruction after the channel has disconnected. If the number of char-acters in the input record was a multiple of the number of characters assembled into each computer word, then the word remaining in the channel buffer is either the last group of characters from the input device, (if they were not previously transferred to memory) or zeros (if the last group of characters had been transferred to memory). In either case, it is safe to issue one such WIM instruction after the channel has disconnected without "hanging up" the com-puter.
During output, words are brought from memory into the WAR and disassembled into the SCR, one 6-bit character at a time. Depending on the characters/word format specified, the 6-bit characters within the word are output as fol-lows:
Format
One character/word Two characters/word
Function
Output one character from bit positions 0 through 5
Output two characters from bit positions 0 through I I
34 Communication Channel Description
Format
Three characters/word Four characters/word
Function
Output three characters from bit positions 0 through 17 Output four characters from bit positions 0 through 23 As required, the characters are transferred into the single-character register and output. After each single-character transfer, the word in the WAR is shifted left 6 bits to be ready for the next transfer. Only those characters needed from each word are used; when required, a new word is brought to the WAR for the next character. For special applications, a time-multiplexed channel may be equipped with a 12- or 24-bit single-character register. The external device having a character size greater than 6 bits specifies to the channel what its size is, 12 or 24 bits. Standard 6-bit devices are unaffected by the installation of a wider SCR.
DIRECT ACCESS CHANNEL REGISTERS
In the direct access channels (E through H) the three other registers of importance are the word assembly register (WAR), the input/output register (lOR), and the data chain register (DCR). The WAR is a 24-bit buffer that contains the infor-mation actively being transmitted to, or received from, the external device. Information is assembled into, or disassem-bled from, the WAR in either character or word format; the
format is programmer-selectable. In word format, a data word of up to 24 bits is received from a peripheral unit, placed directly into the WAR, and then del ivered directly to the lOR. When transmitting in the word format mode, words are delivered directly from the lOR into the WAR and from the WAR to the peripheral unit. When transmitting or receiving words, any size from one bit to 24 bits is accept-able (see Figure 7).
The lOR is a 24-bit buffer between the WAR and memory.
The direct access channel control unit places words into the lOR, awaiting their transfer to WAR to be output. During input, the lOR receives words from the WAR and places them into memory under control of the word count and mem-ory address being used in the transmission.
When operating in the character mode, one to four charac-ters are packed into a word. These will normally be the standard 6-bit input/output character size. Characters of less than 6 bits can be handled in character format as de-fined by a particular installation's need. For character for-mats that use characters of less than 6 bits, the data trans-mission is actually in 6-bit character form with zeros filling out the remainder of the 6 bits. When operating in charac-ter format mode, the number of characcharac-ters to be packed in-to, or unpacked from, each data word can be specified by program control. Under this format, one, two, three, or four characters may be packed into, or unpacked from, all words in a particular data transmission. This is true for all channels.
I
WARCharacter Input
parity~
6-Bit + Parity Check
I
(8-, 12-, 24-BitOptional)
,
r
~Error Signal
I
ErrorI ,
I
Character Output
parity~ ,
6-Bit + Parity Gen.
(8-, 12-, 24-BitOptional) I Up to 30 I/O
I UAR
~9
Devices I
t i I t
Device
Control Logic Control
When receiving 6-bit character data from a peripheral de-vice, the first character ora word is received into bit po-sitions 18 through 23 of the WAR. When the second charac-ter is received, the characcharac-ter in bit positions 18 through 23 is shifted into bit positions 12 through 17 and the incoming character is placed into bit positions 18 through 23. The third incoming character causes the characters in bit posi-tions 12 through 23 to be shifted to bit posiposi-tions 6 through 17 and the incoming character is placed into bit positions 18 through 23. The fourth character causes another 6-bit left shift and then the character is placed in the vacated bit positions 18 through 23. At this point the WAR is completely filled; this information is now copied into the lOR to be placed into the proper memory location. The above proce-dure would be followed when four characters per data word were specified for the data transmission. If three characters per word had been specified, the WAR would contain three 6-bit characters in bit positions 6 through 23 and zeros in bit positions 0 through 5 when the word is del ivered to the lOR. The next incoming character would be accepted as the first of another set of three characters. If two characters per word had been specified, the data word containing two 6-bit characters in bit positions 12 through 23 and zeros in positions 0 through I I would be del ivered to the lOR. If one character per word had been specified, the data word delivered to lOR would contain zeros in bit positions 0 through 17 and one character in positions 18 through 23.
When transmitting data using the character format mode, characters are taken from the most significant end of the
lOR
Data Lines
MAR
I
AddressLines
Request Line
DACC Control
Unit
Address
Data Memory
Modules
Figure 7. Typical SDS 940 Direct-Access Communication Channel, Block Diagram
Communication Channel Description 35
WAR. If one character per word is specified, the 6-bit transmitted. The contents of the WAR are again left-shifted 6 bits and the third character from positions 0 through 5 is transmitted; then, another word is received from the lOR to be processed. If four characters are specified, the above process is extended to one more 6-bit left shift and the final 6 bits of the word are transmitted before the next word is accepted from the lOR.
The data chain register (DCR) is used to control input/out-put operations that involve data chaining (i. e., data trans-fer to/from memory locations in noncontinuous memory blocks). The DCR is a 6-bit register that is loaded with a
l-bit data chain interrupt flag and the 5-bit actual block number of the next memory block associated with the I/O operation. After the DCR has been loaded, the channel control unit monitors the contents of the memory address register (MAR). When the 11 low-order bits of the MAR are all zeros after being incremented, the 5 high-order bits of the MAR are replaced by the contents of the DCR so that the
I/o
operation continues with a new memory block. If the data chain interrupt flag has been set to 1, the channel transmits a signal to the zero-word-count interrupt level associated with the channel at this time; otherwise, the com-puter is not notified when the data chaining occurs (see and an attached peripheraI
device to perform a data transmis-sionoratheroperation in ENERGIZE OUTPUT M (EOM). This instruction operates in four distinct modes: buffer control (mode 0), input/output control (mode 1), internal control (mode 2), and system control (mode 3). In modes 2 and 3, EOM is used in non-communication channel operations such as special systems transmission. The different modes of op-eration are program selectable by the setting of two bits36 Primary Input/Output Instructions
EOM in the buffer control mode (0) operates essentially as a set-up or preparation facility for data transmissions or other peripheral activities using the channel. The channel to be used, the peripheral unit on that channel, the direct peripheral devices to perform nontransmitting opera-tions such as rewind magnetic tape and upspace the printer.
Selection of certain channel operations such as interrupt response and input/output terminal function desired is made with this EOM. It is also used to alert peripheral devices installation and system. Address capabil ity is expanded for special system designations. and performs essentially the same functions and operations as an EOM. The internal control (2) and system control (3) modes are avai lable, as special systems require expanded capabil ities.
Affected: determ ined by address field Timing: