_ Manual Update __ _

_ Manual Update _ _ _

Document Title: TMS380 Adapter Chipset User's Guide

TMS380 Adapter Chipset User's Guide Supplement

Document Number: SPWU001D, SPWU003 Revision: F

This document updates the TMS380 Adapter Chipset User's Guide, Revision 0, document number SPWUOOl 0, dated July 1986, and the TMS380 Adapter Chipset User's Guide Supplement (which includes Revision E), document number SPWU003, dated August 1987.

2-9

2-11

3-8

3-8

3-14

TMS380 Adapter Chipset User's Guide, SPWUOO 1 D

Change or Add

Section 2.4, PC AT Adapter Card Example. The schematic supports standard 6-MHz PC AT buses. For higher-speed buses, when the TMS380 is in 16-bit mode, 8-bit 010 using SBHE and AO should be used. This is to avoid timing problems with lOCH ROY for wait state generation.

Figure 2-5 should be replaced with the new Figure 2-5 on page 12 of this manual update.

Add the following paragraph to the bottom of section 3.4.2.

Also shown in Figure 3-3 is a structure called an abort delimiter. The abort delimiter consists of a Starting Delimiter and Ending Delimiter sequence. The abort delimiter is transmitted by the TMS380 Adapter whenever the Adapter detects a 'false free token' as described in Section 3.10.2.

Add the following to Figure 3-3.

ABORT DELIMITER:

SDEL 1 BYTE

EDEL 1 BYTE

The last paragraph. on this page should be changed to read as follows:

A ring station address assigned by the attached system or contained in the BIA ROM must conform to the format shown in Figure 3-14. Note that bit 0 of byte 0 must be set to zero. Bit 1 of byte 0 may be set to either 0 or 1 when the TMS38021 Protocol Handler is used but must be set to 1 when the TMS38020 Protocol Handler is used.

Violating these conditions causes the Adapter to reject the address assignment with a node address error.

TEXAS •

3-14

o

3-15

3-42

3-47

4-7

4-9

4-10

4-22 4-43

4-68

Figure 3-14 should be replaced with the following figure:

BYTE BYTE BYTE BYTE BYTE BYTE

I+-

1 2 ... 7 ⁰

----.I+-

0 ... ¹

----.I+-

7 0 ... ²

----.I+-

7 0 .. , ³

----.I+-

7 0 ... ⁴

----.I+-

7 0 ... ⁵

^--+I

7

I

NODE ADDRESS

... - - - (PASSED FROM ATTACHED SYSTEM OR CONTAINED IN BIA ROM) ----I~~I

LOCALLY (1) OR UNIVERSALLY (0) ADMINISTERED ADDRESS SPECIFIC ADDRESS

Section 3.5.2, Source Routing, has been updated per recent IEEE 802.5 activity.

Section 7.1.3 of the TMS380 Adapter Chipset User's Guide Supplement should be consulted in lieu of this section. Please reference the IEEE 802.5 source routing proposals for current developments regarding source routing specifications.

Add the following note to the end of Section 3.8.5.2.

Note:

When the TMS38021 Protocol Handler ROM code is used or when the OLC Software is used, the Adapter will execute the Beacon Transmit Autoremoval Test after 16 seconds have passed during beacon if the adapter has not proceeded to Monitor Contention mode during beacon transmit.

Add the following note to the end of Section 3.8.7.2.

Note:

When the TMS38021 Protocol Handler ROM code is used or when the OLC Software is used, the Lobe Media Test MAC frame is 1048 bytes in length, and the frame will be transmitted 511 times for this phase of insertion.

Figure 4-5, sheet 1. The R24 resistor connected to the CHPTST pin (pin J 10) and the TEST pin (pin G8) of the TMS38030 should be removed. These two pins should be left unconnected.

Figure 4-5, sheet 3 of the Adapter Chipset Interconnect Schematic should be replaced with the new sheet 3 on page 13 of this update.

Figure 4-5 sheet 4. The value for capacitor C3 should be changed to 22,000 pF ± 10%, and a Note 4 reference added. The following should be added to the bottom of the page as Note 4:

NOTE 4: For additional noise immunity, the value for C3 has been increased to 22,000 pF. For existing designs, the original 6,800 pF value may be used.

Replace (A 1) and (AO) in Table 4-6 with (A2) and (A 1), respectively.

The second sentence of the top paragraph should be changed to read as follows:

Two address-latch-enable signals, system address latch enable (SALE) and extended address latch enable (SXAL), are provided by the SIF.

Table 4-19. Replace the description for BIT 2, SSB_CLEAR, with the following:

SSB_CLEAR. This interrupt request is used by the system to acknowledge adapter- to-host interrupts and to notify the Adapter that the System Status Block (SSB) is

4-68 4-71

4-77 4-77

4-83

4-87

4-88

4-88

4-89

4-92

Table 4-19. Under the description of BIT 8, remove the last sentence.

Section 4.4.2.3. Replace the third paragraph with the following:

Only the address range

>

0800 through > OFFF can be read through the data registers unless an Adapter Check interrupt occurs, in which case only the address range

>

0000 through > 07FF can be read.

In section 4.4.6.1, remove sub-item b, SSB CLEAR (bit 2), from list item 2.

Replace the last paragraph on this page with the following:

If the SCB_REQUEST bit (bit 4) of the Adapter Interrupt Register is set to one, an SCB_CLEAR interrupt will also be posted when the SCB is available for additional commands. To acknowledge this interrupt, the attached system must set the INTERRUPT .-ADAPTER and SSB_CLEAR bits in the Interrupt Register. In addition, the RESET _SYSTEM_INTERRUPT bit should be set to zero to clear the adapter-to- host hardware reset line. It is recommended that SCB_REQUEST be set coincident with EXECUTE if the SCB_CLEAR interrupt is desired.

Table 4-26. Under the description for BIT 1, the 110 seconds reference should be 10 seconds. The sentence should read:

This can be a result of parity errors in excess of the parity abort threshold set during initialization, bus errors in excess of the bus error abort threshold also set during initialization, or if the Adapter times out (10 seconds) waiting for the completion of DMA bus operation (with or without an error).

Table 4-28. The last two sentences in the description for BYTES 2-7 should be replaced with the following:

When using the TMS38020 Protocol Handler, bits 0,1 must be set to "01". When using the TMS38021 Protocol Handler, bit 0 must be set to zero. Bit 1 can be set to either zero or one.

Table 4-28. Under the description of BYTES 22-23, the fifth sentence should be replaced with the following:

The RAM start address must be on an eight-byte boundary minus two bytes (bits 13 and 14 are "11") and must be less than >8000; otherwise, an expansion RAM OPEN error will result.

Table 4-28. Under the description of BYTES 24-25, add the following sentence:

The value of this field must be even.

Add the following note to the bottom of the page:

Note:

Under heavy ring loading conditions, especially when the heavy traffic is broadcast address frames or frames addressed to the inserting adapter, the OPEN command will fail due to a ring poll failure during the insertion process. This failure will occur due to excessive receive loading on the inserting station. The OPEN command should be attempted again after a short delay. If the problem persists, the source of the receive traffic to the inserting adapter should be identified and stopped or removed from the ring before attempting another OPEN command.

Under Buffer Allocation, add the following paragraph:

To avoid the possibility of transmit congestion, causing transmit operations to suspend, it is highly recommended that a RECEIVE command and corresponding valid receive lists be issued as soon as possible following the OPEN command.

4-92

4-99

4-100

4-109

4-119

A-1

Under Buffer Size, change the second sentence to read as follows:

The default TRANSMIT MAXIMUM COUNT is six, allowing a transmit frame maximum information field size of 592 bytes, which includes a 32-byte frame header.

Table 4-34. Under the description of bit 0, change the last sentence to read:

The COMMAND COMPLETE and FRAME COMPLETE bits are not set at the same time.

After the seventh paragraph add the following:

When the last list in a chain contains an odd FORWARD POINTER, the adapter performs the following operations in order:

1. Updates the CST A T field of the last start of frame list.

2. Posts the FRAME COMPLETE status if requested.

3. Rereads the FORWARD POINTER field of the list containing the odd FORWARD POINTER.

4. If FORWARD POINTER is still odd, the adapter posts a COMMAND COMPLETE status.

Because the adapter rereads the FORWARD POINTER after posting the FRAME COMPLETE status, the host software should not modify the FORWARD POINTER of the last list unless it is to add another transmit list to the chain. Therefore, this list containing the odd FORWARD POINTER should not be considered "free" until one of the following occurs:

• IS. COMMAND COMPLETE status is received for this list, or

• Any transmit status (i.e., FRAME COMPLETE, COMMAND COMPLETE, or LIST ERROR) occurs specifying a list further down the chain.

Section 4.4.7.5, CLOSE Command. The following sentence should be added to the first paragraph in this section:

After issuing the CLOSE command, the Adapter should be reinitialized before re-issuing the OPEN command.

Table 4-44. The value for capacitor C3 should be changed to 22,000 pF ± 10%.

See Note 4 added to Figure 4-5 on page 2 of this update.

Add feature bullet as follows:

• Cost-Effective 48-Pin Plastic Dual-ln-Iine Package

A-11 Under the table titled "recommended operating conditions", the reference to TESTO-TEST2 in the specifications for VIH and VIL should be removed. The TESTO-TEST2 pins now have the same VIH and VIL characteristics as all other inputs.

A-14 Add a Note 9A reference to specification for td29. Add the following note to the bottom of this page.

NOTE 9A. When the TMS38010 maintains bus mastership through the next bus cycle, the LRIW signal does not change state for 55 nanoseconds following LBCLK1 low.

A-20 The figure under "interrupt timing" should be replaced with the following new diagram:

LBCLK1 \

/ \o.sv _, r

^{0.45 4V}

^v

/

^4V

LBCLK2

,{o.sv ^{\ ,}

_I ^{I 0.45 V}

LlRQO-LlRQ2, LNMI

~

:

VALID (NOTE 15)

: ~

^2.4V

0.45 V

,

I I

,

_I

I I

,

_I

--,

_{t--tsu2 --t t--th5}

A-20 Note 15 on this page should be replaced with the following:

A-42

NOTE 15. Inputs LlRQO-LlRQ2 should not change state except during the window when LBCLK1 and LBCLK2 are both low. To meet this requirement, a latch, clocked by the falling edge of LBCLK 1, should be added between the LlRQOUTO-LlRQOUT2 outputs of the TMS38030 and the LlRQO-LlRQ2 inputs of the TMS3801 O. Parameter th5 is to be met at the next falling edge of LBCLK 1 following the rising edge of LBCLK2 in which tsu2 was met.

Add a Note 7 A reference to specification for td29. Add the following note to the bottom of the page.

NOTE 7 A. When the TMS38020 maintains bus mastership through the next bus cycle, the LR/W signal does not change state for 55 nanoseconds following LBCLK1 low.

A-53

NC 18 NC 19 NC 20 NC 21 SRS1 22 SRS2 23 VDD 24 SADL7 25 SADL6 26 SADL5 27 SADL4 28 SADL3 29 SADL2 30 SADL1 31 SADLO 32 SPL 33 VSS1 34 SPH 35 SADH7 36 SADH6 37 SADH5 38 SADH4 39 SADH3 SADH2 SADH1 SADHO vSS10 VDD CHPTST NC NC NC VBB(LF)

Replace the seventh feature bullet with the following:

• 132-Pin Plastic Quad Flat Pack or 100-Pin Ceramic Pin Grid Array Package Add the following pinout drawing:

' < t ( , ) N . - N . - O a > O O I ' C O L ! l ' < t ( , ) N . - O a > o o I ' ( Y ' ) ( Y ' ) ( , ) N N N N N N N N N N . - . - . - 0 ' - ' - ' - ' - ' - ' - ' - ' - ' - ' - ' - ' - ' - ' - ' - ' -

VBB(LF) NC NC NC 112 VSS11 111 SBRLS 110 NC 109 VDD 108 LAD15 107 LAD14 106 LAD13 105 LAD12 104 LAD11 103 LAD10 102 LAD9 101 LAD8 100 LPL

99 VSS5 98 LPH 97 LAD7 96 LAD6 95 LAD5 94 LAD4 93 LAD3 92 LAD2 91 LAD1 90 LADO 89 VDD 88 LBGRS 87 NC 86 NC 85 NC 84 NC

Special Note: The user PC board design should include a connection from the VBB pin (67) to one of the VBB(LF) pins (17, 50, 83, 116). This connection should be as short as possible.

The VBB(LF) pins should be unconnected.

A-54 Add a dagger after "pin descriptions" and the following note at the bottom of the page:

tPin numbers refer to the GB package only.

A-65

A-67

A-68

A-74

A-77

A-101

A-105

A-108

A-109

A-110

A-111 A-112

A-114

A-114

A-114

Add a Note 3A reference to the VIL specification in the row labeled, "All other inputs".

Add the following note to the bottom of the page:

NOTE 3A. SRESET is a hysteresis input and should be driven below 0.6 V during assertion to guarantee recognition.

ICC supply current (VCC

=

5.5 V, T A

=

OOC) should be changed from 240 mA max to 260 mA max.

Add a Note 6A reference to specification for td29. Add the following note to the bottom of the page.

NOTE 6A. When the TMS38030 maintains bus mastership through the next bus cycle, the LR/W signal does not change state for 55 nanoseconds following LBCLK1 low.

Add the following sentence to Note 10:

The timing presented above is in reference to externally requested interrupts (those presented on LlRQINO-LlRQIN2) only.

TMS38030-6 has been replaced by the TMS38030-8. Under the section titled "timing requirements over recommended supply voltage range and operating free-air temperature range", remove all references to the TMS38030-6.

Table 1. The value for capacitor C3 should be changed to 22,000 pF ± 10%. See Note 4 added to Figure 4-5 on page 9 in this update.

Under the section titled "energy detect", all references to C3

=

6800 pF should be changed to C3

=

22,000 pF.

Under the section titled "TTL input", remove the reference to FILTER under IIH, IlL, and II.

Under the section titled "transmitter", a note should be added to the "Output current, off" specifications as follows:

Output not under test is loaded with 75 Q to VCC.

Under the section titled "phantom driver", the test conditions under the IOH specification should be changed such that NSRT = VIH, and the parameter IOL should be removed in its entirety.

Figure 5. The 240 Q resistor should be changed to a 330 Q resistor.

Under the section titled "energy detect", the test conditions under parameter VHYS should be changed to VHYS = VIH - VIL.

Note 19 should be replaced with the following:

Peak-to-peak voltage swing between EQUALA and EQUALB. RCVINA and RCVINB are unconnected.

Note 20 should be replaced with the following:

Peak-to-peak voltage swing between DROUT A and DROUTB. A differential between RCVINA and RCVINB is held to assure that noise on the receiver signal does not affect wrap mode.

Figure 8. The value 240 Q assigned to the resistor should be changed to 330 Q.

A-117 Figure 15 should be replaced with the following:

DRVR (4 MHz OS C)

DCLKIN ----, ... _ _

--'J-

^{+ 1.5 V}

L __ --'J-

^{+ 1.5 V}

(8 MHz OSC)

I _ . _

I I

2V 0.8 V

2V 0.8 V tpHL

--t

I-- tpLH

--t

I--

-l

^{I 2.8 V}

t+

^{I.SV F S V}

RCVR

' - - - ' 0.5 V

FIGURE 15. PROPAGATION DELAYS FROM DCLKIN TO RCVR WITH INTERNAL WRAP MODE A-118 Figure 16 should be replaced with the following:

RCVINA (4 MHz OSC)

DCLKIN

(8 MHz OSC)

l f+

^1.5V

'---'I

---4f

^{+ I.S V}

I I

2V 0.8 V 2V 0.8 V I I

RCVR/DRVR I ^2V

(NOTE 23) _ _ _ _ _ ... ' _ _ ....

0.8 V

DROUTB

DROUTA

I I

i t 2 - - - 1

1

1

^50%

I t---t1 - - I - - - -_ _ _ I

i

^{I ... 1 ..} - - - t 3 - -.... ^50%"1

~

--t. ^VCC "" VCC - 2.25V I

50% I

\50%

,- t4

-r

^l "" VCC

' - -_ _ _ _ _ _ _ _ ---J "" VCC - 2.25 V

Note 23: For this test the RCVR output is tied directly to the DRVR input to test the asymmetry of the transmitter in a repeater configuration.

tA t1 + t2

- - -

2

tB t3 + t4

- - -

2

FIGURE 16. SKEW AND ASYMMETRY FROM DCLKIN TO DROUTA AND DROUTB

A-118

8-2

8-4

8-8

8-8

Figure 17 should be replaced with the following:

RCVINA 2V (4 MHz OSCI

0.8 V DCLKIN

l

t + 1.5 V t + 1.5 V 2V (8 MHz OSCI

0.8 V

I I

tPHL--I I-- tpLH---t I--

I I _{2.8 V}

RCVR ! + 1 . 5 V +

1.5V~

0.5 V

FIGURE 17. PROPAGATION DELA VS FROM DCLKIN TO RCVR

Under the Duplicate Address Test frame entry, include the following reference under column 2:

FC

=

>01

Under the Report New Monitor, Report SUA Change, and Report Ring Poll Failure frame entries, include the following under column 2:

FC

=

>01 for TMS38020 ROM code only. Otherwise FC = >00.

The paragraph under Section 8.2.1 should be replaced with the following:

The burned-in address must conform to that shown in the figure below. Note that bit 0 must be set to zero. If the TMS38020 Protocol Handler is used, bit 1 must also be set to zero.

Replace Figure 8-1 with the following:

BYTE BYTE BYTE BYTE BYTE BYTE

I

^{~ o 12 ... 7 0 ~I~ 0 ... 1 ~I~ 7 0 ... 2 ~I~ 7 0 ... 3 ~I~ 7 0 ... 4 ~I~ 7 0 ... 5 ~ 7}

^I

NODE ADDRESS

.... - - - (PASSED FROM ATTACHED SYSTEM OR CONTAINED IN BIA ROM) ---~.~I

LOCALLY (1) OR UNIVERSALLY (0) ADMINISTERED ADDRESS SPECIFIC ADDRESS

FIGURE B-1. BURNED-IN ADDRESS FORMAT

8-19

8-19

27,56 (1.085) 27,31 (1.075)

Section 8.3.3.4. The bottom portion of the 1 OO-pin G8 pin-grid array draw'ing should be labeled "TOP VIEW".

Add the following mechanical drawings:

8.3.3.5 132-Pin Plastic Quad Flat Package (PQ Suffix)

0,635 (0.025) NOM

24,21 (0.953) 24,05 (0.947) 27,56 (1.085)

~--- ---~

27,31 (1.075)

24,21 (0.953) 24,05 (0.947)

0,254 (0.010) NOM

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

8.3.3.6 48-Pin Dual-In-line Plastic Package (N suffix)

r ; : : - - 6 2 , 2 (2.45) M A X - - - ,

I~·~- ---=

^.---.

^I

cr. r

15,49 10.610!,

cr.

I ,

14.99 10.590),

I IND~X~ P

t

^{1 0 ; '} t::::r:=r==L-..A

======;::::;::I~

I--

^90°

8 ---....

PIN SPACING IS 2,54 (0.100) T.P.

(See Note A)

NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

5015 Bl Al 10

~

5014 B2 A2

5013 B3 A3 .'\

5012 B4 A4

~

:\

5011 B5 A5

5010 B6 A6

~

S09 B7 A7

S08 B8 A8

OE _O-'-R_

"

PC-AT SDBEN

10 ..L. ^{+5 V} +5 V +5 V

CHANNEl 19 SOOIR

OE OIR 10 k!l 150 kll 150 kll

S07 Bl Al <----

~

S06 B2 A2 r - - -

~-

505 B3 ^It) A3 -

-::;:--'

S04 B4 ~ A4

~

S03 B5 ~ A5

t:\

'~'~i~lili

^...J

S02 B6 <! A6 Il.

SOl B7 A7

:\

^'"

SOO 11

B8 A8

"

( ^{SOBEN SOOIR}

LA23 10 10 5AOLO

LA22 20 20 SAOLl

LA21 30

'" ^{30 SAOL2}

LA20 40 .... 40

~

^SAOL3

LA19 50 '" _~ ^{50 SAOL4}

LA18 60 <! 60 SAOL5

LA17 70 10 SAOL6

LA16 80 80 SAOL7

OE C

1 1 ... SXAL ~~ SXAL

1 [1~ SOWN ^SOWN

lG 2G

TMS38030

MEMR lYl

~

^{lAl SR5 Gl SRO}

MEMW lY2 lA2 H

SWR

lOR 2Al <! 2Yl

t=J

^SWR

lOW

...

^{2A2 2Y2 SBHE Kl}

SHBE lY3 lA3 SBFiE

L 2A3 2Y3 L.J

SA15 10 10 H7

SAOHO

5A14 20 20 K

SAOHl

SA13 30

'" ^{30 SAOH2}

SA12 40 .... 40

~

^SAOH3

SAll 50 '" ⁵⁰ SAOH4

'"

SA10 60 ;;. ^{60 SAOH5}

SA9 70 70 SAOH6

SA8 80 80 SAOH7

OE C

SOWN ~

1 ^.J\AA_ ·5 V

03

1 11 SALE

""'" B2 SALE

SBRLS <!

il-

2 OE C

l ( J ,! CK

RCO~

O .... N:sa:OO >-~

SA7 10 10 ~ ^LOAO "''''",u~a:...JI'''iw

SA6 20 20 ; - - -

Q ^ENT a:a:a:al_::I:J:ua::a:

~ ^ENP VJ(,J)tnVJ (/)VHJ)cn CJ)

SA5 30 30 ; - - -

SA4 40 40 rr--

S t8~

~NC ^:r

5A3 50 50 OA

SA2 _~ 60 60 14 '/ OB NC

~gLR

SAl .T 70 70 OC NC

SAO

,II

^{80 80 00 ~NC}

l5ACKX ORQX MASTER IROX IOCHROY IOCS16 CLK

AEN ~

RESET ORV f - - -

~

l5ACKX

~k>o--

~

~~

^{' - -}

~B:=

~~

liiAASTIR_

IROX

=

~SA9 [>o-~

^cs

~B:=

^{10CHROY L - - -}

h

~~

^ALS74

~ ^~

~B:= --

.'[:

^{r - - -}

AEN~ ^{10k!! : CLR o 8 WAITlTCH}

~

^{3.3 kO}

20

u:""

"" ^IOCS16

~

^{+5 V}

11 PRE

CLK

I

^{' - - - SRESE'f}

FIGURE 2-5. TMS380 INTERFACE TO IBM PC AT SYSTEM BUS

tv

PAGE 1

A ._::;:-:-\

1""1 PHCS J1

~ r - - - , PHROM

I 'Iii O~I"O

ti ^{t~ t~}

I E1 ._, E3 I ENABLE ^I ~

•

~

^{I • _}

- • EPROM. •

~--~---~, EROM

A2-A14 HM27CS4G-12

~

^ENABLE

L~ ^__

^{J A2.A,4}

~ AO.A~2-~A~1~4~~A~0~

__________ _

~

^EROM

HM6264P-12

2 A12 U17 11 07 29 A11 1/01 12 06 ' ' - - - _2,1. A10 1/02 13 05

OR HM27C64G-15-NA 135 A2 I 2

A3 23 A12U23 11 07

A4 21 :~~ ~~~

LA015 LA014 LA013 LA012 LA011 LA010 LA09 LADS LAL

LA07

U20 R25

Y1 14 RAM

LEN

LA07 2

BUFENB

1S

74AS245 1S B1 17 B2 16 B3 15

015 014 013 012 011 010 09 OS

07

~

~

~ 03

~ 01

Do

24 A9 1/03 15 04 25 AS 1/04 16 03 A7 3 A7' gl 1/05 17 02 AS 4 A6 x 1/06 1S 01 A9 5 A5 co 1/07 19 DO A10 6 A4 I/OS

A11 7 A3 ...;...---:S_.A2 _ _ _ _ 9.~,A1 10 AO 20 CS1

26 CS2

~II ~ _{+5 V} ^R30

WE~ DE~

A2 2 HM6264P-12 A3 I ~A12U1S

A4 21 A11 1/01 r-1_1 __ ....I....l.!"-,~

A5 24 A10 1/02 12 A6 25 A9 1/03r-1

__ 3 --....I....l.!"-'':

A7 3 AS 1I04r.1 :-::5

,---4-.J,.::.!.:

4 A 7 gl 1/05, r-1_6 __ --l-.l.!"-'-' 5 A6 x 1/06r-1_7 __ ....I...~~

6 A5 co 1I07 .. 1_S __ --'-L~~

7 A4 I/OSr-1-9----+~:!.-

-::---S--' A3

9 A2

-=A-=1-4+--1"':0:..J A 1

20~

26 g~~

WE~ DE~

A5 24 A9 Q2 13 05

A6 25 AS Q3 15 04

A7 3 A7 gl Q4 16 03 AS 4 A6 x Q5 17 02 A9 5 A5 Q) Q6 1S 01

A10 6 A4 Q7 19 DO

A11 7

A 12 S A3 VPP i1-^{+ 5 V}

I A13 9:~ ^NC ~NC(A1)

A14 10 AO PGM ~

~ CE ~R27

m 22 DE +5 V

~I HM27g~4G-12

HM27C64G-15-NA 135

A2 2

A12U24 I'\.:.';';;""+--r=-:--.A 11

- ' - - r - - : -,A 1 0 I"""""'"'--t--T';:-:;-IA9 I,,-,..;.;o...-t--r-~ lAS I""""..:..;....-t--r-~ I A 7 Q)

4 A6 '"

5 A5 _ _ -r-6_ ,A4 co

A3 A12 S A2

A13 9

A14 10

CE DE

Vpp~1 ^+5V

NC 26 NC(A1) PGM 27

R28 +5 V R31

+ 5 V HM6264P-12 HM27g~4G-12

2! A12 U19 H:27C64G-15-NA135

A2

LAOO-LA015.LPH.LPL

U15 B4 14 B5 13 86 12 B7 11

BS ---'2=1"-'A11 1/01 11 12 U25

24 A 1 0 1/02 12 11 QO 11 PL

R33 LPH 'PL 74AS245

---I----...:2::;;5~A9

3 A8 0/04 15 ^{1/03 13 Q1 12} 02 '3 ^PH

B1 1S PH 4 A7 CO 1/05 16 Q3 15

1

82 17 PL 5 A6 '" 1/06 17

~ !

^{A7 CO Q4 16}

a 5 NC 83 16 6 A5

~'/07'8

^{5 A6 • 05 17}

Ull 84 15 7 A4 0/08 19 A5 06 '8

LBCLK1 3

b

^{74ALS74 85 '4 8 A3 6 A4 • OJ'9 NC}

CK 0

6

8 6 " 9

A2

WE 27 A3

CLR 87 ,2 '0 A' DE 22 A2 Vep 26 . , V

BS 11 20 ~ NC 27 NC(A1)

26 CS1 PGM

CS2 R29

+5 V

74ALSOO

00-015.PH.PL 00-015.PH.PL

NOTE 4. For additional noise immunity, the value for C3 has been increased to 22,000 pF. For existing designs, the original 6,800 pF value may be used.

FIGURE 4-5. ADAPTER CHIPSET INTERCONNECT DIAGRAM (3 of 4)

2-9

2-29

2-73

2-84

2-86

2-87 2-87

TMS380 Adapter Chipset User's Guide Supplement

Change or Add

Change the last sentence in the first paragraph to read as follows:

If a link station is in either a Checkpointing or Remote Busy state, then I-frame transmission is temporarily suspended.

The description for BIT 9, LLC_CTR_OVERFLOW, should be changed to read as follows:

When set to one, indicates that one of the adapter's LLC error counters has reached half its maximum value.

The description for OPTIONS and BIT 0 should be changed to read:

(reset) - If this bit is set to one, bytes 0-7 are reset to zero after this command is executed.

Table 2-29. Under the explanation for error code> 28, remove the second line, which reads" An XID frame had too much data".

Under the explanation for error code > 41, remove the sentence which reads "this error code will be returned if an I-frame is issued before the DMA is ready," and place it under the explanation of error code > 27.

After the second paragraph add the following:

When the last list in a chain contains an odd FORWARD POINTER, the adapter performs the following operations in order:

1. Updates the CST A T field of the last start of frame list.

2. Posts the FRAME COMPLETE status if requested.

3. Rereads the FORWARD POINTER field of the list containing the odd FORWARD POINTER.

4. If FORWARD POINTER is still odd, the adapter posts a COMMAND COMPLETE status.

Because the adapter rereads the FORWARD POINTER after posting the FRAME COMPLETE status, the host software should not modify the FORWARD POINTER of the last list unless it is to add another transmit list to the chain. Therefore, this list containing the odd FORWARD POINTER should not be considered "free" until one of the following occurs:

• A COMMAND COMPLETE status is received for this list, or

• Any transmit status (i.e., FRAME COMPLETE, COMMAND COMPLETE, or LIST ERROR) occurs specifying a list further down the chain.

BIT 3. Remove the last sentence in this description.

BIT 4. Replace the description for BIT 4 with the following:

(READY): Bit 4 will be used to indicate when a link station is ready to accept I-frames from the attached system. This bit will be set under either of two conditions. First, when a CONNECT.STATION command completes, the attached system should assume a not ready state, and wait fO,r a READY transmit status interrupt. This interrupt will occur when the link station is ready for I-frame transmission, whether or not a TRANSMIT command has been issued. This interrupt may occur prior to receiving

3-2

4-3

4-4

4-5

Second, after an I-frame has been DMA' ed into the adapter, and a CST AT completion of > FE has been received, the link station is in a not ready state. When this condition clears, a READY transmit interrupt will be issued. If, after a > FE completion has been issued, another I-frame for that link station is passed to the adapter, the adapter will reject the I-frame with the error code> 27, Link not Transmitting I-frames. Processing of the transmit lists will continue, and frames for other link stations will not be affected.

Figure 3-2 should be replaced with the new Figure 3-2 included on page 18 of this update.

The following paragraphs should be added after the last paragraph on this page.

The refresh of this DRAM is accomplished by a CAS-before-RAS refresh cycle whenever the DRAM is not being accessed by any of the chipset bus masters. This occurs during Communications Processor internal processing cycles or whenever addresses below > 1000 are accessed. Additionally, refresh occurs whenever sequential DRAM read or write cycles occur to each of the 256 DRAM row addresses.

This occurs during normal DMA operations by the System Interface or Protocol Handler.

Analysis of the Communications Processor software characteristics and Protocol Handler and System Interface DMA loading characteristics guarantees that DRAM refresh timing is not violated.

Figure 4-4 should be replaced with the new Figure 4-4 included on page 1 9 of this update.

The top portion of Section 4.3 should be replaced in its entirety with the following:

The download of DLC Software is performed by:

1. Placing the adapter into download state.

2. Downloading and executing the Enable Memory (ENM) software.

3. Setting the PHDIS to one.

4. Downloading the DLC Software object code via direct I/O (010) operations.

The special download state of the adapter is entered via the following procedure:

1. Perform a hardware reset (SRESET driven lo'v).

2. Verify normal completion of bring-up diagnosf.lcs (>0040 read in the Interrupt Register).

3. 010 write the data pattern >AA55"from Ic)cation >0800 through >OFFE via the Address Register and Data Register with Autoincrement.

4. Apply a second hardware reset.

5. Write the value > 8000 to the TMSJ8030 Interrupt Register immediately following reset but no later than 1.6 ms following the reset.

Following the write of > 8000 to the Intern;pt Register and a delay of 10 milliseconds, the Interrupt Register should be read. If the Interrupt Register is equal to zero, then the adapter is in the download state. T:,e memory locations from >0800 through

> OFFE should be cleared to zero.

After successfully entering the download state and clearing the RAM, the object file may be loaded into the adapter RAM. Before this procedure is discussed, the following provides a description of the format of the object file in which DLC Software and ENM Software is provided.

4-6

4-6

4-6

5-13

5-15

7-1

7-4

7-14

7-15 7-21

A-3

A-22 A-24

Section 4.3.2. Add the following sentences to the description of the WRITE Command (>E6):

This command takes nine microseconds to execute. No other command should be issued prior to this time.

Section 4.3.2. Add the following sentence to the description of the STEP Command (>FF):

This command takes seven microseconds to execute.

Section 4.3.2. Add the following sentence to the description of the EXECUTE Command (>C5):

This command takes 12 microseconds to get to the first instruction of the target code.

Under Section 5.2.5.1, the reference to the fail code of > 7X should be deleted. The last paragraph should be deleted and replaced with the following:

No failure code is presented with the OMA tests. The source and destination data patterns must be compared to verify good completion of the OMA operation.

Under Section 5.2.6.1, the reference to the fail code of > 7X should be deleted. The last paragraph should be deleted and replaced with the following:

No failure code is presented with the DMA tests. The source and destination data patterns must be compared to verify good completion of the OMA operation.

The Bridge Options Software, referenced throughout Section 7, has been replaced by the OLC Software. All functions contained in the Bridge Options Software are also contained in the OLC Software. For information on the OLC Software refer to Section 2.

Under the description for the Broadcast Bits, the definitions for bit codes "110" and

"111" should be reversed.

The last paragraph on this page should be replaced with the following:

The bridge options are included in the OLC software.

The first paragraph on this page should be deleted in its entirety.

Replace the 41 st equation with the following:

COMB2

=

! (!A12 & A1314 & !GRPDLY & SAVE12 & STAT

# A12 & A1314 & !GRPDLY & !SAVE12 & STAT);

Change the second to the last feature bullet to read:

• 48-Pin, 600-MiI, Plastic or Ceramic Dual-ln-Iine Packaging Change the package description above the pinout to read:

liN OR JD PACKAGE"

The units for ICC supply current should be changed from p.A to rnA.

Add a Note 7 A reference to specification for td29. Add the following note to the bottom of this page.

NOTE 7 A: When the TMS38021 maintains bus mastership through the next bus

A-37 B-3 C-1

D-2

The manual updates listed in the appendix are also included in this update.

Replace Figure B-2 with the new Figure B-2 on page 20 of this update.

Appendix C should be replaced in its entirety by the new download program included on pages 21 through 25 of this update.

Add the following information to Appendix D:

NOTE: For Developers of PC Adapters:

In TI's testing of the LLC software, we have discovered the following hardware dependency in IBM's APPC/PC program and IBM's 3270 Emulation Program.

These software programs read a register at I/O location h' A20' (primary adapter) and/or h' A24' (secondary adapter) to determine the interrupt level that the card is using.

On the IBM card, the interrupt level is encoded in the two least significant bits of this register, as follows:

00 interrupt level 2 01 interrupt level 3 10 interrupt level 6 11 interrupt level 7

This register is described in Section 6 of the IBM Token-Ring PC Adapter Technical Reference. To avoid confusion, though, please note that if a switch is "on," the corresponding bit in the register will be O. If a switch is "off," the bit will be 1.

These two software programs violate the IBM software interface to read these registers on the hardware. If the programs read bad data from the locations (either because there is nothing there, or because what is there is not what is expected), their operation will be unreliable. Designers should consider adding hardware to boards at these locations.

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FIGURE 3-2. EPROM-Based Adapter Bus Schematic