Network Processors

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Network Processors

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The Designer’s Guide to VHDL, Second Edition Peter J. Ashenden

The System Designer’s Guide to VHDL-AMS

Peter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden Modeling Embedded Systems and SoCs

Axel Jantsch

ASIC and FPGA Verification: A Guide to Component Modeling Richard Munden

Multiprocessor Systems-on-Chips

Edited by Ahmed Amine Jerraya and Wayne Wolf Functional Verification

Bruce Wile, John Goss, and Wolfgang Roesner

Customizable and Configurable Embedded Processors Edited by Paolo Ienne and Rainer Leupers

Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures

Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Configured Processors

Steve Leibson

ESL Design and Verification

Grant Martin, Andrew Piziali, and Brian Bailey Aspect-Oriented Programming with e David Robinson

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation Edited by Scott Hauck and André DeHon

System-on-Chip Test Architectures

Edited by Laung-Terng Wang, Charles Stroud, and Nur Touba Verification Techniques for System-Level Design

Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad VHDL-2008: Just the New Stuff

Peter J. Ashenden and Jim Lewis

On-Chip Communication Architectures: System on Chip Interconnect Sudeep Pasricha and Nikil Dutt

Embedded DSP Processor Design: Application Specific Instruction Set Processors Dake Liu

Processor Description Languages: Applications and Methodologies Edited by Prabhat Mishra and Nikil Dutt

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Network Processors

Architecture, Programming, and Implementation

Ran Giladi

Ben-Gurion University of the Negev and EZchip Technologies Ltd.

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Network processors: architecture, programming, and implementation/Ran Giladi.

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1. Network processors. 2. Routing (Computer network management)—Equipment and supplies.

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In memory of my father Benjamin (Sontag) Z”L To my mother Rita (Aaron)

To my beloved wife Kora

To Ornit, Niv, and Itamar, our wonderful children,

and to my dear brother Eival

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CHAPTER 1 Introduction and Motivation

... 1

1.1 Network Processors Ecosystem ... 1

1.2 Communication Systems and Applications ... 2

1.3 Network Elements ... 6

1.4 Network Processors ... 8

1.5 Structure of This Book ... 10

1.6 Summary ... 12

PART 1 Networks CHAPTER 2 Networking Fundamentals

... 15

2.1 Introduction ... 16

2.2 Networks Primer ... 17

2.3 Data Networking Models ... 21

2.4 Basic Network Technologies ... 25

2.5 Telecom Networks ... 26

2.6 Data Networks ... 38

2.7 Summary ... 69

Appendix A ... 70

Appendix B ... 72

CHAPTER 3 Converged Networks

... 77

3.2 From Telecom Networks to Data Networks ... 78

3.3 From Datacom to Telecom ... 87

3.4 Summary ... 134

Appendix A ... 135

CHAPTER 4 Access and Home Networks

... 149

4.1 Access Networks ... 149

4.2 Home and Building Networks ... 178

4.3 Summary ... 180

PART 2 Processing CHAPTER 5 Packet Processing

... 183

5.1 Introduction and Defi nitions ... 183

5.2 Ingress and Egress ... 186

5.3 Framing ... 188

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5.4 Parsing and Classifi cation ... 195

5.5 Search, Lookup, and Forwarding ... 205

5.6 Modifi cation ... 236

5.7 Compression and Encryption ... 237

5.8 Queueing and Traffi c Management ... 238

5.9 Summary ... 239

CHAPTER 6 Packet Flow Handling

... 241

6.1 Defi nitions ... 242

6.2 Quality of Service ... 243

6.3 Class of Service ... 244

6.4 QoS Mechanisms ... 249

6.5 Summary ... 286

CHAPTER 7 Architecture

... 287

7.2 Background and Defi nitions... 289

7.3 Equipment Design Alternatives: ASICs versus NP ... 308

7.4 Network Processors Basic Architectures... 309

7.5 Instruction Set (Scalability; Processing Speed) ... 314

7.6 NP Components ... 314

7.7 Summary ... 335

CHAPTER 8 Software

... 337

8.2 Conventional Systems ... 342

8.3 Programming Models Classifi cation ... 348

8.4 Parallel Programming ... 349

8.5 Pipelining ... 355

8.6 Network Processor Programming ... 359

8.7 Summary ... 363

Appendix A ... 364

Appendix B ... 371

Appendix C ... 377

CHAPTER 9 NP Peripherals

... 379

9.1 Switch Fabrics ... 379

9.2 CoProcessors ... 403

9.3 Summary ... 407

PART 3 A Network Processor: EZchip CHAPTER 10 EZchip Architecture, Capabilities, and Applications

411

10.1 General description ... 411

10.2 System Architecture ... 413

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10.3 Lookup Structures ... 419

10.4 Counters, Statistics and Rate Control ... 421

10.5 Traffi c Management ... 424

10.6 Stateful Classifi cation ... 425

10.7 Multicast Frames ... 425

10.8 Data Flow ... 426

10.9 Summary ... 438

CHAPTER 11 EZchip Programming

... 439

11.1 Instruction Pipeline ... 440

11.2 Writing NP Microcode ... 443

11.3 Preprocessor Overview ... 447

11.4 Developing and Running NP Applications ... 447

11.5 TOP Common Commands ... 449

11.6 Summary ... 457

Appendix A ... 458

CHAPTER 12 Parsing

... 461

12.1 Internal Engine Diagram ... 461

12.2 TOPparse Registers ... 465

12.3 TOPparse Structures ... 469

12.4 TOPparse Instruction Set ... 469

12.5 Example ... 474

12.6 Summary ... 478

Appendix A ... 479

Appendix B ... 486

Appendix C ... 487

CHAPTER 13 Searching

... 501

13.3 TOPsearch I Structures ... 505

13.4 Interface to TOPparse (Input to TOPsearch) ... 506

13.5 Interface to TOPresolve (Output of TOPsearch) ... 509

13.6 Hash Table Learning ... 511

13.7 Example ... 513

13.8 Summary ... 516

CHAPTER 14 Resolving

... 517

14.2 TOPresolve Registers ... 521

14.3 TOPresolve Structures ... 526

14.4 TOPresolve Instruction Set ... 527

14.5 Example ... 531 Contents ix

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14.6 Summary ... 536

Appendix A ... 537

Appendix B ... 544

Appendix C ... 546

CHAPTER 15 Modifying

... 561

15.1 Introduction ... 561

15.3 TOPmodify Registers ... 566

15.4 TOPmodify Structures ... 570

15.5 TOPmodify Instruction Set ... 571

15.6 Example ... 574

15.7 Summary ... 583

Appendix A ... 584

Appendix B ... 591

Appendix C ... 592

CHAPTER 16 Running the Virtual Local Area Network Example

... 603

16.1 Installation ... 603

16.2 Getting Started ... 604

16.3 Microcode Development Workfl ow ... 607

16.4 Summary ... 615

CHAPTER 17 Writing Your First High-Speed Network Application

... 617

17.2 Data Flow and TOP Microcode ... 618

17.3 Data Structures ... 648

17.4 Summary ... 654

List of Acronyms

655

References

673

Index

695

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Preface

Network Processor Units (NPUs) are designed for use in high-speed, complex, and fl exible networking applications, and they have very unique architectures and software models. The fi rst generation of NPUs appeared in about 2000, followed by a second generation of specialized NPUs for various segments of networking applications, usually equipped with the traffi c managers required by contemporary networks. NPUs can be compared to Digital Signal Processors (DPSs) that are targeted for high-speed, complex, and fl exible signal processing, or to Graphical Processing Units (GPUs) that are required in demanding video processing.

Using NPUs is not trivial, and professional engineers have to learn how to use and program these processors. System architects and system engineers must be aware of the capabilities and advantages that NPUs can provide them in designing network devices. Since data communications and telecommunications industries are bound to use these devices, I found it necessary to include a basic course on NPUs in my department of Communication Systems Engineering at Ben-Gurion Univer- sity. I have been teaching the subject of NPUs since 2003, and during this period an increasing number of similar courses have been given by other electrical engineering, computer science, and communication systems engineering departments worldwide. In addition, many of my graduate students (now engineers) have called specifi cally to tell me how important this course has been for their professional careers, helping them to use any NPU, or even developing and using a special-purpose ASIC, for networking applications.

After teaching this subject for several years, I was asked to write a comprehensive book to cover all aspects of NPUs, from network technologies, computer architecture, and software, to specifi c network processing functions and traffi c engineering.

Taking advantage of my long association with EZchip, one of the leading NPU vendors, what I wrote emphasizes what practitioners require while studying NPUs for their projects. The result is this book, which took me almost two years to complete.

Network Processors: Architecture, Programming, and Implementation is organized in three parts: (1) Networks—from fundamentals, to converged core and metro networks, to access networks; (2) processing—from network processing and algorithms, to network processor architectures and software modeling; and (3) an in—depth example of a network processor (EZchip), including hardware, interfaces, programming and applications.

The book’s target audience is practitioners and students alike. Practitioners include professionals—system architects and system engineers who plan their next-generation equipment and require more in-depth knowledge for choosing and using NPUs; network engineers and programmers who manage projects or write applications for high-speed networking, and need the knowledge and the terminology used in networks, network algorithms and software modeling; and possibly product managers and other professionals who want cutting-edge knowledge in order to design products or to understand them. Research and graduate students,

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or students in the last phase of their undergraduate studies, may need this book for projects, research on high-speed network applications, or simply a deeper understanding of networking; it will prepare them well for their professional careers.

Acknowledgments

While writing, many assisted me in various ways—too many to list here, and I thank them all. However, I must thank fi rst and foremost a dear friend, Eli Fruchter, who I have known for the last 25 years since we started working together as engineers. Eli founded EZchip and has headed the company from the beginning, and he agreed to disclose EZchip’s architecture and have it included in this book.

Amir Eyal, EZchip’s vice president of business development, who knows the NPU market and technology inside out, provided me with his vision and insight into this fi eld. Eyal Choresh, vice president of software at EZchip, whom I also have known for many years, assisted me in explaining the NP architecture’s details, as well as providing other clever ideas on software issues. Alex Tal, EZchip’s fi rst chief tech- nical offi cer, gave me my fi rst insight into how this book should be structured and provided me with his perspectives on the architecture of NPUs. Thanks go to all the EZchip family for various kinds of assistance, including, EZchip’s current CTO Guy Koren, Nimrod Muller, Aweas Rammal, Daureen Green, and Anna Gissin.

Many of my students and colleagues were very helpful in writing and checking software, reviewing and commenting; they include Mark Mirochnik, Dr. Nathalie Yarkoni, Dr. Iztik Kitroser, Micahel Borokhovich, Kfi r Damari, Arthur Ilgiaev, Dr.

Chen Avin, Dr. Zvi Lotker, Prof. Michael Segal, and Dr. Nissan Lev-Tov.

Among the many friends and colleagues who pushed and supported me during the long period of writing, I must thank Prof. Gad Rabinowitch, Prof. Gabi Ben-Dor, Shai Saul, Beni Hanigal, Prof. Yair Liel, and Moshe Leshem.

Special thanks go to Dr. Tresa Grauer who worked with me on editing everything I wrote, watching me to make sure that everything I wrote was clear, who made me rewrite and reedit until she was satisfi ed. Her devoted efforts have been remarkable. I am grateful to Chuck Glaser, Greg Chalson, Marilyn Rash, and the edi- torial and production staff at Morgan Kaufmann and Elsevier for their wonderful work, patience, encouragement, and professionalism.

I want to take the opportunity to thank my parents who form the basis of everything I’ve got, each of them in a special way—the endless support and warmth of my mother and the drive for knowledge and accomplishments from my father.

I owe them the many things I have achieved, this book included. I regret that my father’s wish to see it completed was unfulfi lled.

Last, but not least: Kora, my wife and lifetime friend, and our three children, Ornit, Niv, and Itamar. All were so tolerant of me and my absence while working on this book (and on other projects, in their turn). They assisted with drawings, and Itamar even arranged all the acronyms. Their support and love allowed me to devote time to read many hundreds of papers, learning and thinking, designing, and writing this book.

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CHAPTER

1

Network processors (NPs) are chips—programmable devices that can process network packets (up to hundreds of millions of them per second), at wire-speeds of multi-Gbps. Their ability to perform complex and fl exible processing on each packet, as well as the fact that they can be programmed and reprogrammed as required, make them a perfect and easy solution for network systems vendors developing packet processing equipment.

Network processors are about a decade old now and they have become a fundamental and critical component in many high-end network systems and demanding network processing environments.

This chapter introduces this relatively new processing paradigm, and provide a high-level perspective of what NPs are, where to use them and why, and conclude with a brief description of the contents of the rest of the book.

1.1 NETWORK PROCESSORS ECOSYSTEM

Telecommunications and data networks have become essential to everything that we do, to our well-being and to all of our requirements. The prevalence of Internet technology, cable TV (CATV), satellite broadcasting, as well as fi xed and cellular mobile telephony, tie many and expanding services to a very large population that is growing exponentially. The increasing speed of the communication links has triggered a wide range of high-speed networks, followed by an increasingly broad spectrum of services and applications.

We are witnessing this dramatic growth in communication networks and services; just think of the changes that networks and services have undergone in the past 10 years in the areas of mobile, video, Internet, information availability, TV, automation, multimedia, entertainment, online services, shopping, and multiplayer games. You can safely assume that an equivalent jump in technology and services will happen again in the next 5 years or so.

Introduction and Motivation

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Networks and infrastructures have enabled it all. Most houses, vehicles, pieces of equipment, and people, maintain a communication link to the “network,” a giant octopus with zillions of arms. And the oxygen that runs in its veins, pipes, and trunks are packets and cells; zillions of zillions of them are fl ying around us and surrounding us at every moment. These packet fl ows undergo various treatments, processing, and forwarding, in many kinds of network devices. These network devices are systems by themselves, and they keep the octopus, or the “network,” alive. Such network systems include switches, adapters, routers, fi rewalls, and so on.

Network systems, therefore, face an ever-increasing magnitude of packets they have to handle, while at the same time, the processing of these packets becomes more and more complex. This creates a gigantic performance problem. In order to cope with it, vendors have replaced the traditional general purpose Central Processing Unit (CPU) in the network systems with Application Specifi c Integrated Circuits (ASICs), which are hardwired processing devices. However, as vendors also face rapid changes in technology, dynamic customer requirements, and a pres- sure for time-to-market, short developing cycles and lots of revisions have become necessary. All of this has required an innovative approach toward network systems architecture and components.

This is the foundation on which NPs fl ourish. NPs enjoy the advantages of two worlds—they have the performance capabilities of an ASIC, and the fast, fl exible, and easy programmability of a general-purpose CPU. NPs constitute the only option for network systems developers to implement dynamic standardized protocols in performance-demanding environments.

1.2 COMMUNICATION SYSTEMS AND APPLICATIONS

Communication systems are composed of networks and network devices (which are sometimes referred to as network elements, or network systems, as we called them above, since they are computerized, special purpose systems that include both software and hardware).

Communication networks can be separated into three main categories: the core, the aggregation (or metro), and the access networks. Each of these network categories are characterized by different requirements, technologies, and equipments.

In addition, there are traditionally two communication systems we use: telecommunications (telecom) and data communications (datacom). The more established and older network, the telecommunication network, is based on “circuits,” or channels of continuous bit streams, which grew out of its original application to telephony services. The more recent networks, the data communications networks, were initially based on packets of data to carry information among computers. This resulted in two paradigms of network technologies—circuit switching and packet switching.

The main technology in telecommunication systems is the Synchronized Opti- cal Networks/Synchronous Digital Hierarchy, which is used in both the core and

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the aggregation networks. Radio Access Networks through which most mobile telephony is conducted, as well as the wireline telephony access networks, are usually attached to these networks, using their own technologies. CATV is a parallel network that is traditionally used for TV services.

The main technologies in the datacom systems are the Ethernet and the Internet Protocol (IP). For the last two decades, converged telecom–datacom networks have been subject to vast research, industry implementation trials, and services.

This convergence happens in the technology plane as well as in services: recent Telecom networks’ cores are implemented using datacom technologies (such as Ethernet, Multiprotocol Label Switching [MPLS] and IP). Recent trends in converged services, starting with “triple-play” service (or “quadruple-play” for Inter- net, TV, telephony, and data-oriented services) to Voice over Internet Protocol telephone services and TV over IP, are just a few examples of the transition to a unifi ed, converged network.

The result is that packet networks have become the prevalent technology for communication systems. Network systems are making the transition from circuit- switched based technologies (multiplexers, cross connects, branch exchanges, etc.) to packet-switched based technologies (such as bridges and routers).

Services are also developing in scale and complexity; from plain telephony, TV, and Internet surfi ng and e-mails, we are now facing High Defi nition TV, new generations of web and web services, digital libraries, and information availability, gaming, and mobile 3G and 4G services that include information, multimedia, video, and TV, and many other demanding applications. Other adjunct services, such as security, provisioning, reliability, and accounting must be supported by network systems, which may impose additional signifi cant load on them.

As networks become the infrastructure for information, interactive data, real-time data, huge multimedia content transport, and many other services described previously, the technology of networks must cope with various requirements, but primarily that of speed. High-speed networking refers to two aspects of speed: the links’ transmission rates—from multi Mbps (10⁶ bits per second) to multi Gbps (10⁹ bits per second)—and the complexity and speed of the required processing due to the number of networks, addresses, services, traffi c fl ows, and so on.

If we examine the speed of network links over the years, we fi nd a similar but higher growth pattern than that of processing capabilities. In computing, this exponential growth is modeled as doubling roughly twice every 2 years (after Moore’s law);¹ however, in the last decade this growth rate has shrunk, and is roughly at 41% annually (with clock speedups increasing only 29% annually).

[116] If we look, for example, at Ethernet bandwidths, we fi nd a ⫻10⁴ speedup in 27 years (from 10 Mbps approved in 1983 to 100 Gbps expected to be approved

1Moore’s law is an interpretation of the 1965 statement of Gordon Moore of Fairchild, who was a founder of Intel. The law refers to the doubling of the number of transistors on a chip, or the chip performance, every 18 to 24 months.

1.2 Communication Systems and Applications 3

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100000

Expected 100 GbE 10 GbE

1 GbE

100 Mbps

10 Mbps Ethernet

1983 1988 1993 1999 2004 2010

10000

1000

100

10

1

2015 FIGURE 1.1

Ethernet-approved interface speeds

in 2010, as shown in Figure 1.1), which is doubling the bandwidth every 24 months. However, if we examine the increase from 100 Mbps (approved in 1995) to 100 Gbps (⫻10³), it is doubling the bandwidth every 18 months. This pattern of growth is similar to that of telecom links (Optical Carrier—availability during these years).

Ethernet bandwidth growth is in-line with Moore’s law, although a bit faster.

Add to that the increase in network utilization and the increased number of networks, which are doubling roughly every four years, as the number of BGP² entries indicate, depicted³ in Figure 1.2; and we have aggregated traffi c that is doubling approximately once a year [85].

This traffi c increase is twice as fast as Moore’s law, or twice as fast as computing processing is capable of meeting, including network systems (such as routers) that are based on the same computing paradigm. The many different applications used on the Internet, with varying demands that are changing constantly, add another dimension of diffi culty for network systems. Figure 1.3 shows a snapshot demonstrating traffi c growth and application mix in a major Asian-Pacifi c ISP⁴ from July 1, 2007, to April 1, 2008.

2Border Gateway Protocol (BGP) routers possess entries that indicate the number of IP networks.

3The number of active BGP entries are from http://bgp.potaroo.net/as2.0/bgp-active.txt.

4The data are sampled on the fi rst of every month, at 07:00 hours.

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FIGURE 1.2

Number of IP networks known to BGP routers 250

Number of IPv4 networks (in 000) 200

150

‘000 Active BGP Entries (IPv4)

100

50

0

06/88 12/90 05/93 11/95 05/98 11/00 05/03 11/05 05/08

FIGURE 1.3

Application mix in internet (Courtesy of Allot Communications.)

Aug 2007 0

100 200 300 400

Total Bandwidth (Mbps)

500

Protocol Bit Torrent eDonkey FTP HTTP P2P Applications SMTP

Streaming Applications YouTube

600 700 800 900

Sep 2007 Oct 2007 Nov 2007 Dec 2007 Jan 2008 Feb 2008 Mar 2008 P2P Applications

HTTP

Bit Torrent

1.2 Communication Systems and Applications 5

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The shift to packet-oriented networks, together with the exponential growth of demanding services, traffi c, and number of networks has thus become a great challenge to network systems. This challenge is enormously complicated, due to the need to forward packets among huge numbers of networks at extremely high speeds, as well as to establish and maintain tunnels, sessions, and fl ows, while keep- ing the required Class of Service.

Network processors must play a signifi cant role in inputting packets and outputting processed, classifi ed, prioritized, and forwarded packets, in high- speed networks, for various requirements and with high complexity. The shift to new network processing paradigms is a must, and NPs are the vehicles for doing it.

1.3 NETWORK ELEMENTS

Network elements (also called network systems, network equipment, or network devices) are nodes in the networks that enable the network to function. These nodes are complex computerized systems that contain both software and hardware (sometimes also operating systems), and are special purpose systems that are used for networking and, more specifi cally, for networking functions such as switching, routing, multiplexers, cross-connects, fi rewalls, or load balancers [380].

Network elements are usually architected in two separated planes [255, 435]:

the control plane and the data forwarding plane. The control plane is responsible for signaling as well as other control and management protocol processing and implementation. The data forwarding plane forwards the traffi c based on decisions that the control plane makes, according to information the control plane collects. The control plane can use some routing or management protocol, according to which it decides on the best forwarding tables, or on the active interfaces, and it can manipulate these tables or interfaces in the data forwarding plane so that the “right” actions will take place. For example, in IP network elements, the control plane may execute routing protocols like RIP, OSPF, and BGP, or control and signaling protocols such as RSVP or LDP. (All these abbreviations indicating various protocols are covered in Part 1 of the book, which describes networks.) The data forwarding in these IP network systems may execute packet processing, address searches, address prefi x matching for forwarding, classifying, traffi c shaping, and metering, network address translation, and so on.

A typical system can be either a “pizza box” (Figure 1.4) or a multicard chassis (see Figure 1.5). A “pizza box” contains a single board, on which all processing, data forwarding, and control are executed. In a multicard chassis, there are separate cards for each function; some execute data forwarding (and are usually referred to as line-cards), while others may execute control and management functions.

Additional cards may be used for switching data between all cards, and other utilities of the chassis.

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FIGURE 1.4

Stand-alone, “pizza box” system

T x R x 1

T x R x

2 T x R x 3

T x R x 4

T x R x

5 T x R x

6 T x R x 7

T x R x

8 T x R x

9 T x R x

10

Since the data forwarding plane is responsible for per-packet processing and handling, it is executed by high-speed devices such as ASICs or NPs, as described before. Control plane processing is usually executed by general-purpose processors, since the load on the control plane is signifi cantly less than that of the data forwarding plane.

There are several alternatives for components in the data forwarding plane that do the processing for various functions; these alternatives include switching chip sets, programmable communication components, Application Specifi c Stan- dard Products (ASSPs), confi gurable processors, Application Specifi c Instruction Processors (ASIPs), Field Programmable Gate Arrays ( FPGAs), NPs, and ASICs [176]. Among these options, ASICs and NPs are the two real options for the main processing units of network systems. These alternatives offer processing power and best fi t to the required applications.

It is worth noting here, that ASIC was perceived as a better solution, commer- cially, although it suffers from a very high development cycle and cost, and is abso- lutely infl exible. NPs, on the other hand, used to be more expensive, but had a short and low cost development cycle. However, as technological advantages made the size and cost of NPs and ASICs about equal, ASICs lost their advantage. Indeed, at the beginning of 2008, leading networking vendors announced that they had devel- oped NPs in-house in order to support their network systems, in addition to their continued use of NPs from various external vendors.

1.3 Network Elements 7

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1.4 NETWORK PROCESSORS

Network processors are categorized into three groups according to their use and the way they have evolved: entry-level or access NPs, mid-level processors (legacy and multiservice NPs), and high-end NPs that are targeted for core and metro networking equipment, usually on line cards.

Entry-level NPs, or access NPs, process streams of up to 1 to 2 Gbps packets, and are sometimes used for enterprise equipment. Applications for such access NPs include telephony systems (e.g., voice gateways and soft switches), Digi- tal Subscriber Loop (xDSL) access, cable modems, RANs, and optical networks (e.g., Fiber to the Home, Passive Optical Networks, etc.). A few examples of such NPs are EZchip’s NPA, Wintegra’s WinPath, Agere, PMC Sierra, and Intel’s IXP2300.

FIGURE 1.5

Multicard chassis system Backplane

Line Cards

Connectors Chassis

Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx

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Mid-level NPs (2–5 Gbps) contain two subgroups of NPs: legacy NPs and multiservice NPs, which are usually used for service cards of communication equipment, data center equipment, and multiservice platforms, in Deep Packet Inspection and Layer 7 applications (security, storage, compression, etc.). In the legacy subgroup, one can include the classical, multipurpose NPs like AMCC, Intel’s IPX, C-port, Agere, Vittese, and IBM’s NP (which was sold to Hifn). Examples of multiservice and application (Layer 7) NPs are Cisco’s QFP, Cavium, RMI, Broadcom, Silverback, and Chelsio.

High-end NPs (10–100 Gbps) are used mainly for core and metro networks, usually on the line cards of the equipment. These NPs can process hundreds of millions of packets per second, at wire-speed. Examples of such NPs are EZchip’s NPs, Xelerated, Sandburst (which was bought by Broadcom), Bay Microsystems, or the in-house Alcatel-Lucent SP2.

The choice of which category can signifi cantly impact the architecture of the NPs. In any case, the architecture and programming models of NPs are completely different from general purpose processors. NPs’ architecture can be characterized as being based on parallel processing and pipelining. Most NPs include integrated hardware assists such as integrated traffi c management and search engines, and also have high-speed memory and packet I/O interfaces. The main processors of NPs can be based on MIPS RISC processors, VLIW or reconfi gurable processors, or special packet processors (generic RISC, also called micro engine, pico engine, or Task-Optimized Processors [TOPs], etc.).

Network processors are sometimes distinguished from packet processors by being programmable, whereas packet processors are just confi gurable. The programming paradigms, models, styles, and languages that are used for NPs are also very different from those used for applications running on general purpose processors. No interrupts are used in NPs, and the main principle is to use an event-driven control program, in which packets dictate how the software runs. Network processors perform several key functions, including:

I Parsing the incoming frames in order to understand what they are, and where to fi nd the relevant information that is required for processing.

I Retrieving the relevant information from the frames, which may be complicated as encapsulation, variable fi elds length, and various levels of protocols may be involved.

I Deep packet analysis when required, such as understanding HTTP names, identifi cation of XML protocols, and so on. This may be required for priority assignments for various kinds of traffi c fl ows.

I Searching for related information in repositories; for example, routing tables, access lists, and so on.

I Classifying the frames according to the various forwarding and processing schemes that the frames should undergo.

I Modifying the frame’s contents or headers, possibly adding tags, changing addresses, or altering the contents.

I Forwarding, which may potentially be coupled with various traffi c management tasks such as metering, policing, shaping, queueing, scheduling, and statistics.

1.4 Network Processors 9

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Network processors appeared in the late 1990s, and fl ourished as major processor and network vendors led the NPs market (companies like Intel, IBM, Motorola, and Agere). Since the concept was new, it created a lot of enthusiasm, and caused a wave of established companies as well as many newcomers to invest and innovate. Then the market suffered a slowdown, and most players abandoned their NPs, or sold them. Some say this was a consequence of the “bubble” phenomena of the early 2000s that hit the telecom markets the most (for which NPs are targeted);

others say it was a normal market reaction to any new revolutionary technology—

the phase of absorbing, understanding, and applying the rules of natural selection ultimately narrows the fi eld until only the best remain.

Whatever the case may be, those who survived established themselves and their NPs as solid solutions for network systems, and the market fl ourished again. As of the beginning of 2008, major network vendors announced new generations of NPs that are the only way for them to compete and introduce network devices that can sustain network demands. Total investment in NPs development has reached approximately 1 billion U.S. dollars, as of 2008.

Companies that introduced various levels of NPs include:

Network and packet processors: Agere, Applied Micro Circuits Corp (AMCC, which bought MMC Networks), Bay Microsystems, C-Port (acquired by Motorola, which is now FreeScale), Cognigine, ClearSpeed Technology, Clearwater Networks (formerly XStream Logic), Entridia, Ethernity Networks, EZchip Technologies, Fast-Chip, Greenfi eld Networks (acquired by Cisco), Hyperchip, IBM (sold its NP line to Hifn), Intel, Internet Machines (changed to IMC semiconductor and a new business), Paion, PMC-Sierra, Sandburst (acquired by Broadcom), Sand- Craft, Silicon Access Networks, Sitera (acquired by Vitesse), Teradiant (formerly SiOptics), Terago Communications, Xelerated, Zettacom (acquired by Integrated Device Technology).

Access processors: Agere, AMCC, Audiocodes, Broadcom, Centillium, Conexant, Ethernity, EZchip Technologies, Freescale, Infi neon, Intel, Mindspeed, Octasic, Texas Instruments, TranSwitch, Wintegra.

1.5 STRUCTURE OF THIS BOOK

Part 1 is concerned with the fi rst part of the phrase Network Processors, the networks. This part contains a brief summary of networks’ technologies, standards and protocols. It begins in Chapter 2 with fundamentals, discussing data and telecommunication network technologies, then goes on to provide more in-depth description of contemporary converged networks, and ends with a description of access networks and home networking.

Chapter 2 describes network models and architectures, and then data networks—

namely, Ethernet and Internet Protocol networks. The basics of telecommunications networks are also described in this chapter (e.g., PDH and SDH/SONET networks), with an emphasis on relevant technologies for data applications.

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Chapter 3 focuses on converged networks. In these networks, data and telecommunications applications interface and mix, despite their very different natures. Data networks are bursty, and oriented toward connectionless traffi c, whereas telecommunications networks are streamed, and connection-oriented.

This chapter covers Asynchronous Transfer Protocol (ATM), Multiprotocol Label Switching (MPLS), Layer 2 and Layer 3 Virtual Private networks (VPNs), Carrier Ethernet, and Next Generation SONET/SDH technologies.

Chapter 4 discusses access and home networks, or customer premises networks.

These networks also use converged technologies, and equipment in these networks is increasingly based on network processors, as bandwidth and complexity reach a degree that justifi es them.

Part 2 is concerned with the second part of the phrase Network Processors, the processing and processors. It discusses the theory behind network processors, starting with frame and packet processing, the algorithms used, data structures, and the relevant networking schemes that are required for packet processing. Then it describes the theory behind the processors themselves, beginning with hardware (architecture), moving on to software (programming models, languages, and development platforms), and concluding with network processors’ peripherals.

Chapter 5 describes packet structure and all the processing functions that the packet must go through (i.e., framing, parsing, classifying, searching, and modifying). Searching (lookups) and classifi cation are treated in a detailed manner, since they are the most important and demanding tasks.

Chapter 6 addresses various aspects of packet fl ows, traffi c management, and buffers queuing. The chapter deals with Quality of Service (QoS) and related defi - nitions, and QoS control mechanisms, algorithms, and methods.

Chapter 7 describes the basic architectures and defi nitions of network processors. It covers various computation schemes, as well as network processing architectures in general. In particular, parallelism, threading, and pipelining are described. Other architectural components (e.g., I/O and memories) as well as interface standards are also described, in order to provide a comprehensive understanding of network processors’ design and interface, both at the system level (board and equipment), and at the networking level.

Chapter 8 describes programming models of network processors, as well as some important principles that are relevant to their programming, and concludes by describing the typical programming environment of network processors.

Programming a network processor is very different from programming any other processor. Parallel and pipelining processing and programming are covered.

Chapter 9 concludes the second part of the book with a description of two important network processors’ peripherals: switch fabrics (the interconnection functions), and coprocessors (for adjunct functions).

Part 3 examines the two subjects of networks and processing together with a concrete example of a network processor. It provides an in-depth description of EZchip’s network processor, which dominates the metro networks markets. It begins with a description of the hardware architecture, and then continues with the software architecture and programming. Following these chapters, each of the 1.5 Structure of the Book 11

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processors and the functional units of the NP is described in a separate chapter.

This part concludes with a comprehensive example of writing a program and using the network processor.

Chapter 10 describes the general architecture of EZchip’s NP-1 network processor, its heterogeneous pipeline of parallel processors, the TOPs, the interfaces, and the data fl ow of a packet inside the NP-1.

Chapter 11 explains how to program the NP, how to use the development environment of the network processor (including compiling, debugging, simulating, etc.), and how to run the programs (i.e., initializing the NP, downloading it, and working with the attached external host processor). It covers pipelining programming in depth, as well as the NP-1 Assembly.

Chapters 12, 14, and 15 outline the TOPparse, TOPresolve, and TOPmodify architectures, respectively, as well as their internal blocks and their instruction sets.

Simple examples are also given to demonstrate the use of these TOP engines.

Chapter 13 describes TOPsearch I very briefl y, and explains how to carry out various simple lookup operations with the TOPsearch engine by providing search keys, and getting results that match these keys.

Chapter 16 describes how to use the EZchip development system based on the example given in previous chapters; that is, how we load it, compile it, and debug it.

In addition, the chapter provides a quick and basic review of how to defi ne frames (which the simulator will use) and how to build the search database (structures that also can be used during the debugging phase).

Chapter 17 concludes the third part of the book by demonstrating how to use the EZchip NP, with a high-speed network application, a multi-Gbps routing, and an “on the fl y” screening fi lter for prescribed words that are to be identifi ed and masked. This chapter shows how to design, write, run, debug, and simulate an application with the Microcode Development Environment (MDE).

The EZmde demo program can be used to write a code, debug it, and simulate an NP with this code (with debugging features turned on). The EZmde can be down- loaded from http://www.cse.bgu.ac.il/npbook (access code: CSE37421), as well as the EZmde design manual.

1.6 SUMMARY

Network processors became an essential component for network system vendors.

This chapter outlined the ecosystem of NPs, the reasons for their importance, their growth, and their capabilities.

This subject is very dynamic; the interested reader may use periodicals, books [86, 92, 134, 135, 278], and Internet sources for remaining updated in the area of NPs.

Some excellent Internet sources for example are Light Reading [10] and the Linley Group [286].

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PART

This part of the book, Network Processors: Architecture, Programming, and Implementation, is concerned with the fi rst part of its title, Networks.

Since network processing is about processing packets and frames in networks, according to network protocols, demands, and behavior, it is essential to have a thorough knowledge of them before network processing is possible. For example, even analyzing a packet or a frame cannot be done without this understanding because the frame is structured according to the network protocol used, among many other issues.

To provide unifi ed terminology for this book, as well as some background on the relevant networking concepts, this part contains a brief summary of networks’ technologies, standards, and protocols. It begins with fundamentals, discussing data, and telecommunication network technologies, with an emphasis on the common networks that are most likely to be of interest to

Networks

1

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users who want to learn about network processing and processors. It then goes on to provide more in-depth descriptions of contemporary converged networks, as well as some good background on the technologies required for the reader who is interested in implementing network processors into metro or core networks. This part ends with a description of access networks, both wireline, and Radio Access Networks (RANs), and home networking.

As this is not a general textbook on networking, the descriptions provided in this part do not cover networking comprehensively; rather, they provide the necessary information required for and relevant to network processors. It contains the following chapters:

I Chapter 2—Networking Fundamentals

I Chapter 3—Networks Convergence

I Chapter 4—Access to Home Networks

Part 2 deals with the second part of this book’s title—processors and processing.

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CHAPTER

2

The previous chapter introduced the huge fi eld of networks—what a network processor is and how to use it, as well as services that are relevant and the challenges that make network processors so important. Before we jump into a discussion of the requirements, roles, and benefi ts of network processors, however, it is fi rst essential to be familiar with networking principles and technologies. Because we assume that most of the readers have at least some background knowledge of networking, our overview of the fundamentals of networking is quite general, and our descriptions are provided primarily in order to establish our terminology. In the next chapter, we move on to discuss more advanced, converged, and contemporary networking technologies.

When talking about networks in the context of network processors, it is important to remember that networks can be found in many places and in many shapes, on many kinds of media and serving many purposes. We focus on a small but important segment of networks, where network processors are used in network nodes to carry the networking functions. We are mainly concerned here with data networks and telecommunications networks. In this chapter, we begin by describing network models and architectures. Then we describe data networks—namely, Ethernet and Internet Protocol (IP) networks. Ethernet technology is used primarily and traditionally for data com munications in local area networks (LANs), and more recently in metropolitan area networks (MANs), or Metro networks. IP, which is a network of networks, is used as the underlying technology for the Internet and most wide area networks (WANs), including enterprise and campus networks. The basics of telecommunications networks are also described in this chapter, with an emphasis on relevant technologies for data applications.

In the next chapter, we describe contemporary networks—networks that com- bine data applications and services with telecommunication (or data networks, telecommunication networks, and what is in between them)—and elaborate on our discussion of converged data and telecommunication networks such as Multiprotocol Label Switching (MPLS) and metro networks technologies.

Networking Fundamentals

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A disclaimer: As mentioned above, we describe and generalize network concepts with a bias toward issues that are relevant to network processors. It is not the goal of this chapter or the next one to work systematically through an explanation of networking itself.

2.1 INTRODUCTION

In recent years, telecommunications, computers, networks, contents, and applications concepts have been combined and reshaped into new paradigms of infrastructure (networks and equipment), services (applications), and information (content). We introduce networks in this chapter from the perspective of infrastructure, that is, starting from the hosts, communication links and network equipment. We then go on to describe algorithms, protocols, and data structures that are part of the communication system.

Communication networks started by creating physical connections between peers, fi rst carrying analog-streamed data and then evolving to connections carrying digital-streamed data. With the ability to carry digital information came the pos- sibility of organizing and packaging information in packets for networking. Data communications networks were initially based on packets to carry data, whereas telecommunication networks were based on “circuits,” or channels of continuous bit streams. This was refl ected in two communication network paradigms—circuit switching and packet switching. In circuit switching, communication channels are dedicated to the communicating peers throughout the communication session, whereas in packet switching, the physical channels are shared by many communication sessions simultaneously, and packets are routed and switched between the communicating peers.

Circuit switching in its original form has been mostly replaced by packet- switching technologies that emulate the circuit-switching paradigm, providing virtual circuits between the communicating peers. Packet networks are subdivided into connection- oriented networks, and connectionless- oriented networks. The fi rst category describes “ordered” and reliable communications procedures like the telephone system (e.g., call set-up, transmission acknowledgment and verifi cation, and call termination), while the second describes “lighter” procedures and requirements that simplify the communication procedure (e.g., a mail or messaging system that does not require call set-up or the other procedures).

Today, almost the entire world of communication networks uses packets, and we are surrounded by packets fl ying and fl owing around us, both in wires and wireless. The rapid growth in networking and communications applications has been accompanied by exponential growth in the number and rate of packets fl owing around—packets that have to be analyzed, treated, processed, routed, and accounted for. This is the ground on which network processors emerged.

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2.2 Networks Primer 17

This chapter begins with a networks primer and some functional, physical, and architectural models. Then we describe networks according to their classifi cation as either Telecom or Datacom:

■ Pure Telecom networks (global, state, regional, or public networks):

– Plesiosynchronous Digital Hierarchy (PDH).

– Synchronized Optical Networks/Synchronous Digital Hierarchy (SONET/SDH).

– Optical networks.

■ Pure Datacom networks (offi ce or campus-wide private networks):

– Enterprise Ethernet.

– Internet Protocol.

The network technologies that are the most likely to be used by Network Processors applications are Ethernet (enterprise and carrier class), MPLS, and IP. Therefore, most of the description in this chapter is focused on these networks, with discussion of the other networks provided to fi ll out the general overview and to provide the reader with a framework of how networks are combined, relate to each other, and develop.

2.2 NETWORKS PRIMER

Networks exist with wide ranges of functions, speeds and distances—from a scale of millimeters to global span (including satellite networks). Networks are even used in chips (called Networks on Chips, NoCs). Networks’ speeds vary from very low bps to as many as thousands of Giga bps (Gbps, ending up in the Tera bps, Tbps range). As a rule of thumb, the smaller the span, the faster the network (Figure 2.1), and technology pushes the speed-span curve to ever higher speeds at larger spans.

1 Mbps 1 Gbps 1 Tbps

1 m 1 km 1000 km

Network Speed

Technology

FIGURE 2.1

Network span and speed

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Network processing covers several segments of networks and technologies, as described in this subsection, and shown in Figure 2.2. Computer-Peripheral Net- works (CNs) are entirely beyond the scope of this book, although, as we shall see in the following chapters, some switching systems are offered that are based on these kinds of networks. Personal area networks (PANs) are also beyond the scope of this book, although as pervasive and ubiquitous computing grows in popularity (and might be the “killer application” for PAN), it might overload the other kinds of networks that we are describing.

Local area networks are defi nitely relevant to network processors, and many applications of network processors are frequently used in these kinds of networks. Since it is important for writing network processors applications to abso- lutely understand how LANs operate (mainly Ethernet, the dominant technology), Ethernet will be covered here in some detail.

Wide area networks are also very relevant to network processors, and the domi nant internetworking technologies are also described here in detail. WAN is overlaid on metro or other telecom and core networks for providing data applications services.

Data networks are used mainly for computer data transfers, and telecommunications networks are used for streaming services (voice, video), as well as for large trunks of data channels to interconnect data networks. In Figure 2.2, for example, data networks are LANs and WANs, whereas Core networks are considered to be telecommunications networks. Metro networks can be either telecommunications networks or data networks, depending on the technology, the defi nition, and the current trend.

Despite the fact that the “convergence” trend of data, voice, and video is both exciting and long-awaited, there is (still) a separation between data networks and

Telecom Core/WAN Metro

1 Mbps 1 Gbps

1000 km 1 km

Data WAN LAN

100 Gbps

1 m PAN

CN

CN—Computer Peripherals Network PAN—Personal Area Network LAN—Local Area Network WAN—Wide Area Network

Access Networks

FIGURE 2.2 Relevant networks

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2.2 Networks Primer 19

telecommunications networks. Convergence is happening though, and buzzwords like triple-play or available services that are data-voice-video converged are here to stay (e.g., Voice over IP, VoIP; or TV over IP, IPTV ).

Another way to categorize networks is based on their functions and the rela- tionships between them (from which the span and the speed are derived). Sche- matically, at one extreme we have PAN, LAN, home networking, data-centers, and enterprise networking (Customer Premise’s Networks, CPN), with core networks at the other extreme (as shown in Figure 2.3). As mentioned above, WANs are overlaid on the access, metro, regional, and core networks.

Networks have basic hierarchies, as can be seen in Figure 2.3. Core networks (sometimes referred to as long-haul, or backbone networks) are networks that span globally, nationwide, and long distance (hundreds and even thousands of miles), carrying 10 Gbps and more, to which regional networks are connected through a Regional Central Offi ce (RCO).¹ The regional networks ( sometimes referred to as core-metro) are many tens of miles in span, carrying 10 Gbps, and

1Regional Central Offi ce (RCO, also called Toll-Center, TC) uses interfacing and switching equipment that is analogous to the class 4 telecommunications switches, or tandem switches, used in the traditional telephone network hierarchy.

Wireless (cellular, WiMax) Regional

Metro

Metro Access

Access

Access Access

CPN

CPN CPN

CPN

CPN Core

RCO (Regional Central Office) LCO (Local Central Office) Remote Units

CPE (Customer Premise’s Equipment) CPN—Customer Premise’s Network

Residential Enterprise—

Branch Office

Enterprise—

Headquarters

Content Provider (TV, information)

Service Provider (storage, hosting) FIGURE 2.3

Network hierarchy

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connecting metro networks through a Local Central Offi ce (LCO).² The metro networks (sometimes referred to as metro edge, metro access, or aggregation networks) run at 2.5 to 10 Gbps, are up to a few tens of miles, and are connected to the access networks through remote units. The access networks have a span of about a mile, run up to 2.5 Gbps, and connect the CPN to the entire network through the customer premise’s equipment. At the customer premises, there are many types of networks, depending on the type of customer— residential, enterprise, content or service provider, and so on. Wireless networks are also part of this setup, where public wireless networks such as cellular and WiMAX are connected like the metro networks (sometimes through the metro networks), and private networks (i.e., residential or enterprise) are within the customer premises (e.g., Wi-Fi and all PAN networks).

Although most readers are familiar with networks topologies (Figure 2.4), it is worth noting that most networks today are either based on a star topology (like most enterprise networks), or a ring topology (like most regional and metro networks).

2Local Central Offi ce (LCO, also called End-Offi ce, EO) uses interfacing and switching equipment that is analogous to the class 5 telecommunications switches, or telephone exchange, used in the traditional telephone network hierarchy. Actual telephones were connected to this equipment, whereas today metro or access trunks are connected to the LCO.

(a) Bus (b) Ring (c) Star

(d) Tree of rings (e) Tree of stars

FIGURE 2.4 Network topologies

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2.3 Data Networking Models 21

2.3 DATA NETWORKING MODELS

Network modeling can be done in any one of the following two ways: either by modeling the data and the communications’ protocols between the communica- tors, or by modeling the physical components of the network and their intercon- nections. Eventually, the two models converge into one representation of network modeling.

Communication between two nodes can be done by a program that handles everything from taking care of bit and byte ordering and transmission or receiv- ing to inter-application inputs and outputs. Such a program also handles all aspects of networking (routing and forwarding), error recovery, handshakes between the applications, data presentation, and security. These programs existed in the early days of data communications; however, in modern, sophisticated networks, it is now impractical not only to handle communications programs in this way, but also to maintain them or to reuse parts of them when required.

As data communications and telecommunications programming, interfaces, and equipment grew more sophisticated, the International Standard Organiza- tion (ISO) suggested a structured, layered architecture of networking called Open System Interconnect (ISO/OSI). The ISO/OSI is an abstract reference model of layered entities (protocols, schemes), depicting how each entity interfaces with the entities that reside in the layers directly above and below it (except for the lowest layer, which communicates only with peer entities). At about the same time, the U.S. Department of Defense (DoD) offered another layered model that concentrated on data-network modeling. These two models provide fundamental concepts in communications, and most systems and defi nitions use their language.

According to the ISO/OSI model, which is also called the seven-layer model, any two peered layers interact logically, carrying the relevant data and parameters, and executing the functionality of that layer. These layers actually interface with the layers above or below them (i.e., they hand them the data and parameters). The seven layers are shown in Figure 2.5.

The physical layer handles bits and the physical transmission of bits across the communication channel through some sort of medium (whether it be a kind of wire, fi ber, radio-waves, or light). The second layer (referred to as L2) is the data- link layer, which takes care of framing bytes or a block of bytes, and handles the integrity and error recovery of the data transmitted at this level between two nodes connected by a physical channel. The third layer (referred to as L3) is the network layer, which is responsible for carrying blocks of data between two or more nodes across a network that is composed of multiple nodes and data-links; L3 responsi- bilities include the required addressing, routing, and so on. The transport layer is the lowest application (or host) layer that carries data between applications (or hosts), independently and regardless of the networks used. It is responsible for the end-to-end data integrity and reliability, and it works through either connection or

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connectionless transport mechanisms.³ The session layer controls the session (e.g., determining whether the relationship between the nodes is peered or master/slave;

establishing, maintaining, and terminating a session). The presentation layer determines such things as the format, encryption, compression, structure, and encoding of the application data. The application layer determines the way the application uses the communication facilities, that is, e-mailing, fi le transfer, and so on.

The upper four layers (the transport, session, presentation, and application) are considered the host layers, while the lower three (the physical, data-link, and network) are the network layers. The network layers are considered the most important in network processing; nevertheless, many networking decisions are made based on the upper four layers, such as priority, routing, addressing, and so on.

The equivalent data-networking model of the DoD (often called the Internet model, or more commonly, the TCP/IP model), is simpler, and contains fewer layers.

(It originally had only four layers, without the physical layer; see Figure 2.6.) The ISO/OSI model layers are not mapped exactly onto the TCP/IP model layers; however, roughly speaking, the TCP/IP model shrinks all host layers into the host-to-host (transport) layer (L4), and adds a new, internetworking layer that is composed mainly of the ISO/OSI network layer (L3). TCP/IP’s network layer (L2) is composed mainly of the functionalities of ISO/OSI’s data link layer and some of its network layer. Recently, this model has been amended by a “half” (or a “shim”)

3Connection and connectionless communication interfaces are fundamental in networking, and the concepts are briefl y described in the introduction. In connection-oriented communication, one node asks the other to establish a link (“call setup”), and once allowed, uses this link until it “hangs up”

(like a telephone conversation). In connectionless communications, the originating node simply

“throws” data to the network (like letters or e-mails).

Medium Physical

Data Link Network Transport Session Presentation

Application

Physical Data Link

Network Transport Session Presentation

Application

L 2 L 3 L 4 L 7

FIGURE 2.5

ISO/OSI seven layers model