HEXFET ® Power MOSFET

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IRL2203S

HEXFET ^® Power MOSFET

S D

G

V

DSS

= 30V R

DS(on)

= 0.007Ω

I

_D

= 100A

Parameter Typ. Max. Units

R_θJC Junction-to-Case ––– 1.2

R_θJA Junction-to-Ambient ( PCB Mounted,steady-state)** ––– 40

Thermal Resistance

°C/W l

Logic-Level Gate Drive

l

Surface Mount

l

Advanced Process Technology

l

Dynamic dv/dt Rating

l

175°C Operating Temperature

l

Fast Switching

l

Fully Avalanche Rated

Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.

The D²Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on- resistance in any existing surface mount package. The D²Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application.

Description

Parameter Max. Units

I_D @ T_C = 25°C Continuous Drain Current, V_GS @ 10V 100

I_D @ T_C = 100°C Continuous Drain Current, V_GS @ 10V 71 A

I_DM Pulsed Drain Current 400

P_D@T_A = 25°C Power Dissipation 3.8 W

P_D@T_C = 25°C Power Dissipation 130 W

Linear Derating Factor 0.83 W/°C

V_GS Gate-to-Source Voltage ± 20 V

E_AS Single Pulse Avalanche Energy 390 mJ

IAR Avalanche Current 60 A

E_AR Repetitive Avalanche Energy 13 mJ

dv/dt Peak Diode Recovery dv/dt 1.2 V/ns

TJ Operating Junction and -55 to + 175

T_STG Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )

°C

Absolute Maximum Ratings

D

²

Pak

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Parameter Min. Typ. Max. Units Conditions

V_(BR)DSS Drain-to-Source Breakdown Voltage 30 ––– ––– V V_GS = 0V, I_D = 250µA

∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.035 ––– V/°C Reference to 25°C, ID = 1mA ––– ––– 0.007 VGS = 10V, ID = 60A ––– ––– 0.01 VGS = 4.5V, ID = 50A

VGS(th) Gate Threshold Voltage 1.0 ––– 2.5 V VDS = VGS, ID = 250µA

gfs Forward Transconductance 47 ––– ––– S VDS = 25V, ID = 60A

––– ––– 25

µA V_DS = 30V, V_GS = 0V

––– ––– 250 VDS = 24V, VGS = 0V, TJ = 150°C Gate-to-Source Forward Leakage ––– ––– 100

nA VGS = 20V Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V

Q_g Total Gate Charge ––– ––– 110 I_D = 60A

Qgs Gate-to-Source Charge ––– ––– 31 nC VDS = 24V

Qgd Gate-to-Drain ("Miller") Charge ––– ––– 57 VGS = 4.5V, See Fig. 6 and 13

td(on) Turn-On Delay Time ––– 15 ––– VDD = 15V

tr Rise Time ––– 210 –––

ns ID = 60A

td(off) Turn-Off Delay Time ––– 29 ––– RG = 1.8Ω, VGS = 4.5V

t_f Fall Time ––– 54 ––– R_D = 0.25Ω, See Fig. 10

Between lead,

––– –––

and center of die contact

Ciss Input Capacitance ––– 3500 ––– VGS = 0V

Coss Output Capacitance ––– 1400 ––– pF VDS = 25V

Crss Reverse Transfer Capacitance ––– 690 ––– ƒ = 1.0MHz, See Fig. 5

Electrical Characteristics @ T

_J

= 25°C (unless otherwise specified)

R_DS(on) Static Drain-to-Source On-Resistance

I_GSS

I_DSS Drain-to-Source Leakage Current

L_S Internal Source Inductance 7.5 nH

Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 )

Notes:

^VDD = 15V, starting T_J= 25°C, L = 220µH R_G= 25Ω, I_AS= 60A. (See Figure 12)

Pulse width ≤ 300µs; duty cycle ≤ 2%.

Calculated continuous current based on maximum allowable junction temperature; for recommended current-handling of the package refer to Design Tip # 93-4

^ISD ≤ 60A, di/dt ≤ 140A/µs, V_DD≤ V_(BR)DSS, T_J≤ 175°C

Parameter Min. Typ. Max. Units Conditions

IS Continuous Source Current MOSFET symbol

(Body Diode) ––– –––

showing the

ISM Pulsed Source Current integral reverse

(Body Diode) ––– –––

p-n junction diode.

V_SD Diode Forward Voltage ––– ––– 1.3 V T_J = 25°C, I_S = 60A, V_GS = 0V trr Reverse Recovery Time ––– 94 140 ns TJ = 25°C, IF = 60A

Qrr Reverse RecoveryCharge ––– 280 410 nC di/dt = 100A/µs

Source-Drain Ratings and Characteristics

S D

G

100 400

A

Uses IRL2203N data and test conditions.

** When mounted on FR-4 board using minimum recommended footprint.

For recommended footprint and soldering techniques refer to application note #AN-994.

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Fig 1. Typical Output Characteristics, T

_J

= 25

^o

C

Fig 2. Typical Output Characteristics, T

_J

= 175

^o

C

Fig 4. Normalized On-Resistance Vs. Temperature

Fig 3. Typical Transfer Characteristics

1 10 100 1000

0.1 1 10 100

I , Drain-to-Source Current (A)D

V , Drain -to -S o urce Vo lta ge (V )_{D S} A 2 0µ s PU L SE W ID TH T = 2 5°C_J

VGS TOP 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V

2.5 V

1 10 100 1000

0.1 1 10 100

I , Drain-to-Source Current (A)D

V , Drain -to -S o urce Vo lta ge (V )_{D S} A 2 0µ s PU L SE W ID TH T = 1 75 °C

VGS TOP 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V

2 .5V

J

1 1 0 1 0 0 1 0 0 0

2 . 0 3 . 0 4 . 0 5 . 0 6 . 0 7 . 0 8 . 0 9 . 0

T = 2 5 °CJ

V , Ga te -to -S o u rce V o lta g e (V )G S

DI , Drain-to-Source Current (A)

T = 1 75 °CJ

A V = 1 5 V

2 0 µ s P U L SE W ID TH

DS

0 . 0 0 . 5 1 . 0 1 . 5 2 . 0

- 6 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0

T , Junctio n Te m p era ture (°C )J

R , Drain-to-Source On ResistanceDS(on) (Normalized)

V = 10V G S A I = 100 A_D

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Fig 8. Maximum Safe Operating Area Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode Forward Voltage

0 2000 4000 6000 8000

1 10 100

C, Capacitance (pF)

V , Drai n-to -So urce V oltag e (V)D S A V = 0 V, f = 1M H z

C = C + C , C SH O RTE D C = C

C = C + C G S

is s gs gd ds rs s gd

o ss ds g d

C is s C o s s

C rs s

0 3 6 9 12 15

0 30 60 90 120 150

Q , T o ta l G ate Ch arg e (n C)_G V , Gate-to-Source Voltage (V)GS

A FOR TE S T CIR C UIT S E E FI GU RE 1 3 V = 24 V

V = 15 V I = 60A_D

D S D S

1 0 1 0 0 1 0 0 0

0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5

T = 25 °C_J

V = 0 V G S

V , S o urce-to -Drain Vo lta ge (V )

I , Reverse Drain Current (A)

S D

SD

A T = 17 5°C_J

1 10 100 1000

1 10 100

V , Dra in -to-So urce Vo ltag e (V)_{D S}

I , Drain Current (A)

O PER ATIO N IN TH IS AR EA L IM ITED BY R

D

DS (o n)

10 µs

10 0µs

1m s

10m s

A T = 25 °C

T = 17 5°C S ing le Pulse

C J

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Fig 10a. Switching Time Test Circuit

V_DS 90%

10%

V_GS

t_d(on) t_r t_d(off) t_f

Fig 10b. Switching Time Waveforms

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

VGS

RG

D.U.T.

5.0V

+

-VDD

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case Fig 9. Maximum Drain Current Vs.

Case Temperature

0 2 0 4 0 6 0 8 0 1 0 0

2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 7 5

C I , Drain Current (Amps)D

T , C ase T em pe ra ture (°C )

A L IM ITED BY PAC KA GE

0 . 0 1 0 . 1 1 1 0

0 . 0 0 0 0 1 0 . 0 0 0 1 0 . 0 0 1 0 . 0 1 0 . 1 1 1 0

t , R ectan gu lar P ulse D u ra tion (se c)₁

thJC

D = 0.50

0.01 0.02 0.05 0.10 0.20

S INGLE PULS E ( THER MAL R ESP ONS E)

A

Thermal Response (Z )

P

t 2 t1 D M

N otes : 1. D uty fac tor D = t / t

2. P ea k T = P x Z + T

1 2

J D M thJ C C

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5.0 V

Fig 13b. Gate Charge Test Circuit Fig 13a. Basic Gate Charge Waveform

Fig 12b. Unclamped Inductive Waveforms Fig 12a. Unclamped Inductive Test Circuit

tp

V_{(BR )D SS}

I_AS

R G

IA S 0 . 0 1Ω t p

D . U . T V D S L

+ - V D D D R IV E R

A 1 5 V

20 V5.0 V

Fig 12c. Maximum Avalanche Energy Vs. Drain Current

0 200 400 600 800 1000

25 50 75 100 125 150 175

J E , Single Pulse Avalanche Energy (mJ) AS

A Sta rtin g T , Ju nction Te mpe ratu re (°C) V = 1 5V

I TO P 24 A 4 2A B OTTO M 60 A

D D

D

Q

_G

Q

_GS

Q

_GD

V

_G

Charge

D.U.T. V_DS

I_D I_G

3mA V_GS

.3µF 50KΩ 12V .2µF

Current Regulator Same Type as D.U.T.

Current Sampling Resistors

+ -

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P.W. Period

di/dt Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop Re-Applied

Voltage Reverse Recovery Current

Body Diode Forward Current

V_GS=10V

V_DD

I_SD Driver Gate Drive

D.U.T. I_SDWaveform

D.U.T. V_DSWaveform

Inductor Curent

D = P.W.

Period

+ - +

+

- + -

-

Fig 14. For N-Channel HEXFETS

*

VGS = 5V for Logic Level Devices

Peak Diode Recovery dv/dt Test Circuit

RG

V_DD

• dv/dt controlled by R_G

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test D.U.T Circuit Layout Considerations

• Low Stray Inductance • Ground Plane

• Low Leakage Inductance Current Transformer

*

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Package Outline — D ² Pak

Dimensions are shown in millimeters (inches)

P AR T NU M BE R I NT E RN A TIO N AL

R E C TIF IE R L OG O E X AM PL E : T H IS I S A N IR F1 0 10

W IT H A S S E MB L Y L OT CO D E 9 B1 M

A SS E MB L Y L OT C OD E

D A TE C OD E (Y YW W ) Y Y = YE A R W W = W EE K 9 2 46

IRF 10 10 9B 1 M

A

Part Marking

P A R T N U M B E R IN T E R N A T I O N A L

R E C T IF IE R L O G O

D A T E C O D E (Y Y W W ) Y Y = Y E A R W W = W E E K A S S E M B L Y

L O T C O D E

F 53 0 S 9 B 1M

9 2 4 6 E X A M P L E : T H IS I S A N I R F 5 30 S

W IT H A S S E M B LY L O T C O D E 9B 1 M

A 10.16 (.400)

RE F .

6.47 (.255) 6.18 (.243)

2.61 (.103) 2.32 (.091) 8.89 (.350) RE F.

- B - 1.32 ( .052) 1.22 ( .048)

2.79 (.110) 2.29 (.090)

1.39 (.055) 1.14 (.045) 5.28 ( .208)

4.78 ( .188) 4.69 (.185) 4.20 (.165) 10.54 (.415)

10.29 (.405) - A -

2

1 3

15.49 (.610) 14.73 (.580)

3X 0.93 (.037) 0.69 (.027) 5.08 (.200)

3X1.40 (.055) 1.14 (.045) 1.78 (.070) 1.27 (.050) 1.40 ( .055) M AX.

NO TE S:

1 DIM ENSIO NS AF T ER S OLDE R DIP.

2 DIM ENSIO NING & TO LERAN CING PER ANS I Y14.5M, 1982.

3 CO NTRO LLING DIME NS IO N : INC H.

4 HE AT SINK & LE AD D IM ENS IONS DO NO T INCLUDE B UR RS . 0.55 (.022) 0.46 (.018)

0.25 (.010) M B A M MINIM UM RE CO MM ENDED F OO TP RINT

11.43 (.450)

8.89 ( .350)

17.78 ( .700)

3.81 (.150) 2.08 (.082) 2X LEA D AS SIG NMEN TS

1 - GA TE 2 - DRAIN 3 - SO URCE

2.54 (.100) 2X

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Dimensions are shown in millimeters (inches)

3 4

4 T R R

F E E D D IR E C T IO N

1 .85 ( .07 3) 1 .65 ( .06 5)

1 .60 (.063 ) 1 .50 (.059 ) 4.10 ( .16 1) 3.90 ( .15 3)

TR L F E E D D IR E C T IO N

1 0 .9 0 (.4 2 9 ) 1 0 .7 0 (.4 2 1 )

1 6 .1 0 (.6 3 4 ) 1 5 .9 0 (.6 2 6 )

1 .7 5 (.0 6 9 ) 1 .2 5 (.0 4 9 ) 1 1 . 6 0 (. 4 5 7 ) 1 1 . 4 0 (. 4 4 9 )

1 5 . 4 2 (. 6 0 9 ) 1 5 . 2 2 (. 6 0 1 )

4 .7 2 (.1 3 6 ) 4 .5 2 (.1 7 8 ) 2 4 . 3 0 (. 9 5 7 ) 2 3 . 9 0 (. 9 4 1 ) 0 .3 6 8 (.0 1 4 5 ) 0 .3 4 2 (.0 1 3 5 ) 1 . 6 0 (. 0 6 3 )

1 . 5 0 (. 0 5 9 )

1 3 . 50 (.5 3 2 ) 1 2 . 80 (.5 0 4 )

330.00 (14.173) MAX.

2 7 .4 0 (1 . 07 9 ) 2 3 .9 0 (. 9 41 )

60 .0 0 (2. 3 6 2) M IN .

3 0 . 40 (1 .1 9 7) M A X . 26.40 (1.039)

24.40 (.961) N O T E S :

1. C O M F O R M S T O E IA -4 1 8.

2. C O N T R O L LI N G D I M E N S IO N : M IL L IM E T E R . 3. D IM E N S I O N M E A S U R E D @ H U B .

4. IN C L U D E S F L A N G E D IS T O R T IO N @ O U T E R E D G E .

WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 7/96

HEXFET ® Power MOSFET

IRL2203S