Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

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Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM

and UMTS Radio Standards

Nadia Khouja, Khaled Grati, Adel Ghazel CIRTA’COM Laboratory Technologic Parc El Ghazala

2089 Ariana Tunisia

Bertrand Le Gal

IMS Laboratory Bordeaux-1 University of Bordeaux Bordeaux, France

Abstract—This work presents a low-power multistandard decimation and channel selection filter architecture. The filter is suitable after an over-sampling sigma-delta converter and performs decimation in two stages. The first stage is a modified structure of the Cascade of Integrators-Combs (CIC) filter and allows reducing sampling rate downto only the double of the Nyquist frequency. The second stage composed of classical FIR filter, has relaxed specifications and performs channel selection.

Implementation of the proposed filter for UMTS and GSM standards shows good filtering performances. The signal to ratio measured for UMTS is 14,65 dB and for GSM 26,96 dB which satisfy largely the standards requirements. Implementation on ASIC 65-nm process technology shows power consumption gain of 14% in comparison to previously proposed low-power architecture.

Keywords-component; Low power, Multistandard receiver, channel selection, decimation, CIC filter, sigma-delta converter

I. INTRODUCTION

Multi-standard wireless receivers are more and more required because they support different communication standards like GSM, UMTS etc…. The multi-standard wireless receivers handle different frequency band and bandwidth, and thus have to be configurable. Therefore, the Software Radio receiver concept is a good candidate for the design of multi-standard wireless receivers.

In fact, Software Radio deployment requires the design and implementation of radio software and electronic circuits that can support target functionalities. Main constraints delaying reaching software radio objectives are related to radio signals digitization issues. The optimum solution proposed nowadays consists on using sigma delta modulator followed by digital filtering for decimation and channel selection.

Multiple contributions are proposed in previous works for multi-standard digital filters for decimation and channel selection [1]. The Cascade of Integrators-Comb filter (CIC) is largely used as first stage of the channel selector filter post sigma-delta conversion [2, 3, 4, 5]. In fact, in its recursive form, the CIC filter is multiplierless and presents low- complexity properties. In addition this form allows high

configurability of the filter. The main drawback of the recursive form is however its higher power consumption [4].

References [3, 5], proposed a three stage architecture filter performing channel selection for UMTS, GSM and DECT standards that achieves good performances results in terms of SNR and allows reducing the computation complexity and surface occupation of the filter but without looking to power consumption reduction.

More recently, several solutions are proposed in litterature and aims to improve the attenuation of the basic CIC filter out of the band. The sharpening technique [7] applied to CIC filter improves the out of band attenuation and preserves the signal bandwidth. However, it increases the hardware complexity.

Cosine prefilters introduced in [8] allows increasing performances of the basic CIC filter but have to work at the highest frequency which increase power consumption of the filter. The Rotated Sinus Cardinal filter (RS filter) increases the attenuation out of the band at the price of two multipliers working at the highest rate [6].

The objective of this paper is to propose a low power design and of a new digital filter processor for multi-standard radio signals decimation and channel selection. Low power design is proposed first at algorithmic level by defining new filters transfer functions and second at circuit level by optimizing filters hardware implementation and clock control.

This paper is organized as following: Section II presents the design of the proposed multi-standard decimation and channel selection filter and details filter design specifications for UMTS and GSM radio standards. Design considerations of filters circuits’ implementation are presented in Section III.

Section IV discuses implementation and obtained results.

Finally, conclusions are given in section V.

II. FILTER DESIGN SPECIFICATIONS

A novel two stages digital filter, as indicated in Fig. 1, is proposed to handle receiver radio signals decimation and channel selection after the Sigma-Delta modulator. The first stage is a cascade of two filters composed of a modified CIC filter followed by a new compensation filter. An FIR filter, having relaxed specifications, in the second stage, is designed

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to perform multi-standard channel selection.

Figure 1. Proposed 2-stages structure of the decimation and channel selection filter

The objective of low power filtering circuit is looked for at two levels. At algorithmic level new transfer functions are defined to reduce filters processing while respecting stability and phase linearity criteria’s. Algorithmic level design is completed by circuit level optimizations to ensure the best power reduction for the hardware solution of the new proposed filter.

A. Modified CIC filter design considerations.

In order to conserve pass-band droop of basic CIC filter but to increase the attenuation out of the band more zeros need to be introduced in the filter transfer function by comparison to basic CIC filter. Hence, a modified CIC filter expression is defined as indicated in equation 1.

( )

_H _z_H _{( )}_z

z M z

z z

H _m

k k M

M

mc ( )

cos 2 1

1 1

1

2 1

2

1 1 =

⎟⎟

⎟

⎠

⎞

⎜⎜

⎜

⎝

⎛

+

⎟⎠

⎜ ⎞

⎝

− ⎛

× +

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

= −

−

π (1) Where M is the oversampling ratio of the sigma-delta

modulator, k1 and k2 are respectively the orders of the basic CIC filter and the Hm(z) filter.

The modified CIC filter Hmc(z) can be considered as a product of two filters H(z) and Hm(z), each of them is stable and has linear phase. H(z) is a basic CIC filter and Hm(z) is a cosine filter. Zeros positions of the filter Hm(z) are given in equation 2, in the z domain.

, 0,..., 1

) 1 2 (

−

=

+

M i

e

z ^M

j i i

π

(2) The Hm(z) filter has also two poles given by equation 3.

jM jM

e p e

p

π

π −

=

= 0

0 ; (3) These two poles are cancelled by the two first conjugate zeros of the numerator part which means that Hm(z) is a stable FIR filter. Fig.2 illustrates zeros’s positions of the modified CIC filter Hmc(z). It shows that a new zero is inserted at the middle of each two consecutives zeros of the H(z) filter.

To reduce filter processing frequency the cascade equivalence schema, as indicated in Fig. 3, is proposed for the modified CIC filter implementation when k1 and k2 are equal to one. The inserted decimation by M/2 allows reducing the operation frequency of the Hmc(z) numerator part down to2× f_N . fN is the input signal Nyquist frequency.

The frequency response of the modified CIC filter is given in Fig.4 for M=16, k1= 1 and k2 =1. This result confirms our design objective to increase the out of band filter attenuation of the modified CIC filter while conserving the same pass- band droop as the basic CIC filter.

Figure 2. Zeros position of the modified-CIC filter for M = 4.

( )

^z¹ ²

cos 2 1

1

−

−+

×

− πM z

1 − z

⁻²

1 + z

⁻²

1

1 − z

−

²

M

Figure 3. Cascade equivalence implementation of the modified CIC filter

0.5 1 1.5 2

x 10⁴ -100

-80 -60 -40 -20 0

Frequency (KHZ)

dB

CIC filter Hm filter Hmc filter

Figure 4. Frequency response of the modified CIC-filter B. Compensation filter design considerations.

The fast drop in band lets the Hmc(z) filter not convenient for high orders decimation ratios. To overcome this limitation a second filter Hp(z) is proposed to follow the Hmc(z) filter in order to cancel the attenuation in the band of the Hmc(z) filter.

To achieve required compensation the Hp(z) filter is defined as given in equation 4. This filter operates at only 2× f_N frequency rate. Hp(z) filter stability condition is respected by having the module of a less than one

(

^a ^≺ ¹

)

^.

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1

1 2

) 1 (

n

p z a z

H ⎟

⎠

⎜ ⎞

⎝

⎛

= + ₋ (4) To verify phase linearity the phase response of the Hp(z) filter for different values of a is plotted in Fig. 5. This figure shows that Hp(z) filter phase can be considered as linear in the base band interval. The length of this interval depends on parameter a. When a is very close to one, the interval is very close to [-B, B], where B is the signal bandwidth.

To guarantee phase linearity only for the band of interest the parameter a is chosen to respect both following conditions:

- maximum linearity in the band of interest - minimum ripples in the band of interest

Figure 5. Phase response of the Hp(z) filter for different values of a Fig.6 gives the response amplitude of the Hp(z) filter for a=

0.9375. The extremum of the Hp(z) filter at the frequency fN

×

2 corresponds to the first zero of the Hmc(z) filter.

Hence, the Hp(z) filter gain profile allows the compensation of the Hmc(z) filter attenuation. Obtained compensation results is shown on Fig.7 for a= 0.9375.

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

0 5 10 15 20 25

Normalized frequency

dB

Figure 6. Frequency response of the Hp(z) filter for a=0.9375 Bi-mode GSM and UMTS radio receiver filtering processing is considered as an application for the novel filter design proposed in section II. The bi-mode filter is designed to meet

the signal to noise ratio (SNR) requirement for the worst case blocking profile and adjacent channel interferers for both GSM and UMTS standards.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-30 -25 -20 -15 -10 -5 0

Frequency (KHz)

dB

Hmc filter Hmc after compensation

Figure 7. Compensation principle for a=0.9375

C. Filter specifications for UMTS standard

The UMTS standard uses a QPSK modulation for a signal rate of 3840 Ksym/s. The oversampling ratio is fixed to 16 leading to a sampling frequency equal to 16 x 3840 KHz. The SNR imposed by the standard should be at minimum equal to 6.8 dB [9].

The decimation by 8 achieved by the first stage of the proposed filter implies that noise contained in the frequency band [5760 kHz - 7680 kHz] will be responsible of alias generation after decimation. In order to obtain enough contribution to reach required SNR in that band a cascade of two modified CIC filter is proposed for UMTS as given in equation 9. The amplitude response of the considered filter is given in Fig.8.

2 2 1 2 16

1 16

) 16 cos(

2 1

1 1

) 1

( ⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

×

−

× +

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

= − ⁻₋ ⁻ ₋ ₋

z z z z

z z H_mc

π (9)

0 0.5 1 1.5 2 2.5 3

x 10⁴ -100

-90 -80 -70 -60 -50 -40 -30 -20 -10 0

Frequency (Khz)

db

Figure 8. Frequency response of the Hmc(z) for UMTS standard In order to compensate the attenuation in the band of interest, a three order cell compensation filter, as expressed in

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equation 10, is designed. This filter will operate at the frequency 7680 kHz.

The parameter a is chosen as sum of power of two terms in order to simplify the hardware implemenation of the filter. For UMTS standard, a is chosen equal to 0.9375.

3 1

1 2

) 1

( ⎟

⎠

⎜ ⎞

⎝

⎛

= + ₋

z z a

H _p (10)

The second stage of the decimation filter should eliminate all interferers, blockers and residual noise. It also performs the channel selection. A FIR filter of 24^th order is designed in order to guarantee a good SNR ratio.

D. Filter specifications for GSM standard

The GSM standard uses a GMSK modulation for a signal rate of 270.833 Ksym/s. The oversampling ratio is fixed to 48 and the sampling frequency leading to a sampling frequency equal to 48 x 270.833 = 13MHz. The GSM required SNR should be at minimum equal to 9 dB [10]. To reach better SNR performances the modified CIC filter for the GSM is designed as given in equation 11.

⎟⎟

⎟

⎠

⎞

⎜⎜

⎜

⎝

⎛

+

×

−

× +

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

= − ⁻₋ ⁻⁴⁸ ₋₁ ₋₂

2 1 48

48) cos(

2 1

1 1

) 1

( z z

z z

z z H_mc

π (11)

The same compensation filter, as designed for the UMTS given by equation 10, is proposed for the GSM. The second stage of the filtering chain is a FIR filter of 47^th order and performs decimation by 2.

III. RECONFIGURABLE DESIGN HARDWARE

In order to reduce hardware circuit complexity a compact architecture is designed to support multi-standard decimation and channel selection filter. As illustrated in Fig. 9, designed filter circuit is composed of a common first stage for GSM and UMTS standards but two separate channel selection filters.

The command unit is designed to support the clock-gating method that allows clock delivery to only working blocks [11]. This control method eliminates power consumption of non used blocks.

The first common stage is a cascade of three filters: H(z), Hm(z) and Hp(z). In their recursive form, H(z) and Hp(z) are common for the two standards. In the FIR form, the Hm(z) filter order is equal to 46 for GSM and 28 for UMTS standard.

In order to increase common processing for both standards the polyphase decomposition into sub-filters stages Hci is proposed to reduce the implementation complexity of Hm(z) filter. Since decimation ratios required for these stages are equal to 8 for UMTS and 24= 8x3 for GSM, it was possible to found a common FIR implementation architecture for both standards. Based on presented design considerations resulting implementation structure of the first common stage is shown

on Fig. 10. Each sub-filter Hci of the Hm(z) filter is a 4^th order in case of UMTS and 6^th order in case of GSM.

Figure 9. Proposed Multistandatd decimation filter architecture

2

z1

1

1 ⎟

⎠

⎜ ⎞

⎝

⎛

− ⁻

( )

¹⁻^z⁻² ² 1 ²z¹³

1 ⎟

⎠

⎜ ⎞

⎝

⎛ +a ⁻

Figure 10. Implementation architecture of the first stage filter Fig. 11 gives implementation details of Hci sub-filter.

Coefficients are 9 bits length for the two standards and are selected depending on the handled standard.

For UMTS signals processing not used registers are disconnected using clock-gating method. The clock received by Hci sub-stage is a pulse repeated each 8 initial clock cycles (decimation factor). The clock at the output of sub-filters is obtained for the case of GSM standard by a simple clock division by 3.

In order to evaluate power consumption reduction for designed 2-stages based filter circuit we propose to compare its hardware performances with best optimized circuit for 3- stages based filter proposed in previous research work [12].

The 3-stages based filter processor for GSM and UMTS standards, as indicated in Fig.12, is composed of a 6^thorder basic CIC filter implemented in its recursive form, a Halfband filter and two FIR filters of order 23 and 47 respectively for UMTS and GSM standards. Clock-gating method is also used for timing control [12].

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Figure 11. Implementation architecture of Hci sub-filter

Figure 12. 3-stages based filter processor for GSM and UMTS IV. IMPLEMENTATION AND RESULTS

Filter designed circuits are implemented in ASIC 65-nm process technology. SYNOPSYS’ DESIGN-COMPILER tool was used, at frequency 80 MHz, to evaluate filters effects on processed signals and hardware circuit performances in term of area, power and latency.

For each standard the desired base band modulated signal plus interferers are applied at the filter circuit input to evaluate filter processing performances of proposed design.

Fig. 13 illustrates filtering performances in term of SNR for UMTS in the presence of an interferer (+41 dB) located at the frequency (1.9 + 5) MHz. The SNR at the output of the filter is equal to 14.65 dB which is greater than the 6.8 dB required by the UMTS standard.

Fig. 14 illustrates filtering performances in term of SNR for GSM in the presence of two interferers respectively (+9dB and

+41dB) at the frequencies (80+200) kHz and (80+2x200) kHz.

The SNR value measured at the output of the filter is equal to 26,96 dB and satisfy largely the standard requirement (9 dB).

0 1 2 3

x 10⁴ -200

-150 -100 -50 0

SD output

Frequency (Khz) SNR=17.75 dB

db

0 1000 2000 3000

-150 -100 -50 0

First stage Output

db

0 500 1000 1500

-120 -100 -80 -60 -40 -20 0

Second stage output

db

Figure 13. Signal to Noise (SNR) at the input and the output of the two stages of the Decimation filter in case of UMTS standard

0 2000 4000 6000

-150 -100 -50 0

SD output

dB

0 50 100 150 200 250

-100 -80 -60 -40 -20 0

First stage output

db

0 20 40 60 80 100 120

-80 -60 -40 -20 0

Second stage output

db

Figure 14. Signal to Noise (SNR) at the input and the output of the two stages of the Decimation filter in case of GSM standard

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TABLE 1.FILTERS PROCESSORS IMPLEMENTATION RESULTS IN ASIC65-NM PROCESS

Table 1 summarizes hardware circuit’s evaluation results in terms of latency, area and power for both filters processors.

Obtained results show a power reduction of 14% with the new proposed filter processor compared with previous proposal.

The new design allows also the operating frequency increase but increase however the occupied area.

V. CONCLUSION

This paper has proposed a low-power decimation and channel selection filter optimized for both GSM and UMTS radios standards. The proposed filter is based on two stages and is suitable after sigma-delta converter. The first stage is composed of a modified CIC that increases the attenuation out of the band and allows frequency rate reduction downto only the double of the Nyquist frequency rate. Then, a compensation filter is cascaded to the modified CIC filter and compensates attenuation in the signal band.

The second stage, composed of a FIR filter reduces the operating frequency by 2 and allows the channel selection.

Good performances in term of SNR was achieved using proposed filter for both considered standards (14,65 dB for UMTS and 26,96 dB for GSM). Filter circuits implementation results in ASIC 65-nm process technology showed that proposed design allows a power reduction of 14% in comparison to previous multi-standard decimation filter circuits.

R^EFERENCES

[1] Seongdo Kim, Weon-Cheol Lee, Sungsoo Ahn, Seungwon Choi

“Design of CIC roll-off compensation filter in a W-CDMA digital IF receiver ”, Digital Signal Processing, Vol. 16, Issue 6, November 2006 [2] Adel Ghazel, Lirida Naviner, and Khaled Grati “On Design and

Implementation of a Decimation Filter for Multi_standards Wireless transceivers”. IEEE Transactions on wireless communications, Vol.1, N°4, pp. 558-562, October 2002.

[3] K. Grati, A. Ghazel, L. Naviner and F. Moatamri, “Design and implementation of cascade decimation filter for radio communications”, in Proceedings of IEEE International Conference on Electronics Circuits and Systems (ICECS’2001), Malta, Vol. III, pp. 1603 - 1606, September 2001.

[4] Y. Dumonteix, H. Aboushady, H. Mehrez, M. M. Louerat “Low power Comb Decimation Filter Using Polyphase Decomposition For Mono-Bit Analog-to-Digital Converters” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume 48, Issue 10, Oct 2001 Page(s):898 – 903

[5] K. Grati, A. Ghazel, L. Naviner “Design and Hardware Implementation of Digital Channel Selection Processor for Radio Receiver”; in Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology (ISSPIT.2004), Vol , Issue , pp. 152 – 156, December 2004.

[6] Lo. Presti “Efficient modified-Sinc Filters for Sigma-Delta A/D Converters” IEEE Transactions on Circuits and Systems-II Analog and Digital Signal Processing, Vol. 47, No.11, November 2000

[7] Y. Kwentus , Z. Jiang and N. Willson “Application of filter Sharpening to Cascaded Integrator-Comb Decimation Filters” IEEE Transactions on signal Processing, Vol. 45, No, 2, February 1997.

[8] G.J. Dolecek, J.D. Carmona, “A new cascaded modified CIC-cosine decimation filter” IEEE International Symposium on Circuits and Systems, 2005. ISCAS, pp: 3733 – 3736, May 2005

[9] Universal Mobile Telecommunication System (UMTS); UE Radio Transmission and Reception (FDD), 3GPP TS.101 version 5.2.0 Release 5. ETSI, 2002.

[10] Radio Transmission and Reception GSM 05.05. ETSI, 1996.

[11] N.Khouja, K.Grati, and A.Ghazel "Low Power FPGA-Based Implementation Of Decimating Filters For Multistandard Receiver"

IEEE International Conference on Design and Technology of Intergrated Systems in Nanoscale Era. pp. 10-14, September 2006.

[12] N.Khouja, K.Grati, B. Le Gal and A.Ghazel "Low Power Design of a Decimation filter in Multistandard Receiver" IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp. 1-5,March 2008.

Multistandard

filter Architecture Area

(um²) Latency (ns)

Dynamic Power (mW)

Static Power (mW)

Power Reduction

average Proposed

2-stages based filter processor

162236,87 4,37 1,05 0.192 14 % 3-stages based

filter processor 109466,76 7,01 1,22 0.135