Optimized Decimation Filter Architecture for 5th Order Converter in GSM/ UMTS/ Wi-max Radio
Receiver
Maha JEBALIA1, Chiheb REBAI1
1CIRTA’COM Research Lab
École Supérieure des Communications de Tunis (SUP’COM)
E-mail: [email protected]
Bertrand LE GAL2, Dominique DALLET2
2IMS Laboratory
ENSEIRB – University of Bordeaux I Bordeaux, France
E-mail: [email protected] [email protected]
Abstract—This paper presents an efficient design of a decimation filter for a continuous-time (CT) complex lowpass modulator in multi-standard receiver. The proposed architecture fulfills the requirements of three standards: Wi-max, UMTS and GSM. The optimization of the proposed decimation structure leads to two implementation architectures which are optimized in different ways: area (in terms of used resources) and power consumption for the required throughput. Experimental results illustrate the high-speed data throughput and low-power consumption features of the proposed designs.
Keywords—Multi-standard receiver, homodyne architecture, decimator filter, sigma-delta ADC, power consumption, clock- gating.
I. INTRODUCTION
The software radio aims at the implementation of flexible multi-standard Tx/Rx architectures which are controlled and may be programmed by software [1-4]. As a matter of fact, it has to operate in a multi-service environment without being restricted to a particular standard. It also seeks to guarantee re- configurability by implementing, in real time, radio interface and upper layers protocols [1]. With all these objectives in view, digitalizing the channels selection process seems to be mandatory. Nowadays, a lot of analog to digital conversion techniques are being used. Sigma-Delta () conversion is a worldwide technique that provides better channel selection.
Besides, it is well adapted to the technology used in VLSI circuits’ realizations. Nevertheless, Sigma-Delta modulation needs a post-conversion processing. Indeed, within the framework of Sigma-Delta A/D conversion, the decimation chain has to reduce any signal that may fold up to the effective channel by avoiding the quantization noise and the out-of-band signals. Then, it has to bring down the sampling frequency to the Nyquist rate.
In this paper, we try to propose a decimation chain for a multi-standard receiver to filter the channels of the standards Wi-max, UMTS and GSM. In the first section, we will reveal the proposed architecture. Then, we will present the different modifications and optimizations brought to it. Finally, we will
show the implementation results for some FPGAs and ASICs 90nm technology.
II. THEPROPOSEDDESIGNSTRATEGY
Heterodyne receivers are used because of their great sensitivity and selectivity characteristics. Meanwhile, they are too expensive to be implemented. That’s why the homodyne structure, illustrated in figure 1, is opted for [1, 2]. It is made up of fewer RF components, allowing a high degree of integration and low power consumption [5]. For these attractive characteristics, we have chosen the homodyne architecture for the multi-standard receiver. Besides, an Automatic Gain Control (AGC) has been taken into consideration during the design of the receiver. It adjusts the dynamic range of the received signal to the dynamic range of the converter. Thus, the use of the AGC prior to Analog to Digital conversion reduces the dynamic range of the converter [6].
( )
cos 2πf tLO
( )
sin 2πf tLO
Figure 1. Multi-standard homodyne architecture.
The specifications of the multi-standard receiver are summarized in the table 1 [7-9].
TABLE I. PHYSICAL SPECIFICATIONS OF THE STANDARDS WI-MAX, UMTS AND GSM.
Standards Wi-max UMTS GSM
Band (MHz) 5150-5350 2110-2170 925-960 Channel width (MHz) 20 5 0.2 Channel effective width
(MHz) 19.25 3.84 0.164
Modulation 64-QAM QPSK GMSK
DRADC(dB) 59.4 74 99
DRADC-AGC(dB) 31.52 39.51 46.98
Noise Figure (dB) 11.7 9.3 10 Oversampling ratio 8 16 32
These three standards were chosen because they have different channel bandwidths. In table 1, we notice that the dynamic range of the ADC (DRADC-AGC) is lower when an AGC is used. However, it’s greater (DRADC) if we get rid of the AGC. That’s why we opt for an architecture with an AGC.
Indeed, as it’s shown in table 2, this choice reduces the resolution N of the input signal.
TABLE 2. RESOLUTIONS OF THE ADC WITH AGC AND WITHOUT AGC FOR THE STANDARDS WI-MAX, UMTS AND GSM.
N (with AGC) N (without AGC)
Wi-max 6 10
UMTS 7 12
GSM 8 17
Once all the specifications of the receiver are defined, we focus on the design of the decimation chain to filter and select the channels of the standards Wi-max, UMTS and GSM. From the basis of the physical requirements of the three chosen standards, and in order to have a better filtering process, we try to implement an architecture that both removes the out-of-band signals and selects the desired channel.
A. Decimation scheme
The architecture shown in figure 2 is considered as a reference to the decimation process within the ADC [10]. It is a multistage structure employing a cascade of decimation filters. Thus, they can be designed with relaxed specifications.
Figure 2. Multistage decimation architecture for ADC.
The analog signal x(t), with a maximum frequency B, is sampled by the modulator to a high frequency fs (more than the Nyquist rate 2xB) as given in the equation 1 where OSR is the oversampling ratio.
f =OSR× 2×B
s (1)To find again the Nyquist rate, the output of the modulator will be down-sampled by a cascade of decimation filters. The decimation factor D, which is the product of the decimation factors Di, has to be equal to the oversampling ratio.
n i i=1
OSR=D= D
(2)Referring to table 1, we notice that the different OSRs are power of two. Consequently, the decimation factors (Di) are power of two.
m j i
j=1
D = 2
(3)In our design strategy, we opt for decimation factors Di equal to 2. In fact, these factors give an architecture that unifies the highest number of the different standards decimation filters.
The proposed architecture can therefore be considered as reconfigurable.
B. Design of the filtering stages
At each stage, the decimation filter has two essential roles [10]:
- It attenuates the noise that lies in the frequency bands [fs/Di – B, fs/Di] called folding bands, which is illustrated in figure 3. In the latter, fs is the sampling frequency, B is the bandwidth of the signal and Di is the decimation factor of the stage i.
- It divides the signal rate by the decimation factor Di.
Figure 3. Folding bands.
The required attenuation is given by the equation 4:
(4) where Psens_ref is the minimum signal power that can be detected by the receiver, SNRout is the signal to noise ratio and Nb is the noise power level in the frequency band [fs/ Di – B, fs/ Di].
The aim of this work is to propose an architecture that uses the minimum multiplication operations. To reach this goal, we have used comb filters for the first stages. Relying on the simulations done with the toolbox “simulink” of matlab, we noticed that the two last stages of each standard cannot be comb ones because they don’t reduce the noise level sufficiently. That’s why, we decided to use halfband filters for the two last stages. They exhibited good results and excellent out-of-band signals attenuation. The proposed cascade decimation chain is illustrated in figure 4.
Figure 4. Architecture 1 – Cascade decimation chain
As shown in figure 4, the proposed architecture has three comb filters which are multiplier-free and six symmetric halfband filters. Each standard has two halfband filters. Their orders are 10 and 86 for Wi-max, 6 and 22 for UMTS and 10
_
sens ref out b
Att = P − SNR − N
and 26 for GSM. Thus, the number of multiplications stands at 49. Hence, this architecture guarantees an efficient channel selection for the three standards Wimax, UMTS and GSM.
Besides, we notice that some filters are in common. This may reduce the area of the receiver.
C. Simulation results
To simulate and validate the proposed architecture illustrated, we have used the low-pass design of the 5th order
modulator presented in [11].
Figure 5. modulator output spectrum.
Figure 5 shows the modulator output spectrum for the GSM. We notice that the band of interest is close to the DC and the noise shaping rejects the quantization noise outside the band of interest. Thus, the signal to noise ratio (SNR) is grown by 10log (OSR).
III. LOWPOWERANDOPTIMIZEDAREAORIENTEDDESIGN
The proposed decimation architecture is a multi-standard one. It filters three standards which are Wi-max, UMTS and GSM. Nevertheless, it turns out that this architecture doesn’t take into consideration the standard to be treated. Indeed, all the filters are active when a standard is being processed even those which are not necessary for the channel selection of the standard at issue. For example, if a GSM signal is detected at the entry of the architecture, not only are the GSM chain’s filters active but even the Wi-max and UMTS ones do too.
Thereby, this architecture results in higher power consumption.
Therefore, to overcome this problem, we propose to add a power consumption controller that well-manages and supervises filters’ operations depending on the selected standard [12] as shown in figure 6.
The commands generated by the controller vary according to the needed standard. This controller has an input encoded into two bits where its value refers to the desired functioning mode. Depending on this value, the controller provides at its end a range of clocks. Only the clocks relating to the selected standard are active. Thus, only the filters relating to these active clocks are ready to begin the processing of the radio signal. The other filters are in an idle state. This technique is called “clock gating” [12].
MUX
Figure 6. Architecture 2 – Decimation chain with clock gating.
The multiplexer at the end of the architecture depends also on the selected decoding mode. Its role is to select the right processed radio signal taking into account the selected mode.
Besides, it is worth noting that the number of multiplications varies according to the selected mode. It is respectively equal to 27, 10 or 12 when a Wi-max, UMTS or GSM signal is being treated.
Furthermore, in order to have a multi-standard architecture with a unique cascade of filters for the three standards, we have realized an architecture that exploits the similarities between the halfband filters. It is illustrated in figure 7. This process produces a multimode design able to handle mutually different exclusive filters with efficient resource sharing. The design timing properties are not modified, glue logic as multiplexers are added to improve the hardware operators and registers sharing.
In fact, using this method we have unified the halfband filters of the three standards to keep only two filters instead of six. The first one has an order equal to 10 which is the highest order between the orders of the second, the third and the fourth filter of the standards Wi-max, UMTS and GSM, respectively.
As regards to the second halfband filter, it has an order equal to 86. We indeed took into account the most severe and the highest constraint between the last filters of the chains Wi-max, UMTS and GSM where the orders are respectively 86, 22 and 26.
Figure 7. Architecture 3 – Decimation chain with unified filters.
We notice that the halfband filters have a new input which corresponds to the selected decoding mode encoded into two bits. Depending on its value, the filter is able to download the coefficients which correspond to the chosen standard. The multiplexer is placed before the two halfband filters.
Depending on the mode, it selects the appropriate signal to finish its processing. This architecture allows to filter, in real
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time, one of the three standards (Wimax, UMTS or GSM) using a unique cascade of filters. Thus, we guarantee the re- configurability of the designed architecture. In addition, it may reduce the power consumption and the area of the receiver.
The number of multiplications varies according to the selected mode too, as it is the case for the second architecture.
It is respectively equal to 27, 10 or 12 when a Wi-max, UMTS or GSM signal is being treated.
IV. IMPLEMENTATIONRESULTS
Three implemented architectures are compared. This comparison deals with the study of the complexity of each architecture in terms of area, used resources and power consumption for a constant minimum throughput of 160MHz on the selected FPGA devices and the selected ASIC technology. We have also evaluated the maximum frequency that they can be reached on some FPGA devices. In this section, we will compare the “architecture 1” which corresponds to the first designed cascade decimation chain illustrated in the figure 4 to the second one with the “clock gating” and the third one with the unified filters. We will indeed verify whether the proposed optimizations improved the performances of the multi-standard receiver.
A. FPGA
The targeted technologies are Xilinx’s Spartan-3E and Virtex-4 FPGAs. These device families are some of the last generations in the Xilinx series. Built upon 90nm technology, the Virtex-4 family is well known from digital hardware designers as it is optimized for high-speed logic and digital signal processing (DSP) embedded processing. The values of the main characteristics of these implemented architectures on the Spartan-3E and Virtex-4 FPGAs (area, frequency) have been obtained using the Xilinx ISE 9.1.i logic synthesis tool chain. As regards power consumption estimation, it has been performed using XPower from Xilinx ISE too.
• Used FPGA resources
In this section, the number of used FPGA resources in terms of logic slices, Flip Flop and LUT is presented. The diagrams in figure 8 and figure 9 illustrate the synthesis results of the different architectures on Spartan-3E and Virtex-4 devices. The logical synthesis was realized under area optimization goal. The number of logic devices available in these targets is given in the table 3.
TABLE 3. NUMBER OF LOGIC DEVICES AVAILABLE IN SPARTAN-3E AND VIRTEX-4.
Slices Flip Flop LUT
Spartan-3E 8672 17344 17344
Virtex-4 5472 10944 10944
The implementation results show that the modifications made to the first and the second architectures lead to a new architecture with unified blocks improving the area performances for LUT (Look Up Table) and register components. In fact, the obtained gains in terms of consumed slices, Flip Flop and LUT are respectively 7.1%, 13% and 1.6% for the target Spartan 3E. This proves that the adoption of a unique cascade of filters to process all the signals for a multi- standard receiver decreases significantly the rate of used resources.
Figure 8. Used FPGA resources for a Spartan 3E.
The same experiments have been realized for a Virtex-4 device and the results (figure 9) have showed similar improvements: the slices, Flip Flop and LUT decreased respectively by 12.7%, 21.2% and 3.8%.
Figure 9. Used FPGA resources for a Virtex 4.
This decrease is due to the diminishing of the number of the halfband filters used for the signal processing.
• Maximum frequency
Now we are interested in the analysis of the maximum frequencies that can be reached by the third architecture for some FPGAs. In fact, we selected FPGA devices from Altera, Actel and Xilinx for their unlike properties. The Actel devices are low power. However, Altera and Xilinx devices consume more power than the Actel ones.
The results of the synthesis are showed in figure 10. We observe that the proposed architecture can reach high frequencies. We notice that the FPGAs of Actel offer the lowest rates. These FPGAs use indeed FLASH and ANTIFUSE technologies. Both of them showed low rates, whereas the FPGAs of Xilinx exploits the SRAM technology which gets higher frequencies.
As we can see from figure 10, the implemented architectures cannot work for the moment on Actel very low power FPGA. Indeed, the length of the critical path on this technology is too long for a real-time implementation. This leads to low functioning frequencies that don’t meet the requirements of the multi-standard receiver.
4377 6013 6755
4365 6002 6819
3754 3765 6472
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Slices Flip Flop LUT
Architecture 1 Architecture 2 Architecture 3
3990 5585 6096
3977 5619 6101
3291 3266 5681
0 1000 2000 3000 4000 5000 6000 7000
Slices FF LUT
Architecture 1 Architecture 2 Architecture 3 Target : Spartan-3E
Target : Virtex-4
Figure 10. Maximum frequencies reached by the proposed decimation chain.
• Power consumption
To estimate the power consumption of each architecture, we made use of the power analyser of Xilinx: XPower. Our targets are Spartan 3E and Virtex 4. The tests were realized at a clock frequency equals to 160 MHz and a switching rate of the bits at the entry equals to 80 %.
Figure 11. Power consumption for a Spartan 3E.
Figure 12. Power consumption for a Virtex 4.
We notice that the second and the third architectures derived from the first one achieve well performances for both of the targets. These diagrams underline the fact that the use of
a controller decreases the power consumption which came down from 21.81 mW to 14.56 mW for the target Spartan 3E and from 99.04 mW to 84.31 mW for the target Virtex 4. In fact, this decrease is due to the diminishing of the number of multiplications that drops off respectively, according to the selected standard Wi-max, UMTS or GSM, from 49 to 27, 10 or 12.
B. ASIC
Our objective behind this section is to validate our implementation architectures on non-reprogrammable devices to estimate their characteristics in architectural free technology.
We have selected a mature ASIC 90nm technology with 1.26 volt. The design tool used to transform the VHDL descriptions is “Design Compiler” from Mentor Graphics. This logical synthesis tool provides the area required for the implementation constraint by minimum clock frequency as square micrometers, the length of the critical path and an estimation of the power consumption of the design.
• Area
Figure 13. ASIC 90nm needed area.
As we may notice from figure 13, the third architecture with the unified filters has the smallest area; its size is 28%
smaller than the other designs. This is quite a normal observation as the first and the second architectures require bigger areas while they use 6 halfband filters instead of 2 as for 0
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FPGA
XILINX ALTERA ACTEL
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eX IGLOO
Proasic 3 Axcelerator
Target : Spartan-3E
Target : Virtex-4
the third architecture. Besides, it’s worth noting that the second architecture needs an area which is a little bit larger than the area of the first one because it involves the clock gating controller.
• Power consumption
Figure 14. Power consumption for ASIC 90nm.
Once again, the third architecture showed better performances. As a matter of fact, the first architecture consumes 41.69mW whereas the second and the third ones consume respectively 33.83mW and 16.05mW. The optimized merged filter design provides a 60% power consumption saving. These results come as no surprise, for the two last architectures involve a power consumption controller that allows reducing the number of multiplications and therefore the power consumption. Moreover, the unification of the filters has a heavy impact on the reduction of the static power consumption because in such a case, we need less decimators within the controller and less filters reducing the circuit’s area.
V. CONCLUSION
The work presented in this paper has focused on the design and the implementation of a decimation filter for a multistandard receiver. We have pointed at having the appropriate cascade of filters for the selection of digital channels Wi-max, UMTS and GSM. We have chosen homodyne architecture with AGC. The synthesis process of the proposed architectures on FPGAs and ASICs showed low cost real time implementations. We have provided various implementation architectures for the deicmation filter chain targetting low area and power cost objectives. We could improve the performances of the proposed architecture in terms of power consumption and area for both FPGAs and ASICs 90nm targets. The improvements were achieved, on the one hand, by introducing a controller that supervises the functioning of the filters and, on the other hand, by unifying the filtering blocks.
In future works, we will see to it that a more accurate characterization based on implementation optimization techniques will be fulfilled in order for us to reach better performances and results in terms of power consumption and area reduction under real time constraint. We will introduce the usage of CSD Canonical Signed-Digit coefficients for the halfband filters as they will reduce the global power consumption of the design and introduce the maximum frequency increase.
VI. REFERENCES
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[4] Walter Tuttlebee, « The Impact of Software Radio », CEC Software Radio Workshop, Brussels, May 1997.
[5] Kaïs Mabrouk, Bernard Huyart, Guillaume Neveux, « 3-D Aspect in the Five-Port Technique for Zero-IF Receivers and a New Blind Calibration Method », IEEE Transactions on Microwave Theory and Technique, Vol. 56, No. 6, June 2008.
[6] Intersil Americas Inc., « Automatic Gain Control (AGC) in ISL 5416 3G QPDC », May 2002.
[7] IEEE Standard for local and metropolitan area networks, « Part 16: Air Interface for Fixed Broadband Wireless Access Systems », IEEE Std 802.16 – 2004 (Revision of IEEE Std 802.16 – 2001.
[8] ETSI, « Universal Mobile Telecommunications System (UMTS), User Equipment (UE) radio transmission and reception (FDD) », 3GPP TS 25.101, version 7.9.0, release 7, 2007.
[9] ETSI, « Digital cellular telecommunications system (Phase 2+), Radio transmission and reception »; GSM 05.05 version 8.5.1, release 1999, 2000.
[10] Massimiliano Laddomada, « Generelized Comb Decimation Filters for A/D Converters: Analysis and Design », IEEE Transactions on Circuits and Systems, vol. 54, no.5, May 2007.
[11] Nejmeddine Jouida, Chiheb Rebai, Adel Ghazel, Dominique Dallet,
« Comparative Study between Continuous-Time Real and Quadrature Bandpass Delta Sigma Modulator for Multistandard Radio Receiver », Instrumentation and Measurement Technology Conference – IMTC 2007, Warsaw, Poland, May 1-3, 2007.
[12] Nadia Khouja, Khaled Grati, Adel Ghazel, « Low Power FPGA-Based Implementation of Decimating Filters for Milti-standard Receiver », IEEE Design and Test of Integarted Systems in Nanoscale Technology, pp. 10-14, September 2006.
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