Advanced Power MOSFET IRFR/U120A

Avalanche Rugged Technology Rugged Gate Oxide Technology Lower Input Capacitance

Improved Gate Charge Extended Safe Operating Area

Lower Leakage Current : 10 A (Max.) @ V_DS = 100V Lower R_DS(ON) : 0.155 (Typ.)

Thermal Resistance

Junction-to-Case Junction-to-Ambient Junction-to-Ambient R _JC

R _JA R _JA

/W

Characteristic Max. Units

Symbol Typ.

FEATURES

*

* When mounted on the minimum pad size recommended (PCB Mount).

Absolute Maximum Ratings

Drain-to-Source Voltage

Continuous Drain Current (T_C=25 ) Continuous Drain Current (T_C=100 ) Drain Current-Pulsed Gate-to-Source Voltage

Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (T_A=25 ) Total Power Dissipation (T_C=25 ) Linear Derating Factor

Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8” from case for 5-seconds

Characteristic Value Units

Symbol

I_DM V_GS E_AS I_AR E_AR dv/dt

P_D I_D

T_J , T_STG

T_L

A V mJ

A mJ V/ns

W W W/

A

V_DSS V

*

D-PAK

1. Gate 2. Drain 3. Source

1

2

3

I-PAK

1 23

µ Ω

O

O

O

ΟC

ΟC

O

O

θ

ΟC

ΟC

ΟC

ΟC

ΟC

θ θ

BV

= 100 V R

= 0.2 I

= 8.4 A

100 8.4 5.3 34 141

8.4 3.2 6.5 2.5 32 0.26 - 55 to +150

300

3.9 50 110 --

-- --

Ω

20 +_

©1999 Fairchild Semiconductor Corporation

Rev. B

(TC

Electrical Characteristics

Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff.

Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse

Characteristic

Symbol Min. Typ. Max. Units Test Condition

Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance

Output Capacitance

Reverse Transfer Capacitance Turn-On Delay Time

Rise Time

Turn-Off Delay Time Fall Time

Total Gate Charge Gate-Source Charge Gate-Drain(“Miller”) Charge g_fs

C_iss C_oss C_rss t_d(on) t_r t_d(off)

t_f Q_g Q_gs Q_gd BV_DSS

BV/ T_J V_GS(th)

R_DS(on) I_GSS

I_DSS

V V/

V nA

A

pF

ns

nC --

-- -- -- -- -- -- -- -- -- -- --

--

V_GS=0V,I_D=250 A I_D=250 A See Fig 7 V_DS=5V,I_D=250 A V_GS=20V

V_GS=-20V V_DS=100V V_DS=80V,T_C=125 V_GS=10V,I_D=4.2A V_DS=40V,I_D=4.2A

V_DD=50V,I_D=9.2A, R_G=18

See Fig 13 V_DS=80V,V_GS=10V, I_D=9.2A

See Fig 6 & Fig 12 Drain-to-Source Leakage Current

V_GS=0V,V_DS=25V,f =1MHz See Fig 5

Source-Drain Diode Ratings and Characteristics

Continuous Source Current Pulsed-Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge I_S

I_SM V_SD t_rr Q_rr

Characteristic

Symbol Min. Typ. Max. Units Test Condition

-- -- -- -- --

A V ns C

Integral reverse pn-diode in the MOSFET

T_J=25 ,I_S=8.4A,V_GS=0V T_J=25 ,I_F=9.2A di_F/dt=100A/ s

∆ ∆

C

Ω Ω

µ

O

O

ΟC µ

µ

ΟC

O

O

O

O

O

Ω

ΟC

µ µ

ΟC µ

O

O

100 -- 2.0

-- -- -- --

-- 0.12

-- -- -- -- --

95 38 14 14 36 28 16 2.7 7.8

-- -- 4.0 100 -100

10 100 0.2 -- 480 110 45 40 40 90 70 22 -- -- 6.29

370

-- -- -- 98 0.34

8.4 34 1.5 -- --

Notes ;

Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature L=3mH, I_AS=8.4A, V_DD=25V, R_G=27 , Starting T_J =25

I_SD 9.2A, di/dt 300A/ s, V_DD BV_DSS , Starting T_J =25 Pulse Test : Pulse Width = 250 s, Duty Cycle 2%

Essentially Independent of Operating Temperature

<_ <_

<_

<

_

O

O

O

O

O

Ω ^oC

oC µ

µ

Fig 1. Output Characteristics Fig 2. Transfer Characteristics

Fig 6. Gate Charge vs. Gate-Source Voltage Fig 5. Capacitance vs. Drain-Source Voltage

Fig 4. Source-Drain Diode Forward Voltage Fig 3. On-Resistance vs. Drain Current

10^-1 10⁰ 10¹

10⁰ 10¹

@ Notes : 1. 250 µs Pulse Test 2. T_C = 25 ^oC V_GS

Top : 1 5 V 1 0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V

ID , Drain Current [A]

V_DS , Drain-Source Voltage [V]

2 4 6 8 10

10^-1 10⁰ 10¹

25 ^oC 150 ^oC

- 55 ^oC

@ Notes : 1. V_GS = 0 V 2. V_DS = 40 V 3. 250 µs Pulse Test ID , Drain Current [A]

V_GS , Gate-Source Voltage [V]

0 10 20 30 40

0.0 0.1 0.2 0.3 0.4

@ Note : T_J = 25 ^oC V_GS = 20 V V_GS = 10 V

RDS(on) , [Ω] Drain-Source On-Resistance

I_D , Drain Current [A]

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

10^-1 10⁰ 10¹

150 ^oC 25 ^oC

@ Notes : 1. V_GS = 0 V 2. 250 _µs Pulse Test IDR , Reverse Drain Current [A]

V_SD , Source-Drain Voltage [V]

10⁰ 10¹

0 200 400 600

C_iss= C_gs+ C_gd ( C_ds= shorted ) C_oss= C_ds+ C_gd

C_rss= C_gd

@ Notes : 1. V_GS = 0 V 2. f = 1 MHz C _rss

C _oss C _iss

Capacitance [pF]

V_DS , Drain-Source Voltage [V]

0 5 10 15 20

0 5 10

V_DS = 80 V V_DS = 50 V

V_DS = 20 V

@ Notes : I_D = 9.2 A VGS , Gate-Source Voltage [V]

Q_G , Total Gate Charge [nC]

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature

Fig 11. Thermal Response

Fig 10. Max. Drain Current vs. Case Temperature Fig 9. Max. Safe Operating Area

P_DM

t₁ t₂

-75 -50 -25 0 25 50 75 100 125 150 175

0.8 0.9 1.0 1.1 1.2

@ Notes : 1. V_GS = 0 V 2. I_D = 250 µA BVDSS , (Normalized) Drain-Source Breakdown Voltage

T_J , Junction Temperature [^oC]

-75 -50 -25 0 25 50 75 100 125 150 175

0.0 0.5 1.0 1.5 2.0 2.5 3.0

@ Notes : 1. V_GS = 10 V 2. I_D = 4.6 A RDS(on) , (Normalized) Drain-Source On-Resistance

T_J , Junction Temperature [^oC]

10⁰ 10¹ 10²

10^-1 10⁰ 10¹ 10²

10 µs

DC

100 µs 1 ms 10 ms

@ Notes : 1. T_C = 25 ^oC 2. T_J = 150 ^oC 3. Single Pulse Operation in This Area is Limited by R _DS(on)

ID , Drain Current [A]

VDS , Drain-Source Voltage [V]

25 50 75 100 125 150

0 2 4 6 8 10

ID , Drain Current [A]

T_c , Case Temperature [^oC]

10^{- 5} 10^{- 4} 10^{- 3} 10^{- 2} 10^{- 1} 10⁰ 10¹

10^{- 1} 10⁰

single pulse 0.2

0.1

0.01 0.02 0.05 D=0.5

@ Notes : 1. Z

θJ C(t)=3.9 ^oC/W Max.

2. Duty Factor, D=t₁/t₂ 3. T_{J M}-T_C=P_{D M}*Z_{θJ C}(t)

Z θJC(t) , Thermal Response

t1 , Square Wave Pulse Duration [sec]

Fig 12. Gate Charge Test Circuit & Waveform

Fig 13. Resistive Switching Test Circuit & Waveforms

Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms

E_AS = ---- L_L I_AS² 2

1 --- BV_DSS -- V_DD

BV_DSS V_in

V_out

10%

90%

t_d(on) t_r

t _on t _off

t_d(off) t_f

Charge V_GS

10V

Q_g

Q_gs Q_gd

Vary t_p to obtain required peak I_D

10V

V_DD C

L_L V_DS

I_D

R_G

t _p

DUT

BV_DSS

t _p

V_DD I_AS

V_DS (t) I_D (t)

Time V_DD

( 0.5 rated V_DS )

10V

V_out V_in

R_L

DUT R_G

3mA

V_GS

Current Sampling (I_G) Resistor

Current Sampling (I_D) Resistor

DUT

V_DS

300nF 50K

200nF 12V

Same Type as DUT

“ Current Regulator ”

R₁ R₂

Ω

Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

V_DS +

--

L I _S

Driver V_GS

R_G ^{Same Type}

as DUT

V_GS • dv/dt controlled by “R_G”

• I_S controlled by Duty Factor “D”

V_DD

10V V_GS

( Driver )

I _S ( DUT )

V_DS ( DUT )

V_DD

Body Diode Forward Voltage Drop

V_f

I_FM , Body Diode Forward Current

Body Diode Reverse Current I_RM

Body Diode Recovery dv/dt di/dt D = Gate Pulse Width

Gate Pulse Period ---

ACEx™

CoolFET™

CROSSVOLT™

E

CMOS

FACT™

FACT Quiet Series™

FAST

FASTr™

GTO™

HiSeC™

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench™

QS™

Quiet Series™

SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Formative or In Design

First Production

Full Production

Not In Production DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

UHC™

VCX™