HAL Id: hal-00627374
https://hal-supelec.archives-ouvertes.fr/hal-00627374
Submitted on 28 Sep 2011
HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.
L’archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d’enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.
A High-Level Modeling Framework for the Design and
Optimization of Complex CT Functions
Philippe Benabes, Catalin Tugui
To cite this version:
Philippe Benabes, Catalin Tugui. A High-Level Modeling Framework for the Design and Optimization
of Complex CT Functions. 9th IEEE International NEWCAS Conference (NEWCAS’11), Jun 2011,
Bordeaux, France. pp.61-64. �hal-00627374�
A high-level modeling framework for the design and
optimization of complex CT functions
Philippe BENABES, Member, IEEE, Catalin-Adrian TUGUI
Department of Signal Processing and Electronic SystemsSUPELEC
91192 GIF-SUR-YVETTE, FRANCE philippe.benabes@supelec.fr Abstract— Novel CMOS technologies are rapidly migrating
towards the nanometer world. The design and optimization of complex analog circuits implying these processes is impracticable when using only transistor-level electronic design automation (EDA) tools. Efficient design methodologies including behavioral modeling are inevitable, but the high-level models should incorporate accurate circuit characteristics and technological limitations. One solution consists in using a refined top-down design process where the macro-models are extracted from the analog block elements (e.g. amplifiers, filters) implemented on specific technologies. These fast-simulating models can be used for the high-level simulation and optimization of the entire system. We propose in this paper a complete design methodology implying the above elements and the corresponding application framework based on the interface between MATLAB and CADENCE software tools. SIMULINK and VHDL-AMS are used for the high-level system modeling. A continuous-time (CT) Sigma-Delta modulator application is presented.
I. INTRODUCTION
The evolution of complex analog systems towards nanometer-scale CMOS processes along with the increasing development of systems-on-a-chip (SoCs) and systems-in-a- package (SiPs) including mixed analog and digital circuitry imposes the existence of efficient analog design methodologies which can balance the high-performance digital implementation and verification techniques. Top-down design paradigms are preferred in order to handle together the digital and the analog parts and to ensure performance optimization directly at system level [1].
In this context, the design techniques implying only transistor-level Spice-like simulations of large analog functions such as continuous-time (CT) Sigma-Delta modulators [2] are prohibitive. Automatic optimization possibilities for a whole system are very limited due to the huge computation times required by each optimization step.
Analog behavioral modeling should be considered in order to reduce the overall system conception and verification effort.
Several high-level modeling approaches have been proposed [3] [4] [5], still the largest problem remains the small number of systematic methods to create good analog behavior
which can be exploited at system level and the lack of efficient tools to automate the macro-model extraction process.
One solution consists in using a refined top-down analog design methodology where the macro-models of amplification functions (Op-amps, Transimpedances, Transconductances) are extracted from transistor-level implementations of circuit blocks, including analog imperfections and technology constraints. Many topics have to be characterized such as the gains, the DC and AC transfer functions, the input and output impedances (real or complex), and the nonlinearities. All these characterizations require simulations which can become very long if they are not automated. The simulations tools do not have very flexible automation possibilities. This is why we propose an application framework MATLAB/SIMULINK – CADENCE – VHDL-AMS where the models extraction process is automated and system exploration can be performed easily at any architectural level.
Section II covers the novel aspects of the design methodology and the modeling approach. In the third section we present the interface between MATLAB and CADENCE and the overall techniques used to get the circuits characteristics. In the fourth section we propose a conception example for a fast current-to-voltage converter used in a Sigma-Delta CT modulator. System level implementation results are also presented. Section V covers the conclusions of this work.
II. DESIGN METHODOLOGY AND MODELING TECHNIQUES
Top-down design methodologies are used for complex analog and mixed systems, allowing fast system level simulations and performance evaluation. Still, the system level results, even when optimized, are rapidly degrading at transistor level due to technological dispersion and analog imperfections. In order to overcome the inconvenient, we propose a refined design methodology (Figure 1). Starting from a theoretically validated system architecture, the circuit design and the specific technology implementation are done.
Then a semi-automatic optimization process is performed on each transistor-level cell using the MATLAB-CADENCE application framework. Using the optimal performance solution (in terms of desired gains, supply, impedances, nonlinear behavior, etc.) a robust component macro-model is
extracted. It includes circuit topology characteristics and real analog functions. Using the macro-models, a high-level system modeling and optimization can be performed, resulting in architecture, circuits and transistor-level adjustments.
Figure 1: Refined top-down design methodology An effective modeling technique is implemented. The fitting approach is combined with a constructive approach, where the unipolar and common-mode/differential behaviors are included. Three levels of models abstraction are presented as example in Figure 2. Including the parasitic effects and the imperfections at system level (Model 2), it is possible to directly optimize the system performance by taking into account the real components behavior.
Figure 2: Abstraction levels for macro-models III. ANALOG FUNCTIONS CHARACTERISTICS EXTRACTION
A. Starting analog simulations from MATLAB
In our case, MATLAB is used as a master tool and the analog simulator as a slave tool. The CADENCE integrated SPECTRE simulator was used. MATLAB functions were implemented in order to automatically create batch command files that will be read by the Open Command Environment for Analysis (OCEAN) interface tool. OCEAN starts all required transistor-level simulations. Then MATLAB can read the simulations results using the compiled functions delivered by CADENCE via their Virtuoso Multi-Mode Simulation (MMSIM) Spectre/RF toolbox.
Analog simulations can easily be started in a batch mode using the OCEAN tool. OCEAN is a text-based process that can be run from a UNIX shell. It can be used with any simulator integrated into the Virtuoso Analog Design Environment. OCEAN works in an existing simulation directory. So the first step is to create the schematic which has
to be simulated and optimized. All the sizes of components should be parameterized with specific names which will be used as MATLAB variables in the framework. When the schematic is finished, the next step is to start the “analog environment” and create the simulation netlist. Once this step is completed, the Virtuoso environment can be closed and our MATLAB-CADENCE framework started.
B. Performed analyses and macro-models extraction
This tool is essentially dedicated to the optimization and macro-model extraction of CT functions such as amplifiers.
The input and output quantities can be either currents or voltages. The interfaces can be unipolar or differential. In the rest of this presentation, we will consider a unipolar example with the input as a current and the output as a voltage, but all other cases can be treated. Four kinds of simulations can be performed: DC analysis, DC parametric analysis, AC analysis and transient analysis. All the analyses results are available as MATLAB variables, and can be synthetically grouped in two windows as presented in Figure 3 and Figure 4.
The MATLAB-CADENCE framework will completely automate the analog simulation process and extract s-models of the transfer functions, combine offsets, gains, nonlinearities and other user-defined criteria (e.g.
normalization of the frequency band) and will synthesize the macro-model of the analog circuit as a SIMULINK block or VHDL-AMS behavioral architecture. A detailed description of the model extraction algorithms can be found in [6].
A more complex approach is used for the differential designs, where the common-mode/differential and normal input-output characteristics are studied.
Figure 3: Macro-model DC parameters extraction
System level
Component circuit level
Transistor level
Layout level
System architecture
Circuit design
Specific tech.
implementation
Layout generation
Semi-automatic cell optimization Components robust
macro-models High level system modeling
High level optimization
Post-layout / Prototype / Fabrication
Rising system verification time
f1H f2H f3H
IN OUT
Uni→Diff
(Funct 1) Diff→Uni
(Funct 3)
IN OUT
System Model
Diff→Diff (Funct 2) DIFF I/F High-level
Model 1
Uni→Diff
IN OUT
Uni→Com (1)
Diff→Diff Diff→Com
(2)
Diff→Uni Parasitic path (3)
High-level Model 2
-0.1 -0.05 0 0.05 0.1
2.7 2.8 2.9 3 3.1 3.2
input current (mA) output voltage (V)
-0.1 -0.05 0 0.05 0.1
2.354 2.355 2.356 2.357 2.358 2.359
input current (mA) input voltage (V)
-0.1
0 0.1
-0.2 0 0.2 2.8 2.9 3 3.1
input current (mA) output voltage (V)
output current (mA) -0.1 0
0.1 -0.2
0 0.2 2.355 2.356 2.357 2.358
input current (mA) input voltage (V)
output current (mA)
-1 0 1
x 10-4 2.8
3 3.2 3.4 3.6 3.8
input value
intermediary voltages
-0.1 -0.05 0 0.05 0.1
8.8 8.9 9 9.1
input current (mA) Supply current (mA) direct gain : 1945.6906
Z out : 3.4843 V out dc : 2.9528 V Z in : 13.8628 inverse gain : -3.3852 V in dc : 2.3562 V
NLX : -0.00014296 -1.7019e-05 NLY : -1.0021e-05 -6.6256e-08 IMOD : -2.9185e-05
NLTOT : 2.2181e-05
NLX : -0.00013725 -1.6219e-05 NLY : -9.8739e-06 -6.5885e-08 IMOD : -2.8936e-05
NLTOT : 2.1349e-05
Figure 4: Macro-model AC/transient parameters extraction IV. MACRO-MODELING A SIGMA-DELTA MODULATOR
The methodology will be applied to the design of the first stage of a sixth order CT Sigma-Delta modulator. The architecture of this modulator was published in [7]. As shown in Figure 5, its filter consists of three transconductance amplifiers (Gm1-Gm3), four transimpedance amplifiers (Z1 to Z4), three multi-output current mirrors (M1 to M3) and Lamb Wave Resonator (LWR) filters.
Z1 M1
LWR
C Z2 M2 Z3 M3
Gm1 Gm2 Gm3
DAC1 DAC2
LWR
LWR C LWR
LWR C LWR
Z4 ADC
Figure 5: Sixth order Sigma-Delta modulator
The differential transimpedance amplifiers are composed with two single-ended transimpedance amplifiers. The schematic of each amplifier is given in Figure 6.
Figure 6: Transimpedance amplifier with real sources
Transistors T1, T4 and resistor R1 act as a current- controlled voltage source. Its gain is equal to R1. Transistors T2 and T3 are constant voltage sources. They help increase the base voltage of T1 and so the input offset voltage.
The current sources initial values can easily be found by simple DC considerations. Then a semi-automatic optimization process is performed using the MATLAB tool.
The schematic is optimized with ideal current sources and afterwards the real sources are added and optimized also. The tool launches a parametric analysis on each transistor size and current source value. For the bipolar transistors the only parameter is their area. In the case of MOS transistors, optimal parameters would be their length (L) and geometric ratio (W/L). One performance parametric analysis result is shown as an example in Figure 7, but the tool gives one window per analyzed parameter. The total simulation time might take minutes or hours depending on the number of varied parameters, the schematic complexity, and the machine speed, but all is automatic and no human intervention is required.
Figure 7 : Performance macro-parametric analysis Once all the macro-parametric analyses were performed, the designer will deduce which parameter influences each performance characteristics and all components values can be usually found after 3 runs.
At the end of the optimization, one can extract the macro- model of the amplifier as a SIMULINK block (Figure 8) or VHDL-AMS module. The macro-model includes the direct and reverse transfer functions, the input and output
Rs in : 13.8628 R in : 1524.8932 L in : 1.3407e-07 C in : 1.0383e-13 Rs out : 3.4843 R out : 38.4561 L out : 3.4054e-09 C out : 6.1868e-14 Zout at f0: 3.9836
Zin at f0: 104.7247 FC transfer : 14.4544 Delay at f0 : -0.25617nS
100
10-2 102 104
105
101 103
10-1 10-3
red=measure blue=model
freq Transfer function
100
10-2 102 101044
100 102 104
red=measure blue=model s magenta=model RLC
freq Z in
100
10-2 102 101044
100 101 102
red=measure blue=model s magenta=model RLC
freq Z out
0 0.5 1 1.5 2
x 10-8 2.6
2.7 2.8 2.9 3 3.1 3.2
time
out
Transient response
FC
1.5 2 2.5 3
x 10-4 2.356
2.358 2.36
I1 input offset
1.5 2 2.5 3
x 10-4 2.6
2.8 3 3.2
I1 output offset
1.5 2 2.5 3
x 10-4 1945
1946 1947 1948
I1 direct gain
1.5 2 2.5 3
x 10-4 -3.4
-3.35 -3.3 -3.25
I1 inverse gain & common mode
1.5 2 2.5 3
x 10-4 11
12 13 14
I1 input impedance
1.5 2 2.5 3
x 10-4 3.3
3.4 3.5 3.6
I1 output impedance
1.5 2 2.5 3
x 10-4 -15
-10 -5 0 5x 10-5
I1 input non linearity
1.5 2 2.5 3
x 10-4 -15
-10 -5 0 5x 10-5
I1 output non linearity
10-5 100 105
10-5 100 105
reduced frequency transfer function
10-5 100 105
100 105
reduced frequency Zin
10-5 100 105
100 101 102
reduced frequency Zout
1.5 2 2.5 3
x 10-4 98
100 102 104 106
I1 input impedance at f0
1.5 2 2.5 3
x 10-4 3.7
3.8 3.9 4
I1 output impedance at f0
1.5 2 2.5 3
x 10-4 -0.258
-0.256 -0.254 -0.252
I1 delay
0 1 2
x 10-8 2
2.5 3 3.5
I1 transient
impedances, computed as minimum-order stable s-functions and all offsets. The nonlinear characteristics can be included on each output port of the model (in our case Vout and Vin) by using the computed nonlinearity coefficients cij(r):
2 02 11
2 20
0 in out out in in out out
out
out V gI Z I c I c I I c I
V = + + + + + (1)
2 02 11
2 20
0 r in
in out r out r in in out r in
in V g I Z I c I c I I c I
V = + + + + + (2)
Figure 8 : Linear macro-model of the amplifier The VHDL-AMS behavioral architecture of the amplifier is generated accordingly:
• Electrical terminals are used for the input and output ports:
PORT (terminal Iin, Vout : electrical);
• S-functions are exported as vectors of real coefficients, e.g.
CONSTANT Num_TF_dir1 : REAL_VECTOR :=
(23.141660, 13486.524207, -14874410.434859);
CONSTANT Den_TF_dir1 : REAL_VECTOR :=
(1.000000, 177.429273, 7636.460716);
• Direct and reverse voltages and currents are defined as:
QUANTITY v_d ACROSS i_d THROUGH ground to Iin;
QUANTITY v_i ACROSS i_i THROUGH Vout to ground;
• The model behavior will use the Laplace formalism to find output signals starting from inputs and offsets, e.g.
v_d == deltaIin'LTF(Num_TF_dir1, Den_TF_dir1) + deltaIout'LTF(Num_Zout1, Den_Zout1) + OffOut1;
v_i == deltaIin'LTF(Num_Zin1, Den_Zin1) +
deltaIout'LTF(Num_TF_inv1, Den_TF_inv1) + OffIn2;
When all amplifiers and LWR filters have been designed and extracted using the proposed methodology, the Sigma- Delta modulator can be implemented as a whole system in SIMULINK or VHDL-AMS based process. Each analog block in Figure 5 was replaced by a macro-model.
High-level implementations were conducted for second- order and third-order components models. MATLAB- SIMULINK and Dolphin Integration SMASH (for VHDL- AMS) were used as simulators. System level performance characteristics were evaluated in order to validate the methodology. As an example, the direct transfer function of the Sigma-Delta filter is compared in the case of the transistor- level implementation and the high-level one (Figure 9). The simulations results are coherent and more accurate when the maximum models orders increase. But orders>6 will not justify the plus-performance, while rising the system complexity. The macro-model simulation takes a few minutes while the transistor-level one requires hours.
Figure 9 : Whole Sigma-Delta filter transfer function V. CONCLUSIONS
A refined top-down design methodology for complex CT functions and the corresponding application framework employing the MATLAB/SIMULINK, CADENCE and VHDL-AMS tools were proposed. They can be used early in the conception stages in order to optimize the components sizes and for the extraction of effective components macro- models, in order to make a high-level implementation of the full system and accelerate simulations. The application can start automatically all kinds of analog simulations (DC, AC, parametric, transient), assure a semi-automatic optimization for the cells at transistor level and automate the macro-model extraction process. The proposed application framework and additional conception examples are available via the MathWorks website at [8].
REFERENCES
[1] Gielen, G.G.E., « Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies », Asia and South Pacific Design Automation Conference, 2007 (ASP-DAC '07).
[2] Schreier, R.; Zhang, B., « Delta-Sigma modulators employing continuous-time circuitry », IEEE Trans. Circuit & Systems-I:
Fundamental Theory and Applications, vol. 43, pp. 324-332, April 1996.
[3] Maxim, A.; Andreu, D.; Cousineau, M.; Boucher, J., « A novel SPICE behavioral macromodel of operational amplifiers including a high accuracy description of frequency characteristics », ISCAS '99, pp. 278- 281, Jul 1999.
[4] Phillips, J.; Afonso, J.; Oliveira, A.; Silveira, L.M., « Analog macromodeling using kernel methods », IEEE/ACM International Conference on Computer Aided Design (ICCAD 2003).
[5] Hui Li Mansour, M.; Maturi, S.; Wang, L.-C., « A new Sampling Method for Analog Behavioral Modeling », IEEE International Symposium on Circuits and Systems (ISCAS 2010).
[6] Benabes, P.; Tugui, C.-A., « Effective Modeling of CT Functions for Fast Simulations Using MATLAB-Simulink and VHDL-AMS Applied to Sigma-Delta Architectures », IEEE International Symposium on Circuits and Systems (ISCAS 2011), accepted.
[7] Javidan, M.; Benabes, P., « Band-Pass Continuous-Time Delta-Sigma Modulators Employing LWR Resonators », IEEE International Conference on Electronics, Circuits, and Systems (ICECS’08).
[8] http://www.mathworks.com/matlabcentral/fileexchange/26525
Vin 2
Vout 1
ZoutNum_Zout1(s) Den_Zout1(s) Num_Zin1(s) Zin
Den_Zin1(s)
TFR Num_TF_inv1(s) Den_TF_inv1(s) TFD Num_TF_dir1(s) Den_TF_dir1(s)
OffOut2 OffOut2 OffOut1 OffOut1
OffIn2 OffIn2 OffIn1 OffIn1
Add3
Add2
Add1 Add
Iout 2 Iin
1
106 107 108 109 1010
1e-8 1e-4 1e0 1e4
Magnitude [log]
106 107 108 109 1010
-30 -25 -20 -15 -10 -5 0 5
freq [Hz]
Phase [rad]
analog function components macro-models ord2 components macro-models ord3
