November2012 MatthieuMoy ModelingofTimeinDiscrete-EventSimulationforSystems-on-Chips
102
0
0
Texte intégral
(2) SoCs and TLM. jTLM. sc-during. Conclusion. Modern Systems-on-a-Chip. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 2 / 42 >.
(3) SoCs and TLM. jTLM. sc-during. Conclusion. Modern Systems-on-a-Chip Software. Hardware. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 2 / 42 >.
(4) SoCs and TLM. jTLM. sc-during. Conclusion. Hardware/Software Design Flow Traditional Design-Flow Specification, Algorithm RTL Design. Time. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 3 / 42 >.
(5) SoCs and TLM. jTLM. sc-during. Conclusion. Hardware/Software Design Flow Traditional Design-Flow Specification, Algorithm RTL Design. Synthesis. Time. cost > 1,000,000 $ ! Factory Software Development Integration. Validation. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 3 / 42 >.
(6) SoCs and TLM. jTLM. sc-during. Conclusion. Time. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 3 / 42 >.
(7) SoCs and TLM. jTLM. sc-during. Conclusion. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design Software Development. Time. Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 3 / 42 >.
(8) SoCs and TLM. jTLM. sc-during. Conclusion. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. TLM Model. Software Development. Time. Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 3 / 42 >.
(9) SoCs and TLM. jTLM. sc-during. Conclusion. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. TLM Model. Software Development Synthesis. Synthesis. Factory. Factory. Time. Integration. Software Development. Validation. Integration. Validation. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 3 / 42 >.
(10) SoCs and TLM. jTLM. sc-during. Conclusion. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. TLM Model. Software Development Synthesis. Synthesis. Factory. Factory. Time. Integration. Software Development. Validation. gain. Integration. Validation. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 3 / 42 >.
(11) SoCs and TLM. jTLM. sc-during. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. jTLM: Experiments Without SystemC. 3. Back to SystemC: sc-during. 4. Conclusion. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 4 / 42 >.
(12) SoCs and TLM. jTLM. sc-during. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. jTLM: Experiments Without SystemC. 3. Back to SystemC: sc-during. 4. Conclusion. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 5 / 42 >.
(13) SoCs and TLM. jTLM. sc-during. Conclusion. The Transaction Level Model: Principles and Objectives A high level of abstraction, that appears early in the design-flow. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 6 / 42 >.
(14) SoCs and TLM. jTLM. sc-during. Conclusion. The Transaction Level Model: Principles and Objectives A high level of abstraction, that appears early in the design-flow A virtual prototype of the system, to enable I I I I. Early software development Integration of components Architecture exploration Reference model for validation. Abstract implementation details from RTL I I. Fast simulation (' 1000x faster than RTL) Lightweight modeling effort (' 10x less than RTL). Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 6 / 42 >.
(15) SoCs and TLM. jTLM. sc-during. Conclusion. Content of a TLM Model A first definition. Model what is needed for Software Execution: I I I. Processors Address-map Concurrency. ... and only that. I I I I I. No micro-architecture No bus protocol No pipeline No physical clock .... Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 7 / 42 >.
(16) SoCs and TLM. jTLM. sc-during. Conclusion. An example TLM Model. CPU process = C++ code. ITC. Timer. VGA. TLM Bus. Data RAM. Matthieu Moy (Verimag). Instruction RAM. Time in Discrete-Event Simulation. GPIO. November 2012. < 8 / 42 >.
(17) SoCs and TLM. jTLM. sc-during. Conclusion. Performance of TLM. Pure RTL. 1 hour. RTL + cosimulation. x20. 3 minutes. TLM. x60. 3 seconds x3. HW emulation. 1 second. Simulation time (second) logarithmic scale 1. Matthieu Moy (Verimag). 10. 100. Time in Discrete-Event Simulation. 10000. November 2012. < 9 / 42 >.
(18) SoCs and TLM. jTLM. sc-during. Conclusion. Uses of Functional Models Reference for Hardware Validation. SPEC. Virtual Prototype for Software Development. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 10 / 42 >.
(19) SoCs and TLM. jTLM. sc-during. Conclusion. Uses of Functional Models Reference for Hardware Validation. SPEC. ?. =. RTL. Virtual Prototype for Software Development. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 10 / 42 >.
(20) SoCs and TLM. jTLM. sc-during. Conclusion. Uses of Functional Models Reference for Hardware Validation. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. Virtual Prototype for Software Development. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 10 / 42 >.
(21) SoCs and TLM. jTLM. sc-during. Conclusion. Uses of Functional Models Reference for Hardware Validation. Virtual Prototype for Software Development. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (Verimag). Instruction RAM. GPIO. Time in Discrete-Event Simulation. November 2012. < 10 / 42 >.
(22) SoCs and TLM. jTLM. sc-during. Conclusion. Uses of Functional Models Reference for Hardware Validation. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. Unmodified Software Virtual Prototype for Software Development. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (Verimag). Instruction RAM. GPIO. Time in Discrete-Event Simulation. November 2012. < 10 / 42 >.
(23) SoCs and TLM. jTLM. sc-during. Conclusion. Uses of Functional Models Reference for Hardware Validation. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. Unmodified Software Virtual Prototype for Software Development. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (Verimag). Instruction RAM. GPIO. ?. ⊇. Time in Discrete-Event Simulation. November 2012. < 10 / 42 >.
(24) SoCs and TLM. jTLM. sc-during. Conclusion. Content of a TLM Model A richer definition. Timing information I I. May be needed for Software Execution Useful for Profiling Software 60 50 40 30. Power and Temperature I I. 20 10 0 10. Validate design choices Validate power-management policy. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. 20 30. November 2012. < 11 / 42 >.
(25) SoCs and TLM. jTLM. sc-during. Conclusion. SystemC. SystemC is ... I I I I. a library for C++ a discrete-event simulator well-suited for TLM (an IEEE standard). SystemC/TLM programs are ... I I I. fast (details abstracted away, efficiency of C++) not fast enough (no physical parallelism) too deterministic?. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 12 / 42 >.
(26) SoCs and TLM. jTLM. sc-during. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. jTLM: Experiments Without SystemC. 3. Back to SystemC: sc-during. 4. Conclusion. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 13 / 42 >.
(27) SoCs and TLM. jTLM. sc-during. Conclusion. SystemC/TLM vs. “TLM Abstraction Level” SystemC. Matthieu Moy (Verimag). TLM. Time in Discrete-Event Simulation. November 2012. < 14 / 42 >.
(28) SoCs and TLM. jTLM. sc-during. Conclusion. SystemC/TLM vs. “TLM Abstraction Level” SystemC. TLM. Cycle accurate TLM 2.0. RTL. Gate level. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 14 / 42 >.
(29) SoCs and TLM. jTLM. sc-during. Conclusion. SystemC/TLM vs. “TLM Abstraction Level” SystemC Cycle accurate. TLM. Parallelism. Clocks RTL Coroutine semantics Gate level δ-cycle. Matthieu Moy (Verimag). Function TLM calls 2.0. Time in Discrete-Event Simulation. November 2012. < 14 / 42 >.
(30) SoCs and TLM. jTLM. sc-during. Conclusion. SystemC/TLM vs. “TLM Abstraction Level” SystemC Cycle accurate. TLM. Parallelism. Clocks RTL Coroutine semantics Gate level δ-cycle. Matthieu Moy (Verimag). Function TLM calls 2.0. ?. Time in Discrete-Event Simulation. November 2012. < 14 / 42 >.
(31) SoCs and TLM. jTLM. sc-during. Conclusion. SystemC/TLM vs. “TLM Abstraction Level” SystemC Cycle accurate. TLM. Parallelism. Clocks RTL Coroutine semantics Gate level δ-cycle. Matthieu Moy (Verimag). jTLM = Alternative to SystemC. Function TLM calls 2.0. ?. Time in Discrete-Event Simulation. November 2012. < 14 / 42 >.
(32) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM: Goals and Peculiarities. jTLM’s initial goal: define “TLM” independently of SystemC I I I. Not cooperative (true parallelism) Not C++ (Java) No δ-cycle. Interesting features I I. Small and simple code (≈ 500 LOC) Nice experimentation platform. Not meant for production. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 15 / 42 >.
(33) SoCs and TLM. jTLM. sc-during. Conclusion. Wall-clock time. Simulated Time Vs Wall-Clock Time. Time elapse Computation. 0. 10. 20. 30. 40. Simulated time. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 16 / 42 >.
(34) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM. SystemC. (Simulated) Time in SystemC and jTLM. A B. P Q. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 17 / 42 >.
(35) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM. SystemC. (Simulated) Time in SystemC and jTLM. A B. Process A: // computation f(); // time taken by f wait(20, SC_NS);. P Q. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 17 / 42 >.
(36) SoCs and TLM. jTLM. sc-during. Conclusion. (Simulated) Time in SystemC and jTLM. jTLM. SystemC. f() wait(20) A B. Process A: // computation f(); // time taken by f wait(20, SC_NS);. P Q. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 17 / 42 >.
(37) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM. SystemC. (Simulated) Time in SystemC and jTLM f() wait(20). Process A: // computation f(); // time taken by f wait(20, SC_NS);. g() awaitTime. Process P: g(); awaitTime(20);. A B. P Q. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 17 / 42 >.
(38) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM. SystemC. (Simulated) Time in SystemC and jTLM f() wait(20). Process A: // computation f(); // time taken by f wait(20, SC_NS);. g() awaitTime. Process P: g(); awaitTime(20); consumesTime(15) { h(); }. A B. P Q. Matthieu Moy (Verimag). h(). Time in Discrete-Event Simulation. November 2012. < 17 / 42 >.
(39) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM. SystemC. (Simulated) Time in SystemC and jTLM f() wait(20). Process A: // computation f(); // time taken by f wait(20, SC_NS);. g() awaitTime. Process P: g(); awaitTime(20); consumesTime(15) { h(); }. A B. h(). P Q. i(). Matthieu Moy (Verimag). j(). Time in Discrete-Event Simulation. November 2012. < 17 / 42 >.
(40) SoCs and TLM. jTLM. sc-during. Conclusion. By default, time does not elapse ⇒ instantaneous tasks awaitTime(T) : suspend and let other processes execute for T time units. Matthieu Moy (Verimag). Wall-clock time. Time à la SystemC: awaitTime(T). Time elapse Computation 0. 10. 20. 30. 40. Simulated time f(); // instantaneous awaitTime(20);. Time in Discrete-Event Simulation. November 2012. < 18 / 42 >.
(41) SoCs and TLM. jTLM. sc-during. Conclusion. Task with Known Duration: consumesTime(T). Semantics: I I. Start and end dates known Actions contained in task spread in between. Advantages: I I I. Model closer to actual system Less bugs hidden Better parallelization. Matthieu Moy (Verimag). consumesTime(15) { f1(); f2(); f3(); } consumesTime(10) { g(); }. Time in Discrete-Event Simulation. November 2012. < 19 / 42 >.
(42) SoCs and TLM. jTLM. sc-during. Conclusion. Execution of consumesTime(T) Fast computation. Slow computation Task finishes. Task starts 0. 10. 20. 30. 40. Computation ends. Wall-clock time. Wall-clock time. Simulated time blocked. Task finishes. Rest of the platform drives time Task starts 0. Simulated time. 10. 20. 30. 40. Simulated time idle. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 20 / 42 >.
(43) SoCs and TLM. jTLM. sc-during. Conclusion. Addressing the Faithfulness Issue: Exposing Bugs Example bug: mis-placed synchronization: imgReady = true; awaitTime(5); writeIMG(); awaitTime(10);. ||. while(!imgReady) awaitTime(1); awaitTime(10); readIMG();. ⇒ bug never seen in simulation. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 21 / 42 >.
(44) SoCs and TLM. jTLM. sc-during. Conclusion. Addressing the Faithfulness Issue: Exposing Bugs Example bug: mis-placed synchronization: imgReady = true; awaitTime(5); writeIMG(); awaitTime(10);. ||. while(!imgReady) awaitTime(1); awaitTime(10); readIMG();. ⇒ bug never seen in simulation consumesTime(15) { imgReady = true; writeIMG(); }. ||. while(!imgReady) awaitTime(1); awaitTime(10); readIMG();. ⇒ strictly more behaviors, including the buggy one. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 21 / 42 >.
(45) SoCs and TLM. jTLM. sc-during. Conclusion. Parallelization P1 jTLM’s Semantics P2 Simultaneous tasks run in parallel. P3 P4. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 22 / 42 >.
(46) SoCs and TLM. jTLM. sc-during. Conclusion. Parallelization P1 jTLM’s Semantics P2 Simultaneous tasks run in parallel. P3. Non-simultaneous tasks don’t P4. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 22 / 42 >.
(47) SoCs and TLM. jTLM. sc-during. Conclusion. Parallelization P1 jTLM’s Semantics P2 Simultaneous tasks run in parallel. P3. Non-simultaneous tasks don’t Overlapping tasks do. P4. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 22 / 42 >.
(48) SoCs and TLM. jTLM. sc-during. Conclusion. Parallelization P1 jTLM’s Semantics P2 Simultaneous tasks run in parallel. P3. Non-simultaneous tasks don’t Overlapping tasks do. P4 Back to SystemC: I I. Parallelizing within δ-cycle = great if you have clocks Simulated time is the bottleneck with quantitative/fuzzy time. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 22 / 42 >.
(49) SoCs and TLM. jTLM. sc-during. Conclusion. Parallelization P1 jTLM’s Semantics P2 Simultaneous tasks run in parallel. P3. Non-simultaneous tasks don’t Overlapping tasks do. P4 Back to SystemC: I I. Parallelizing within δ-cycle = great if you have clocks Simulated time is the bottleneck with quantitative/fuzzy time. Can we apply the idea of duration to SystemC? (Answer in next section) Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 22 / 42 >.
(50) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and awaitTime(T) Current instant. P, Q, R Process P: f(); awaitTime(50);. Matthieu Moy (Verimag). Process Q: h(); awaitTime(30); g(); awaitTime(30); Time in Discrete-Event Simulation. Process R: i(); awaitTime(90);. November 2012. < 23 / 42 >.
(51) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and awaitTime(T) Current instant. awaitTime(50). Q, R Process P: f(); awaitTime(50);. Matthieu Moy (Verimag). P Process Q: h(); awaitTime(30); g(); awaitTime(30); Time in Discrete-Event Simulation. Process R: i(); awaitTime(90);. November 2012. < 23 / 42 >.
(52) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and awaitTime(T) Current instant awaitTime(30). R Process P: f(); awaitTime(50);. Matthieu Moy (Verimag). Q. P. Process Q: h(); awaitTime(30); g(); awaitTime(30); Time in Discrete-Event Simulation. Process R: i(); awaitTime(90);. November 2012. < 23 / 42 >.
(53) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and awaitTime(T) Current instant. awaitTime(90). Q Process P: f(); awaitTime(50);. Matthieu Moy (Verimag). P. Process Q: h(); awaitTime(30); g(); awaitTime(30); Time in Discrete-Event Simulation. R Process R: i(); awaitTime(90);. November 2012. < 23 / 42 >.
(54) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and awaitTime(T) Current instant. Time Elapse Q Process P: f(); awaitTime(50);. Matthieu Moy (Verimag). P. Process Q: h(); awaitTime(30); g(); awaitTime(30); Time in Discrete-Event Simulation. R Process R: i(); awaitTime(90);. November 2012. < 23 / 42 >.
(55) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and awaitTime(T) Current instant. Q Process P: f(); awaitTime(50);. Matthieu Moy (Verimag). P. Process Q: h(); awaitTime(30); g(); awaitTime(30); Time in Discrete-Event Simulation. R Process R: i(); awaitTime(90);. November 2012. < 23 / 42 >.
(56) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T). What about consumesTime(T)?. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 24 / 42 >.
(57) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. P, Q, R Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(90); awaitTime(30); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(58) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. consumesTime(50). Q, R. P. Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(90); awaitTime(30); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(59) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. Q, R. P. Process P: Process R: Process Q: l(); f(); i(); consumesTime(50){ awaitTime(90); awaitTime(30); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(60) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant awaitTime(30). R. Q. P. Process P: Process R: Process Q: l(); f(); i(); consumesTime(50){ awaitTime(30); awaitTime(90); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(61) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. awaitTime(90). Q. P. R. Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(30); awaitTime(90); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(62) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. Time Elapse Q. P. R. Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(30); awaitTime(90); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(63) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. Q. P. R. Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(90); awaitTime(30); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(64) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant consumesTime(30). P. R. Q. Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(90); awaitTime(30); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(65) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. P. R. Q. Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(90); awaitTime(30); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(66) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. Time Elapse P. R. Q. Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(90); awaitTime(30); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(67) SoCs and TLM. jTLM. sc-during. Conclusion. Time Queue and consumesTime(T) Current instant. P. R. Q. Process P: Process R: Process Q: f(); l(); i(); consumesTime(50){ awaitTime(90); awaitTime(30); g(); j(); } consumesTime(30){ h(); k(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 25 / 42 >.
(68) SoCs and TLM. jTLM. sc-during. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. jTLM: Experiments Without SystemC. 3. Back to SystemC: sc-during. 4. Conclusion. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 26 / 42 >.
(69) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM is cool ... ... but nobody will use it.. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 27 / 42 >.
(70) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. the Idea. Goal: allow during tasks in SystemC I I. Without modifying SystemC Allowing physical parallelism. Idea: let SystemC processes delegate computation to a separate thread. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 28 / 42 >.
(71) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Sketch of Implementation. void during(sc_core::sc_time duration, boost::function<void()> routine) { À boost::thread t(routine); // create thread Á sc_core::wait(duration); // let SystemC execute  t.join(); // wait for thread completion } A B C. pthread Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 29 / 42 >.
(72) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Sketch of Implementation. void during(sc_core::sc_time duration, boost::function<void()> routine) { À boost::thread t(routine); // create thread Á sc_core::wait(duration); // let SystemC execute  t.join(); // wait for thread completion } during(5, f); A B C. pthread Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 29 / 42 >.
(73) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Sketch of Implementation. void during(sc_core::sc_time duration, boost::function<void()> routine) { À boost::thread t(routine); // create thread Á sc_core::wait(duration); // let SystemC execute  t.join(); // wait for thread completion } during(5, f); A B C. À create thread. pthread Matthieu Moy (Verimag). routine Time in Discrete-Event Simulation. November 2012. < 29 / 42 >.
(74) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Sketch of Implementation. void during(sc_core::sc_time duration, boost::function<void()> routine) { À boost::thread t(routine); // create thread Á sc_core::wait(duration); // let SystemC execute  t.join(); // wait for thread completion } during(5, f); A B C. À create thread. pthread Matthieu Moy (Verimag). Á wait(d). routine Time in Discrete-Event Simulation. November 2012. < 29 / 42 >.
(75) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Sketch of Implementation. void during(sc_core::sc_time duration, boost::function<void()> routine) { À boost::thread t(routine); // create thread Á sc_core::wait(duration); // let SystemC execute  t.join(); // wait for thread completion } during(5, f); A B C. À create thread. pthread Matthieu Moy (Verimag). Á wait(d). routine Time in Discrete-Event Simulation. November 2012. < 29 / 42 >.
(76) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Sketch of Implementation. void during(sc_core::sc_time duration, boost::function<void()> routine) { À boost::thread t(routine); // create thread Á sc_core::wait(duration); // let SystemC execute  t.join(); // wait for thread completion } during(5, f); A B C. create thread pthread Matthieu Moy (Verimag). Â. À Á wait(d). join thread. routine Time in Discrete-Event Simulation. November 2012. < 29 / 42 >.
(77) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Sketch of Implementation. void during(sc_core::sc_time duration, boost::function<void()> routine) { À boost::thread t(routine); // create thread Á sc_core::wait(duration); // let SystemC execute  t.join(); // wait for thread completion } during(5, f); A B C. create thread pthread Matthieu Moy (Verimag). Â. À Á wait(d). join thread. routine Time in Discrete-Event Simulation. November 2012. < 29 / 42 >.
(78) SoCs and TLM. jTLM. sc-during. Conclusion. Wait ... are you saying that parallelization is just about fork/join?. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 30 / 42 >.
(79) SoCs and TLM. jTLM. sc-during. Conclusion. Wait ... are you saying that parallelization is just about fork/join? Well, sometimes it is .... Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 30 / 42 >.
(80) SoCs and TLM. jTLM. sc-during. Conclusion. When Things are Easy: Pure Function Before. After. compute_in_systemc();. compute_in_systemc();. // my profiler says it’s // performance critical. // does not communicate // with other processes. big_computation(); wait(10, SC_MS);. // Won’t be a performance // bottleneck anymore during(10, SC_MS, big_computation); next_computation();. next_computation();. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 31 / 42 >.
(81) SoCs and TLM. jTLM. sc-during. Conclusion. Wait ... are you saying that parallelization is just about fork/join? Well, sometimes it is .... Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 32 / 42 >.
(82) SoCs and TLM. jTLM. sc-during. Conclusion. Wait ... are you saying that parallelization is just about fork/join? Well, sometimes it is ... ... and sometimes it isn’t: Time synchronization: make sure things are executed at the right simulated time Data/scheduler synchronization: avoid data-race between tasks, processes and the SystemC scheduler. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 32 / 42 >.
(83) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Synchronization. extra_time(t): increase current task duration wait(5) initial extra time P duration. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 33 / 42 >.
(84) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Synchronization. extra_time(t): increase current task duration wait(5) initial extra time P duration catch_up(t): block task until SystemC’s time reaches the end of the current task while (!c) { extra_time(10, SC_NS); catch_up(); // ensures fairness }. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 33 / 42 >.
(85) SoCs and TLM. jTLM. EXTRA _ TIME ():. sc-during. Conclusion. Sketch of Implementation. void during(duration, routine) { end = now() + duration; boost::thread t(routine); // used to be just sc_core::wait(duration) while (now() != end) { sc_core::wait(end - now()); } t.join(); } void extra_time(duration) { end += duration; }. Matthieu Moy (Verimag). void catch_up() { while (now() != end) { // avoid busy-waiting condition.wait(); } }. Time in Discrete-Event Simulation. November 2012. < 34 / 42 >.
(86) SoCs and TLM. jTLM. sc-during. Conclusion. Temporal decoupling and sc-during Plain SystemC. sc-during. f(); t_local += 42; g(); t_local += 12;. f(); extra_time(42); g(); extra_time(12);. wait(t_local); t_local = 0; i();. catch_up();. Matthieu Moy (Verimag). i();. Time in Discrete-Event Simulation. November 2012. < 35 / 42 >.
(87) SoCs and TLM. jTLM. sc-during. Conclusion. sc_call: be cooperative for a while. sc_call(f): call function f in the context of SystemC e.notify(); // Forbidden in during tasks sc_call("e.notify()"); // OK (modulo syntax) sc_call("i++"); // implicit big lock, // no data-race. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 36 / 42 >.
(88) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. during(5, f); A B C. pthread. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 37 / 42 >.
(89) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. during(5, f); A B C wait(d or sync_ev) create thread pthread. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 37 / 42 >.
(90) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. during(5, f); A B C wait(d or sync_ev) create thread pthread. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 37 / 42 >.
(91) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. during(5, f); A B C wait(d or sync_ev) create thread pthread sc_call(g) Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 37 / 42 >.
(92) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. during(5, f); A B g. C wait(d or sync_ev) create thread. notify sync_ev. pthread sc_call(g) Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 37 / 42 >.
(93) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. during(5, f); A B g. C wait(d or sync_ev) create thread. sc_call_f. notify sync_ev. = 0. pthread sc_call(g) Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 37 / 42 >.
(94) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. during(5, f); A B g. C. wait. wait(d or sync_ev) create thread. sc_call_f. notify sync_ev. = 0. pthread sc_call(g) Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 37 / 42 >.
(95) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. during(5, f); A B g. C. wait. wait(d or sync_ev) create thread. sc_call_f. notify sync_ev. = 0. join thread. pthread sc_call(g) Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 37 / 42 >.
(96) SoCs and TLM. jTLM. SC _ CALL :. sc-during. Conclusion. Sketch of Implementation. void during(duration, f) { void sc_call(f) { end = now() + duration; sc_call_f = f; boost::thread t(f); // Implemented while (now() != end) { // with SystemC 2.3’s // wait sync_ev // async_request_update() // with timeout: async_notify_event sc_core::wait (sync_ev); (sync_ev, while(sc_call_f != 0) { end - now()); condition.wait(); if (sc_call_f) { } sc_call_f(); } sc_call_f = 0; condition.notify(); } } t.join(); } Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 38 / 42 >.
(97) SoCs and TLM. jTLM. SC - DURING :. sc-during. Conclusion. Actual Implementation. SC_THREAD_1. sync_task_1. OS thread_1. SC_THREAD_2. sync_task_2. OS thread_2. sync_task_N. OS thread_N. .. . SC_THREAD_N SystemC. OS Threads. Possible strategies: SEQ Sequential (= reference) THREAD Thread created/destroyed each time POOL Pre-allocated worker threads pool ONDEMAND Thread created on demand and reused later Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 39 / 42 >.
(98) SoCs and TLM. jTLM. sc-during. SC - DURING :. 12 10 8. Results. thread, during_quant thread, during_sync ondemand, during_quant ondemand, during_sync. Speedup. 14. Conclusion. Loosely-Timed Models. 6 4. Fine-grain Timing. 2. Number of CPU in the platform. 0 10. 20. 30. 40. 50. 60. Test machine has 4 × 12 = 48 cores Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 40 / 42 >.
(99) SoCs and TLM. jTLM. sc-during. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. jTLM: Experiments Without SystemC. 3. Back to SystemC: sc-during. 4. Conclusion. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 41 / 42 >.
(100) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM and SC - DURING: Conclusion New way to express concurrency in the platform Allows parallel execution of loosely-timed (clockless) systems jTLM: experimentation platform, new scheduler sc-during: jTLM’s ideas, implemented on top of SystemC. Still room for performance optimizations.. Try it: https://forge.imag.fr/projects/sc-during/. Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 42 / 42 >.
(101) SoCs and TLM. jTLM. sc-during. Conclusion. jTLM and SC - DURING: Conclusion New way to express concurrency in the platform Allows parallel execution of loosely-timed (clockless) systems jTLM: experimentation platform, new scheduler sc-during: jTLM’s ideas, implemented on top of SystemC. Still room for performance optimizations.. Try it: https://forge.imag.fr/projects/sc-during/. Questions ? Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 42 / 42 >.
(102) SoCs and TLM. jTLM. sc-during. Conclusion. Sources. http://en.wikipedia.org/wiki/File:Diopsis.jpg (Peter John Bishop, CC Attribution-Share Alike 3.0 Unported). http://www.fotopedia.com/items/flickr-367843750 (oskay@fotopedia, CC Attribution 2.0 Generic). Matthieu Moy (Verimag). Time in Discrete-Event Simulation. November 2012. < 42 / 42 >.
(103)
Documents relatifs
They will however miss important aspects of the execution of a SystemC program, like: how much time is spent in the SystemC kernel as opposed to the user-written parts, per-
PAGAI is a prototype interprocedural static analyzer, that implements our re- cent combined techniques [11] as well as the classical abstract interpretation algorithm, and
We have implemented our proposed solutions inside a prototype of intraproce- dural static analyzer called PAGAI, as well as the classical abstract interpretation algorithm, and
When a behavior starts at time 0 a task with the duration of 20 time units ( consumesTime(20) ), all actions that are part of that task will be simulated somewhere between times 0
This paper proposes a solution based on an asynchronous model (namely Promela) to encode TLM concurrent programs, that consists in modeling the asynchronous communications and
Habilitation à Diriger des Recherches High-level Models for Embedded Systems Matthieu Moy Verimag Grenoble INP Grenoble, France.. March 13th 2014 Jury: Gérard Berry Rolf Drechsler
Modeling of Time in Discrete-Event Simulation of Systems-on-Chip Giovanni Funchal1,2 and Matthieu Moy1 1 Verimag.. Grenoble INP
Efficient and Playful Tools to Teach Unix to New Students Matthieu Moy Grenoble-INP, Ensimag.. Matthieu Moy
