Habilitation à Diriger des Recherches High-level Models for Embedded Systems
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(2) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. About Me. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 2 / 51 >.
(3) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. About Me. Teaching at Ensimag Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 2 / 51 >.
(4) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. About Me. Research at Verimag. Teaching at Ensimag Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 2 / 51 >.
(5) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. About Me The SystemC guy Research at Verimag. Teaching at Ensimag Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 2 / 51 >.
(6) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. About Me The SystemC guy. The RTC guy. Research at Verimag. Teaching at Ensimag Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 2 / 51 >.
(7) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. About Me The SystemC guy. The RTC guy Also works on abstract interpretation. Research at Verimag. Teaching at Ensimag Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 2 / 51 >.
(8) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. About Me The SystemC guy. The RTC guy. Research at Verimag. Also works on abstract interpretation. Teaching at Ensimag. The macarons guy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 2 / 51 >.
(9) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. What Are Processors For?. Computers. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 3 / 51 >.
(10) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. What Are Processors For?. Computers. Embedded systems. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 3 / 51 >.
(11) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. What Are Processors For?. Computers. Vertebrate. Embedded systems. Insects. Source: http://skepchick.org/2013/03/planet-of-the-arthropods/ Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 3 / 51 >.
(12) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. What Are Processors For?. Computers ≈ 2%. Vertebrate ≈ 4%. Embedded systems ≈ 98%. Insects ≈ 96%. Source: http://skepchick.org/2013/03/planet-of-the-arthropods/ Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 3 / 51 >.
(13) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Prehistory: My Phone (2010). Source: http://www.embeddedinsights.com/epd/samsung/samsung-s5pc110.php Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 4 / 51 >.
(14) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Another Typical Embedded System: my New Camera. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 5 / 51 >.
(15) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Another Typical Embedded System: my New Camera. Firmware Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 5 / 51 >.
(16) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Another Typical Embedded System: my New Camera. Firmware A Matthieu Moy (Verimag). Firmware B High-level Models for Embedded Systems. March 13th 2014. < 5 / 51 >.
(17) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Another Typical Embedded System: my New Camera. Firmware A Matthieu Moy (Verimag). Firmware B High-level Models for Embedded Systems. March 13th 2014. < 5 / 51 >.
(18) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Modern Systems-on-a-Chip. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 6 / 51 >.
(19) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Modern Systems-on-a-Chip Software. Hardware. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 6 / 51 >.
(20) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 1: Functional Correctness. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 7 / 51 >.
(21) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 1: Functional Correctness. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 7 / 51 >.
(22) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 1: Functional Correctness. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 7 / 51 >.
(23) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 2: Early Software Development Traditional Design-Flow Specification, Algorithm. Time. RTL Design. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 8 / 51 >.
(24) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 2: Early Software Development Traditional Design-Flow Specification, Algorithm. Time. RTL Design. Synthesis cost > 1,000,000 $ ! Factory Software Development Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 8 / 51 >.
(25) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Time. Issue 2: Early Software Development Traditional Design-Flow. Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 8 / 51 >.
(26) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 2: Early Software Development Traditional Design-Flow. Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Time. Software Development Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 8 / 51 >.
(27) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 2: Early Software Development Traditional Design-Flow. Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Model. Time. Software Development Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 8 / 51 >.
(28) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 2: Early Software Development Traditional Design-Flow. Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Model. Time. Software Development Synthesis. Synthesis Integration. Factory Software Development. Factory. Validation. Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 8 / 51 >.
(29) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 2: Early Software Development Traditional Design-Flow. Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Model. Time. Software Development Synthesis. Synthesis Integration. Factory Software Development. Factory. Validation. gain. Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 8 / 51 >.
(30) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 3: Timing. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 9 / 51 >.
(31) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 4: Power and Temperature. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 10 / 51 >.
(32) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 4: Power and Temperature. 50-130 watt. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 10 / 51 >.
(33) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 4: Power and Temperature. 50-130 watt 20-30 watt. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 10 / 51 >.
(34) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 4: Power and Temperature. 20 watt. 50-130 watt 20-30 watt. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 10 / 51 >.
(35) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 4: Power and Temperature. 20 watt. 50-130 watt < 1 watt 20-30 watt. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 10 / 51 >.
(36) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 5: Simulation speed. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 11 / 51 >.
(37) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 6: Model Faithfulness model. actual. Unmodeled behaviors (B) Extra behaviors of the model (A). Matthieu Moy (Verimag). Exactly modeled behaviors (C). High-level Models for Embedded Systems. March 13th 2014. < 12 / 51 >.
(38) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Models and Virtual Prototypes. Model/Prototype. Matthieu Moy (Verimag). High-level Models for Embedded Systems. Real system. March 13th 2014. < 13 / 51 >.
(39) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Models and Virtual Prototypes. Synthesize. Model/Prototype. Matthieu Moy (Verimag). High-level Models for Embedded Systems. Real system. March 13th 2014. < 13 / 51 >.
(40) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Models and Virtual Prototypes. (Synthesize). Model/Prototype. Matthieu Moy (Verimag). High-level Models for Embedded Systems. Real system. March 13th 2014. < 13 / 51 >.
(41) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Models and Virtual Prototypes. (Synthesize) Compare Use as specification .... Model/Prototype. Matthieu Moy (Verimag). High-level Models for Embedded Systems. Real system. March 13th 2014. < 13 / 51 >.
(42) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Context and Collaborations of my Work 2002. 2005 My Ph.D. 2010. 2014. G. Funchal Ph.D OpenTLM FoToVP. OpenES HELP. Combest. CESyMPA.
(43) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Context and Collaborations of my Work 2002. 2005 My Ph.D. STMicroelectronics 2010. 2014. G. Funchal Ph.D OpenTLM FoToVP. OpenES HELP. Combest. CESyMPA.
(44) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Context and Collaborations of my Work 2002. STMicroelectronics 2010. 2005 My Ph.D. 2014. G. Funchal Ph.D OpenTLM FoToVP. CESyMPA. HELP Combest. CEA-LETI IRISA ETHZ. Matthieu Moy (Verimag). OpenES. INRIA Rhone Alpes. High-level Models for Embedded Systems. TIMA Docea Power. March 13th 2014. < 14 / 51 >.
(45) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Outline Real-Time Calculus. Abstract Interpretation. T C/ em st. LM. Sy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 15 / 51 >.
(46) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Outline Real-Time Calculus. Abstract Interpretation. T C/ em st. LM. Sy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 15 / 51 >.
(47) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. TLM and Software Development Traditional Design-Flow. Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Model. Time. Software Development Synthesis. Synthesis Integration. Factory Software Development. Factory. Validation. gain. Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 16 / 51 >.
(48) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. TLM and Software Development Traditional Design-Flow. Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. TLM Model. Time. Software Development Synthesis. Synthesis Integration. Factory Software Development. Factory. Validation. gain. Integration. Validation. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 16 / 51 >.
(49) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 17 / 51 >.
(50) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow. ≈ 1000 Faster than low-level simulations (RTL). Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 17 / 51 >.
(51) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow. ≈ 1000 Faster than low-level simulations (RTL) In production in the industry Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 17 / 51 >.
(52) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Content of a TLM Model Model what is needed for Software Execution: I I I. Processors Address-map Concurrency. read - addr - data. write - addr - data. ... and only that. I I I I I. No micro-architecture No bus protocol No pipeline No physical clock .... addr data. Standard for TLM = SystemC (IEEE1666). Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 18 / 51 >.
(53) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. An Example TLM Model. CPU ITC. process = C++ code. Timer. VGA. TLM Bus. Data RAM. Matthieu Moy (Verimag). Instruction RAM. High-level Models for Embedded Systems. GPIO. March 13th 2014. < 19 / 51 >.
(54) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Uses of Functional Models Reference for Hardware Validation. SPEC. Virtual Prototype for Software Development. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 20 / 51 >.
(55) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Uses of Functional Models Reference for Hardware Validation. SPEC. ?. =. RTL. Virtual Prototype for Software Development. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 20 / 51 >.
(56) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Uses of Functional Models Reference for Hardware Validation. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. Virtual Prototype for Software Development. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 20 / 51 >.
(57) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Uses of Functional Models Reference for Hardware Validation. Virtual Prototype for Software Development. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. CPU ITC. process = C++ code. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (Verimag). Instruction RAM. GPIO. High-level Models for Embedded Systems. March 13th 2014. < 20 / 51 >.
(58) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Uses of Functional Models Reference for Hardware Validation. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. Unmodified Software Virtual Prototype for Software Development. CPU ITC. process = C++ code. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (Verimag). Instruction RAM. GPIO. High-level Models for Embedded Systems. March 13th 2014. < 20 / 51 >.
(59) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Non-Functional Models Timing, Power consumption, Temperature Estimation. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (Verimag). Instruction RAM. GPIO. High-level Models for Embedded Systems. March 13th 2014. < 21 / 51 >.
(60) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Non-Functional Models Timing, Power consumption, Temperature Estimation. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. 60. 60. 50. 50. 40. 40. 30. 30. 20. 20. 10. 10. 0. 0. 10. 10. 20. 20. 30. 30. Estimated Time/Power/Temperature Matthieu Moy (Verimag). High-level Models for Embedded Systems. Actual March 13th 2014. < 21 / 51 >.
(61) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Non-Functional Models Timing, Power consumption, Temperature Estimation. Unmodified Power/Temperature-Aware Software. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. 60. 60. 50. 50. 40. 40. 30. 30. 20. 20. 10. 10. 0. 0. 10. 10. 20. 20. 30. 30. Estimated Time/Power/Temperature Matthieu Moy (Verimag). High-level Models for Embedded Systems. Actual March 13th 2014. < 21 / 51 >.
(62) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Timing. Faithfulness. Early Software Execution. Simulation Speed. Power/Temperature Correctness Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 22 / 51 >.
(63) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 22 / 51 >.
(64) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 22 / 51 >.
(65) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. SystemC: Simple Example A int sc_main (int, char **) { /* Instanciate modules */ A a("Alice"); B b("Bob");. B struct A : sc_module { /* Connection to outside */ initiator_socket socket; /* Behavior */ void thread() { do_stuff(); write(socket, addr, data); }. /* Connect them together */ a.socket.bind(b.socket); /* and start simulation */ sc_start(); return 0;. SC_CTOR(A) { SC_THREAD(thread); }. } };. ; Compilable with any C++ compiler. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 23 / 51 >.
(66) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Challenges and Solutions with SystemC Front-Ends 1. C++ is complex (e.g. clang++ ≈ 400,000 LOC). 2. Architecture built at runtime, with C++ code. int sc_main (int, char **) { /* Instanciate modules */ A a("Alice"); B b("Bob");. struct A : sc_module { /* Connection to outside */ initiator_socket socket; /* Behavior */ void thread() { do_stuff(); write(socket, addr, data); }. /* Connect them together */ a.socket.bind(b.socket); /* and start simulation */ sc_start(); return 0;. SC_CTOR(A) { SC_THREAD(thread); }. } };. Matthieu Moy (Verimag). Kevin Marquet. High-level Models for Embedded Systems. Guillaume Sergent March 13th 2014. < 24 / 51 >.
(67) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Challenges and Solutions with SystemC Front-Ends 1. 2. C++ is complex (e.g. clang++ ≈ 400,000 LOC) ; Write a C++ front-end or reuse one (g++, clang++, EDG, . . . ) Architecture built at runtime, with C++ code ; Analyze elaboration phase or execute it. int sc_main (int, char **) { /* Instanciate modules */ A a("Alice"); B b("Bob");. struct A : sc_module { /* Connection to outside */ initiator_socket socket; /* Behavior */ void thread() { do_stuff(); write(socket, addr, data); }. /* Connect them together */ a.socket.bind(b.socket); /* and start simulation */ sc_start(); return 0;. SC_CTOR(A) { SC_THREAD(thread); }. } };. Matthieu Moy (Verimag). Kevin Marquet. High-level Models for Embedded Systems. Guillaume Sergent March 13th 2014. < 24 / 51 >.
(68) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Challenges and Solutions with SystemC Front-Ends 1. 2. C++ is complex (e.g. clang++ ≈ 400,000 LOC) ; Write a C++ front-end or reuse one (g++, clang++, EDG, . . . ) Architecture built at runtime, with C++ code ; Analyze elaboration phase or execute it. int sc_main (int, char **) { /* Instanciate modules */ A a("Alice"); B b("Bob");. struct A : sc_module { /* Connection to outside */ initiator_socket socket;. Dynamic Approaches. /* Behavior */ void thread() { do_stuff(); write(socket, addr, data); }. /* Connect them together */ a.socket.bind(b.socket);. Static /*Approaches and start simulation. */. sc_start(); return 0;. SC_CTOR(A) { SC_THREAD(thread); }. } };. Matthieu Moy (Verimag). Kevin Marquet. High-level Models for Embedded Systems. Guillaume Sergent March 13th 2014. < 24 / 51 >.
(69) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 25 / 51 >.
(70) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 25 / 51 >.
(71) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Formal Verification: Encoding Approaches SystemC program Property. Encoding. Built-in knowledge of SystemC. Formal language Existing verifier. Lesar, Nbac (Lustre) SMV SPIN (Promela). Yes/No/Maybe Kevin Marquet Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 26 / 51 >.
(72) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 27 / 51 >.
(73) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models Giovanni Funchal. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 27 / 51 >.
(74) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Nabila Abdessaied Verification. Memory Models jTLM. Faithfulness Traffic models Giovanni Funchal. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 27 / 51 >.
(75) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 27 / 51 >.
(76) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Simulation Parallelization. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 28 / 51 >.
(77) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Simulation Parallelization. SystemC uses co-routine semantics (Sequential). Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 28 / 51 >.
(78) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Problems and Solutions for Parallel Execution of SystemC/TLM. (1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable). Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 29 / 51 >.
(79) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Problems and Solutions for Parallel Execution of SystemC/TLM. (1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable). ; No efficient and automatic solution for SystemC/TLM. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 29 / 51 >.
(80) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Problems and Solutions for Parallel Execution of SystemC/TLM. (1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable). ; No efficient and automatic solution for SystemC/TLM Our proposal = new constructs: Desynchronisation (1) / Synchronisation (2). Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 29 / 51 >.
(81) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. The Idea. SC_THREAD_1. OS thread_1. SC_THREAD_2. OS thread_2. .. . SC_THREAD_N. OS thread_N. SystemC. OS Thread. Unmodified SystemC Computations delegated to external threads Weak synchronization between SystemC and tasks with duration Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 30 / 51 >.
(82) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. SC - DURING. SystemC. Simulated Time in SystemC and SC - DURING. A B. P Q. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 31 / 51 >.
(83) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Simulated Time in SystemC and SC - DURING. SC - DURING. SystemC. f() wait(20) A B. Process A: // computation f(); // time taken by f wait(20, SC_NS);. P Q. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 31 / 51 >.
(84) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. SC - DURING. SystemC. Simulated Time in SystemC and SC - DURING f() wait(20). Process A: // computation f(); // time taken by f wait(20, SC_NS);. g() wait(20). Process P: g(); wait(20, SC_NS);. A B. P Q. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 31 / 51 >.
(85) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. SC - DURING. SystemC. Simulated Time in SystemC and SC - DURING f() wait(20). Process A: // computation f(); // time taken by f wait(20, SC_NS);. g() wait(20). Process P: g(); wait(20, SC_NS); during(15, SC_NS, h);. A B. P. h(). Q. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 31 / 51 >.
(86) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. SC - DURING. SystemC. Simulated Time in SystemC and SC - DURING f() wait(20). Process A: // computation f(); // time taken by f wait(20, SC_NS);. g() wait(20). Process P: g(); wait(20, SC_NS); during(15, SC_NS, h);. A B. h(). P Q. i(). Matthieu Moy (Verimag). j(). High-level Models for Embedded Systems. March 13th 2014. < 31 / 51 >.
(87) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. Sketch of Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Create thread 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } A B C. Thread Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 32 / 51 >.
(88) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. Sketch of Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Create thread 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. Thread Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 32 / 51 >.
(89) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. Sketch of Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Create thread 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. 1 create thread. Thread Matthieu Moy (Verimag). f High-level Models for Embedded Systems. March 13th 2014. < 32 / 51 >.
(90) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. Sketch of Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Create thread 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. 1 create thread. Thread Matthieu Moy (Verimag). 2 wait(d). f High-level Models for Embedded Systems. March 13th 2014. < 32 / 51 >.
(91) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. Sketch of Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Create thread 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. 1 create thread. Thread Matthieu Moy (Verimag). 2 wait(d). f High-level Models for Embedded Systems. March 13th 2014. < 32 / 51 >.
(92) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. Sketch of Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Create thread 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. create thread Thread Matthieu Moy (Verimag). 3. 1 2 wait(d). join() f High-level Models for Embedded Systems. March 13th 2014. < 32 / 51 >.
(93) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. Sketch of Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Create thread 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. create thread Thread Matthieu Moy (Verimag). 3. 1 2 wait(d). join() f High-level Models for Embedded Systems. March 13th 2014. < 32 / 51 >.
(94) Introduction. TLM. RTC. SC - DURING :. Abstract Interpretation. Conclusion. Sketch of Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Create thread 1 sc_core::wait(d); // SystemC executes 2 + thread pooling 3 t.join(); // Wait for completion } during(d, f); A B C. 1 create thread. Thread Matthieu Moy (Verimag). + richer 3 synchronization API wait(d) 2 join() f. High-level Models for Embedded Systems. March 13th 2014. < 32 / 51 >.
(95) Introduction. TLM. RTC. Abstract Interpretation. SC - DURING : 14. Speedup. 8. Results. Loosely-Timed Models. 12 10. Conclusion. 6 4. Fine-grain Timing. 2. Number of CPUs in the platform. 0 10. 20. 30. Test machine has 4 × 12 = 48 cores Matthieu Moy (Verimag). High-level Models for Embedded Systems. 40. 50. 60. Swadhin Mangaraj March 13th 2014. < 33 / 51 >.
(96) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 34 / 51 >.
(97) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO Samuel Jones. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 34 / 51 >.
(98) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 34 / 51 >.
(99) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. SystemC and Extra-Functional Solver Cosimulation Power States SystemC Temperature. Matthieu Moy (Verimag). High-level Models for Embedded Systems. Power and Temperature Solver (ATMI, ACEplorer). March 13th 2014. < 35 / 51 >.
(100) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. SystemC and Extra-Functional Solver Cosimulation Power States SystemC Temperature. Claude Helmstetter Matthieu Moy (Verimag). High-level Models for Embedded Systems. Power and Temperature Solver (ATMI, ACEplorer). Tayeb Bouhadiba March 13th 2014. < 35 / 51 >.
(101) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 36 / 51 >.
(102) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Contributions on TLM. Parallelization Compilation Smart FIFO. Timing Formal Verification. Memory Models jTLM. Faithfulness Traffic models. Early Software Execution. Simulation Speed. Optimizing Compiler. Power/Temperature Correctness Matthieu Moy (Verimag). Functional/extra-functional Cosimulation High-level Models for Embedded Systems. March 13th 2014. < 36 / 51 >.
(103) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Outline Real-Time Calculus. Abstract Interpretation. T C/ m e st. LM. Sy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 37 / 51 >.
(104) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Outline Real-Time Calculus. Abstract Interpretation. T C/ m e st. LM. Sy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 37 / 51 >.
(105) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Analysability. Precision Vs Algorithmic Complexity. Real−Time Calculus. Unreachable zone. Analytical Models No states useless zone. Model Checking. States. Detailed Computational Models. Simulation. Expressivity. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 38 / 51 >.
(106) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Analysability. Precision Vs Algorithmic Complexity. Real−Time Calculus. Unreachable zone. Analytical Models No states useless zone. Model Checking. States. Detailed Computational Models. Simulation. Expressivity. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 38 / 51 >.
(107) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Modular Performance Analysis (MPA): The Big Picture [Thiele et al.]. Component1. Component2. output. input. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 39 / 51 >.
(108) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Modular Performance Analysis (MPA): The Big Picture [Thiele et al.]. Component1. Component2. output. input. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 39 / 51 >.
(109) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Modular Performance Analysis (MPA): The Big Picture [Thiele et al.]. Component1. Component2. output. input. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 39 / 51 >.
(110) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Modular Performance Analysis (MPA): The Big Picture [Thiele et al.]. Component1. Component2. ⊗, , ⊗, , .... ⊗, , ⊗, , .... input. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. output. < 39 / 51 >.
(111) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Real-Time Calculus and Arrival Curves. #events. αu. 5. αu (t) / αl (t) : min/max number of events in any window of duration t.. 4 3. αl. 2 1. δt. 0 0. 1. 2. Matthieu Moy (Verimag). 3. 4. 5. High-level Models for Embedded Systems. March 13th 2014. < 40 / 51 >.
(112) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Interfacing with Timed Automata RTC. [Chakraborty et al.]. input: αi. output: αo. Richer Formalism. formal analysis. compilation. Generator. Component. Observer Yanhong Liu. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 41 / 51 >.
(113) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Timed Automata Vs Abstract Interpretation and SMT-Solving Large event counters. Large timing constants. Timed automata (Uppaal). SMT solving. Abstract Interpretation ac2lus: use Lustre tools to analyze MPA components (Nbac = abstract interpretation, Kind = SMT solving) Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 42 / 51 >.
(114) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Causality Problem #events. 7 6 5 4 3 2 1. δt. 0 0. 1. 2. Matthieu Moy (Verimag). 3. 4. 5. 6. 7. 8. 9. 10 11. High-level Models for Embedded Systems. March 13th 2014. < 43 / 51 >.
(115) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Causality Problem #events. 7. αl. 6 5. Deadline 6 pages written. 4 3 2 1. δt. 0 0. 1. 2. Matthieu Moy (Verimag). 3. 4. 5. 6. 7. 8. 9. 10 11. High-level Models for Embedded Systems. March 13th 2014. < 43 / 51 >.
(116) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Causality Problem αu. #events. 7 6. αl. One page per day. 5. Deadline 6 pages written. 4 3 2 1. δt. 0 0. 1. 2. Matthieu Moy (Verimag). 3. 4. 5. 6. 7. 8. 9. 10 11. High-level Models for Embedded Systems. March 13th 2014. < 43 / 51 >.
(117) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Causality Problem αu. #events. 7 6. Week-end αl. One page per day. 5. Deadline 6 pages written. 4 3 2 1. δt. 0 0. 1. 2. Matthieu Moy (Verimag). 3. 4. 5. 6. 7. 8. 9. 10 11. High-level Models for Embedded Systems. March 13th 2014. < 43 / 51 >.
(118) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Causality Problem αu. #events. 7 6. Week-end αl. One page per day. 5. Deadline 6 pages written. 4 3 2 1. δt. 0 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11. Implicit constraint: maximal procrastination = 2 days Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 43 / 51 >.
(119) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. The Causality Problem αu. #events. 7 6. Week-end αl. One page per day. 5. Deadline 6 pages written. 4 3 2 1. δt. 0 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11. Causality closure = compute the implicit constraint automatically Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 43 / 51 >.
(120) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Outline Real-Time Calculus. Abstract Interpretation. T C/ m e st. LM. Sy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 44 / 51 >.
(121) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Outline Real-Time Calculus. Abstract Interpretation. T C/ m e st. LM. Sy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 44 / 51 >.
(122) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation and PAGAI $ pagai -i test.c void f() { int x = 0, y = 1; /* invariant: y = x + 1 y <= 102 y >= 1 */ while (x <= 100) { x++; y++; } } Julien Henry Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 45 / 51 >.
(123) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 46 / 51 >.
(124) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 46 / 51 >.
(125) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 46 / 51 >.
(126) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 46 / 51 >.
(127) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 46 / 51 >.
(128) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. F#. Matthieu Moy (Verimag). High-level Models for Embedded Systems. = join. March 13th 2014. < 46 / 51 >.
(129) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. F#. Matthieu Moy (Verimag). High-level Models for Embedded Systems. = join. March 13th 2014. < 46 / 51 >.
(130) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. F#. Matthieu Moy (Verimag). High-level Models for Embedded Systems. = join. March 13th 2014. < 46 / 51 >.
(131) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. ∇ = widening F#. Matthieu Moy (Verimag). High-level Models for Embedded Systems. = join. March 13th 2014. < 46 / 51 >.
(132) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot]. ∇ = widening F#. = join. SMT formula “is there a feasible path that makes the candidate invariant grow?” Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 46 / 51 >.
(133) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot] Don’t consider if only activated because of ∇. ∇ = widening F#. = join. SMT formula “is there a feasible path that makes the candidate invariant grow?” Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 46 / 51 >.
(134) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Abstract Interpretation with PAGAI [Cousot & Cousot] Don’t consider if only activated because of ∇. ∇ = widening F#. = join. Keep union symbolic SMT formula “is there a feasible path that makes the candidate invariant grow?” Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 46 / 51 >.
(135) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. PAGAI: Results. Name a2ps gawk gnuchess gnugo grep gzip lapack make tar. kLOC 55 59 38 83 35 27 954 34 73. |loops| 2012 902 1222 2801 820 494 16422 993 1712. S 23 15 50 77 41 22 294 67 37. Time (in seconds) G PF C 74 34 115 46 12 40 220 81 312 159 92 766 85 22 65 268 91 303 3740 3773 8159 108 53 109 218 115 253. Improves discovered invariants DIS 162 50 351 1493 122 230 10351 257 396. 18 ( ) uncomparable. 16 percentage of control points. Tested on real programs. 14 12 10 8 6 4 2 0 F +P /G IS D /S F +P G /G F +P G /PF F. /G. /S. +P. G. PF. High-level Models for Embedded Systems. PF. /S G. Matthieu Moy (Verimag). March 13th 2014. < 47 / 51 >.
(136) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Outline Real-Time Calculus. Abstract Interpretation. M. TL C/. m. te ys. S. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 48 / 51 >.
(137) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Outline Real-Time Calculus. Abstract Interpretation. M. TL C/. m. te ys. S. Time to conclude.... Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 48 / 51 >.
(138) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Summary Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Issue 1: Functional Correctness. Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Introduction. TLM. Issue 2: Early Software Development Traditional Design-Flow. Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Synthesis. Synthesis. RTC. Abstract Interpretation. Conclusion. Issue 3: Timing. Model. Time. Software Development Integration Factory. Factory. Software Development. Validation. gain. Integration. Validation. Matthieu Moy (Verimag) Introduction. TLM. March 13th 2014. High-level Models for Embedded Systems RTC. Abstract Interpretation. < 7 / 51 > Conclusion. Issue 4: Power and Temperature. Matthieu Moy (Verimag) Introduction. TLM. High-level Models for Embedded Systems RTC. March 13th 2014. Abstract Interpretation. < 8 / 51 > Conclusion. Issue 5: Simulation speed. Matthieu Moy (Verimag) Introduction. TLM. High-level Models for Embedded Systems RTC. actual Unmodeled behaviors (B). 20 watt Extra behaviors of the model (A). 50-130 watt. Matthieu Moy (Verimag). < 9 / 51 > Conclusion. Issue 6: Model Faithfulness model. < 1 watt. March 13th 2014. Abstract Interpretation. Exactly modeled behaviors (C). 20-30 watt. High-level Models for Embedded Systems. Matthieu Moy (Verimag). March 13th 2014. < 10 / 51 >. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 11 / 51 >. High-level Models for Embedded Systems. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. March 13th 2014. < 12 / 51 >. < 49 / 51 >.
(139) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Scientific Production Software Pinapa, PinaVM, PAGAI, LIBTLMPWT, SC - DURING , ac2lus, ... Papers 15 international conferences, 9 workshops, 1 book chapter, 1 journal. Trained students Completed: 1 Ph.D, 5 research master, 6 post-docs, 20 short internships Ongoing: 2 Ph.D, 2 research master, 3 short internships Ensimag course on SystemC/TLM. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 50 / 51 >.
(140) Condition for Success of a Lab/Industry Cooperation. (Slide from Laurent Maillet-Contoz). Suitable environment: • Shared motivation • Understanding and respect of each party’s constraints • Legal framework • Bonus: geographic proximity.
(141) Condition for Success of a Lab/Industry Cooperation. A common ground • Scientific context • Applicative context. (Slide from Laurent Maillet-Contoz). Suitable environment: • Shared motivation • Understanding and respect of each party’s constraints • Legal framework • Bonus: geographic proximity.
(142) Condition for Success of a Lab/Industry Cooperation. A common ground • Scientific context • Applicative context. A research subject covering shared interests (Slide from Laurent Maillet-Contoz). Suitable environment: • Shared motivation • Understanding and respect of each party’s constraints • Legal framework • Bonus: geographic proximity.
(143) Condition for Success of a Lab/Industry Cooperation. Periodic exchanges and in-depth discussions In the long-term. A research subject covering shared interests (Slide from Laurent Maillet-Contoz). A common ground • Scientific context • Applicative context Suitable environment: • Shared motivation • Understanding and respect of each party’s constraints • Legal framework • Bonus: geographic proximity.
(144) Condition for Success of a Lab/Industry Cooperation. Periodic exchanges and in-depth discussions In the long-term. A research subject covering shared interests (Slide from Laurent Maillet-Contoz). Concrete works to progress at each party’s own rythm and enrich the landscape (not everything will succeed). A common ground • Scientific context • Applicative context Suitable environment: • Shared motivation • Understanding and respect of each party’s constraints • Legal framework • Bonus: geographic proximity.
(145) Condition for Success of a Lab/Industry Cooperation Elements of solution that enrich both parties Next cooperation theme. Periodic exchanges and in-depth discussions In the long-term. A research subject covering shared interests (Slide from Laurent Maillet-Contoz). Concrete works to progress at each party’s own rythm and enrich the landscape (not everything will succeed). A common ground • Scientific context • Applicative context Suitable environment: • Shared motivation • Understanding and respect of each party’s constraints • Legal framework • Bonus: geographic proximity.
(146) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Prospects Real-Time Calculus. Abstract Interpretation. LM. T C/. m te. s Sy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 51 / 51 >.
(147) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Prospects Real-Time Calculus. Abstract Interpretation Critical Systems. LM. T C/. m te. s Sy. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 51 / 51 >.
(148) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Questions? Real-Time Calculus. Abstract Interpretation Critical Systems. LM. T C/. m te. s Sy. Thank Matthieu Moy (Verimag). You! High-level Models for Embedded Systems. March 13th 2014. < 51 / 51 >.
(149) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Supervised/Co-supervised Ph.D. Giovanni Funchal 2007 → 2011 CIFRE STMicroelectronics co-supervised with Florence Maraninchi Julien Henry 2011 → present co-supervised with David Monniaux Swadhin Mangaraj 2013 → present OpenES european project. Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 51 / 51 >.
(150) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Sources http://en.wikipedia.org/wiki/File:Diopsis.jpg (Peter John Bishop, CC Attribution-Share Alike 3.0 Unported). http://www.fotopedia.com/items/flickr-367843750 (oskay@fotopedia, CC Attribution 2.0 Generic). http://www.flickr.com/photos/artbystevejohnson/4654013143/ (Steve Johnson, CC Attribution 2.0 Generic). http://xkcd.com/612/ (Randall Munroe, CC Attribution 2.0 Generic). http://uk.wikipedia.org/wiki/%D0%A4%D0%B0%D0%B9%D0%BB:Soldering_iron_%28UK_Plug%29. jpg (oomlout, CC Attribution Share-Alike 2.0 Generic). Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 51 / 51 >.
(151) Introduction. TLM. RTC. Abstract Interpretation. Conclusion. Sources http://commons.wikimedia.org/wiki/File:Intel_Core_I7-920_Boxed_-_15.JPG (Alan Lorenzo, CC Attribution-Share Alike 3.0 Unported). http://commons.wikimedia.org/wiki/File:Choc_cake_ill_01.svg (Kilom691, CC Attribution-Share Alike 3.0 Unported). http://en.wikipedia.org/wiki/File:Singapore_Airlines_A380_9V-SKH.jpg (Simon_sees, CC Attribution 2.0 Generic). http://opensource.org/logo-usage-guidelines (OSI, Creative Commons Attribution 3.0 License). + Open Clip Art public domain pictures Matthieu Moy (Verimag). High-level Models for Embedded Systems. March 13th 2014. < 51 / 51 >.
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