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Intel Corporation is a leading supplier of microcomputer components, modules and systems. When Intel invented the microprocessor in 1971, it created the era of the microcomputer. Today, Intel architectures are considered world standards. Whether used in embedded applications such as automobiles, printers and microwave ovens, or as the CPU in personal computers, client

seNers or supercomputers, Intel delivers leading-edge technology.

8-BIT EMBEDDED CONTROLLER HANDBOOK

1991

About Our Cover.' Thinkers, inventors, and artists throughout history have breathed life into their ideas by converting them into rough working sketches, models,

and products. This series of covers shows a few of these creations, along with the applications and products created by Intel customers.

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice.

Contact your local sales office to obtain the latest specifications before placing your order.

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287, 376, 386, 387, 486, 4-SITE, Above, ACE51 , ACE96, ACE186, ACE196, ACE960, ActionMedia, BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX, FaxBACK, Genius, i, t, i486, i750, i860, ICE, iCEL, ICEVIEW, iCS, iDBP, iDIS, 1²1CE, iLBX, iMDDX, iMMX, Inboard, Insite, Intel, intel, Intel386, intelBOS, Intel Certified, Intelevision, inteligent Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, Library Manager, MAPNET, MCS, Megachassis, MICROMAINFRAME, MULTICHANNEL, MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, Pr0750, PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse Programming, READY LAN, RMX/80, RUPI, Seamless, SLD, SugarCube', SX, ToolTALK, UPI, VAPl,Visual Edge, VLSiCEL, and ZapCode, and the combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a numerical suffix.

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©INTEL CORPORATION 1990

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After a customer purchases any system hardware or software product, service and support become major factors in determining whether that product will continue to meet a customer's expectations. Such support requires an international support organization and a breadth of programs to meet a variety of customer needs.

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Today's broad spectrum of powerful networking capabilities are only as good as the customer support provided by the vendor. Intel offers network services and support structured to meet a wide variety of end-user comput- ing needs. From a ground up design of your network's physical and logical design to implementation, installa- tion and network wide maintenance. From software products to turn-key system solutions; Intel offers the customer a complete networked solution. With over 10 years of network experience in both the commercial and Government arena; network products, services and support from Intel provide you the most optimized network offering in the industry.

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MCS® .. 48 Single Component System

MCS® .. 48 Expanded System

MCS® .. 48 Instruction Set

MCS® .. 48 Data Sheets MCS® .. 51 Architectural Overview

MCS® .. 51 Programmer's Guide and Instruction Set

MCS® .. 51 Hardware

Description and Data Sheets 8XC51FX Hardware

Description and Data Sheets 8XF 51FC Hardware

Description and Data Sheets

83C152 Hardware

Description and Data Sheets UPI .. 452 CHMOS

. Programmable 110 Processor MCS® .. 51 Development Support Tools

RUPITM .. 44 Family RUPITM Development Support Tools

MCS® .. 80/85 Family

Table of Contents

Alphanumeric Index ... . MCS®-48 FAMILY

Chapter 1

MCS®-48 Single Component System ... . Chapter 2

. MCS®-48 Expanded System ... . Chapter 3

MCS®-48 Instruction Set ... . Chapter 4

MCS®-48 DATA SHEETS

8243 MCS-48 Input/Output Expander ... . P87 48H/P87 49H/8048AH/8035AHLl8049AH/8039AHLl8050AH/8040AH L

HMOS Single Component 8-Bit Microcontroller ... . D8748H/D8749H HMOS-E Single-Component 8-Bit Microcomputer ... . P8049KB HMOS Single-Component 8-Bit Microcontroller ... . MCS-48 Express ... . MCS®-51 FAMILY

Chapter 5

MCS-51 Family of Microcontrollers Architectural Overview ... . Chapter 6

MCS-51 Programmer's Guide and Instruction Set ... . Chapter 7

8051, 8052 and 80C51 Hardware Description ... . 8XC52/54/58 Hardware Description ... . DATA SHEETS

MCS-51 8-Bit Control-Oriented Microcomputers 8031/8051/8031 AH/8051 AHI 8032AH/8052AH/8751 H/8751 H-8 ... . 8051 AHP MCS-51 Family 8-Bit Control-Oriented Microcontroller with Protected

ROM ... . 8031 AH/8051AH/8032AH/8052AH/8751 H/8751 H-8 Express ... . 8751 BH Single-Chip 8-Bit Microcomputer with 4K Bytes of EPROM Program

Memory ... . 8751 BH Express ... . 8752BH Single-Chip 8-Bit Microcomputer with 8K Bytes of EPROM Program

Memory ... . 8752BH Express ... . 8051 KB/8052KB MCS-51 Family 8-Bit Microcontroller ... . 80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcomputer ... . 80C31 BH/80C51 BH Express ... . 80C51 BHP CHMOS Single-Chip 8-Bit Microcomputer with Protected ROM ... . 87C51 187C51-1 187C51-2 CHMOS Single-Chip 8-Bit Microcontroller with 4K Bytes

of EPROM Program Memory ... . 87C51 Express ... , ... . 80C52/80C32 CHMOS Single-Chip 8-Bit Microcomputer ... . 80C52/80C32 Express ... . 87C54/80C54 CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes User

Programmable EPROM ... . 87C54/80C54 Express ... . 87C58/80C58 CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes User

Programmable EPROM ... ~ ... . 87C58/80C58 Express ... .

xi

xiv

1-1 2-1 3-1

4-1 4-8 4-21 4-33 4-45

5-1 6-1 7-1' 7-38

7-48 7-62 7-72 7-74 7-86 7-88 7-100 7-102 7-114 7-130 7-132 7-146 7-160 7-163 7-176 7-178 7-193 7-195 7-212

Table of Contents

Chapter 8

8XC51 FX Hardware Description. . . 8-1 8XC51GB Hardware Description... ... ... ... 8-44 DATA SHEETS

83C51 FAl80C51 FA CHMOS Single-Chip 8-Bit Microcontroller ... ... 8-104 83C51 FAl80C51 FA Express.. ... ... ... 8-118 87C51 FA CHMOS Single-Chip 8-Bit Microcontroller 8K Byte User Programmable

EPROM ... '. . . . .. 8-120 87C51FAExpress ... 8-136 83C51 FB CH MOS Single-Chip 8-Bit Microcontroller ... 8-139 87C51 FB CHMOS Single-Chip 8-Bit Microcontroller ... ;. 8-152 87C51FB Express ... 8-168 87C51 FC/83C51 FC CHMOS Single-Chip 8-Bit Microcontroller 32K Bytes User

Programmable EPROM... .. ... 8-171 87C51 FC/83C51FC Express ... 8-186 87C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller ... . . . .. 8-188 87C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller Express. . . . .. 8-209 UCS51 ASIC Family of Enhanced 8-Bit Microcontrollers with User-Selectable

Peripheral Set and ROM/RAM Configurations ... 8-210 EV80C51 FB Evaluation Board Fact Sheet. . . .. 8-217 EV80C51 FC Evaluation Board Fact Sheet. . . .. 8-219 Chapter 9

8XF51 FC Hardware Description. . . 9-1 DATA SHEETS

88F51 FC CHMOS Single-Chip 8-Bit Microcontroller 32 Kbytes User Programmable Flash Memory .. . . 9-54 88F51 FC CHMOS Single-Chip 8-Bit Microcontroller 32 Kbytes User Programmable

Flash Memory Express... ... ... 9-75 Chapter 10

83C152 Hardware Description ... . . . 10-1 DATA SHEETS

8XC152JAI JB/ JC/ JD Universal Communication Controller 8-Bit Microcontroller .. 10-71 8XC152JAI JB/ JC/ JD Universal Communication Controller 8-Bit Microcomputer

Express. . . .. 1 0-88 Chapter 11

UPI-452 CHMOS Programmable I/O Processor. . . 11-1 Chapter 12

MCS®-51 DEVELOPMENT SUPPORT TOOLS

. 8051 Software Packages. . . 12-1 AEDIT Source Code and Text Editor... ... ... ... 12-4 ICE-51 fPC In-Circuit Emulator. . . .. . . .. . . 12-6 ICE-51 00/252 In-Circuit Emulator ... . . . ... 12-11 ICE-51 00/452 In-Circuit Emulator ... 12-15

THE

FAMilY

Chapter 13

The RUPI-44 Family: Microcontroller with On-Chip Communication Controller . . . 13-1 8044 Architecture . . . 13-9 The RUPI-44 Serial Interface Unit ... 13-19 8044 Application Examples. . . .. . . .. 13-57 8044 DATA SHEET

8044AH/8344AH/8744AH High Performance 8-Bit Microcontroller with On-Chip

Serial Communication Controller ... 13-131

xii

Table of Contents

Chapter 14

RUPITM DEVELOPMENT SUPPORT TOOLS

ICE-51 001044 In-Circuit Emulator ... :.. 14-1 MCS®·80/85 FAMILY

Chapter 15

80/85 DATA SHEETS

8080Al8080A-1/8080A-2 8-Bit N-Channel Microprocessor. . . 15-1 8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors ... ,... 15-11 8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with 1/0 Ports and

Timer ... -... ... ... 15-31 8185/8185-21024 x 8-Bit Static RAM for MCS-85 ... , 15-45 8224 Clock Generator and Driver for 8080A CPU . . . .. 15-50 8228 System Controller and Bus Driver for 8080A CPU. . . .. 15-55 8755A 16,384-Bit EPROM with 1/0... 15-59

xiii

Alphanumeric Index

8031AH/8051AH/8032AH/8052AH/8751 H/8751 H-8 Express... 7-72 8044 Application Examples ... 13-57 8044 Architecture ... '.' . . . 13-9 8044AH/8344AH/8744AH High Performance 8-Bit Microcontroller with On-Chip Serial

Communication Controller ... 13-131 8051 Software Packages ... 12-1 8051,8052 and 80C51 Hardware Description. . . 7-1 8051AHP MCS-51 Family 8-Bit Control-Oriented Microcontroller with Protected ROM... 7-62 8051 KB/8052KB MCS-51 Family 8-Bit Microcontroller... ... 7-102 8080Al8080A-1 18080A-2 8"Bit N-Channel Microprocessor. . . 15-1 8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . .. 15-11 80C31BH/80C51BH Express ... 7-130 80C51 BHP CHMOS Single-Chip 8-Bit Microcomputer with Protected ROM ... 7-132 80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcomputer. . . .. 7-114 80C52/80C32 CHMOS Single-Chip 8-Bit Microcomputer... 7-163 80C52/80C32 Express... ... ... 7-176 8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer .. 15-31 8185/8185-2 1024 x 8-Bit Static RAM for MCS-85. . . .. 15-45 8224 Clock Generator and Driver for 8080A CPU. . . .. 15-50 8228 System Controller and Bus Driver for 8080A CPU ... . 15-55 8243 MCS-48 Input/Output Expander ... . . . 4-1 83C152 Hardware Description ... '. . . . 10-1 83C51 FAl80C51 FA CHMOS Single-Chip 8-Bit Microcontroller... ... 8-104 83C51FAl80C51 FA Express ... 8-118 83C51 FB CH MOS Single-Chip 8-Bit Microcontroller . . . .. 8-139 8751 BH Express. . . .. . . .. . . .. . . 7-86 8751 BH Single-Chip 8-Bit Microcomputer with 4K Bytes of EPROM Program Memory. . . 7-74 8752BH Express ... ,. ... 7-100 8752BH Single-Chip 8-Bit Microcomputer with 8K Bytes of EPROM Program Memory. . . 7 -88 8755A 16,384-Bit EPROM with I/O. . . .. 15-59 87C51 Express ... 7-160 87C51 187C51-1 187C51-2 CHMOS Single-Chip 8-Bit Microcontroller with 4K Bytes of

EPROM Program Memory .... ~... ... 7-146 87C51 FA CHMOS Single-Chip 8-Bit Microcontroller 8K Byte User Programmable EPROM. 8-120 87C51FA Express ... 8-136 87C51 FB CHMOS Single-Chip 8-Bit Microcontroller . . . .. 8-152 87C51FB Express ... 8-168 87C51FC/83C51 FC CHMOS Single-Chip 8-Bit Microcontroller 32K Bytes User

Programmable EPROM. . . .. 8-171 87C51 FC/83C51 FC Express. . . .. . . .. 8-186 87C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller Express ... 8-209 87C51GB/80C51GB CHMOSSingle-Chip 8-Bit Microcontroller ... 8-188 87C54/80C54 CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes User

Programmable EPROM... ... 7-178 87C54/80C54 Express... ... 7-193 87C58/80C58 CHMOS Single-Chip 8-Bit Microcontro/ler with 32 Kbytes User

Programmable EPROM ... 7-195 87C58/80C58 Express... 7-212 88F51 FC CHMOS Single-Chip 8-Bit Microcontroller 32 Kbytes User Programmable Flash

Memory Express. . . 9-75 88F51 FC CHMOS Single-Chip 8-Bit Microcontroller 32 Kbytes User Programmable Flash

Memory ... 9-54 8XC152JAlJB/JC/JD Universal Communication Controller 8-Bit Microcontroller ... 10-71 8XC152JAlJB/JC/JD Universal Communication Controller 8-Bit Microcomputer Express. 10-88

xiv

Alphanumeric Index

8XC51 FX Hardware Description ... . 8XC51 GB Hardware Description ... . 8XC52/54/58 Hardware Description ... . 8XF51 FC Hardware Description ... . AEDIT Source Code and Text Editor ... . D8748H/D8749H HMOS-E Single-Component 8-Bit Microcomputer ... . EV80C51 FB Evaluation Board Fact Sheet ... . EV80C51 FC Evaluation Board Fact Sheet ... . ICE-51 001044 In-Circuit Emulator ... . ICE-5100/252 In-Circuit Emulator ... . ICE-51 00/452 In-Circuit Emulator ... . ICE-51 IPC In-Circuit Emulator ... . MCS-48 Express ... . MCS-51 8-Bit Control-Oriented Microcomputers 8031/8051/8031 AH/8051 AH/8032AHI

8052AH/8751 H/8751 H-8 ... . MCS-51 Family of Microcontrollers Architectural Overview ... . MCS-51 Programmer's Guide and Instruction Set ... . MCS®-48 Expanded System ... . MCS®-48 Instruction Set ... . MCS®-48 Single Component System ... . P8049KB HMOS Single-Component 8-Bit Microcontroller ... . P8748H/P8749H/8048AH/8035AHLl8049AH/8039AHL/8050AH/8040AHL HMOS

Single Component 8-Bit Microcontroller ... . The RUPI-44 Family: Microcontroller with On-Chip Communication Controller ... . The RUPI-44 Serial Interface Unit ... . UCS51 ASIC Family of Enhanced 8-Bit Microcontrollers with User-Selectable Peripheral

Set and ROM/RAM Configurations ... . UPI-452 CHMOS Programmable 1/0 Processor ... .

xv

8-1 8-44 7-38 9-1 12-4 4-21 8-217 8-219 14-1 12-11 12-15

12-6 4-45 7-48 5-1 6-1 2-1 3-1 1-1 4-33 4-8 13-1 13-19 8-210 11-1

MCS® ... 48 Single Component 1

System

THE SINGLE COMPONENT MCS®-48 SYSTEM

1.0 INTRODUCTION

Sections 2 through 5 describe in detail the func- tional characteristics of the S74SH and S749H EPROM, S04SAH/S049AH/SOSOAH ROM, and S03SAHLI S039AHLlS040-AHL CPU only single component micro- computers. Unless otherwise noted, details within these sections apply to all versions. This chapter is limited to those functions useful in single-chip implementations of the MCS®-4S. The Chapter on the Expanded MCS®-48 System discusses functions which allow expansion of program memory, data memory, and input output capa- bility.

2.0 ARCHITECTURE

The following sections break the MCS-4S Family into functional blocks and describe each in detail. The follow- ing description will use the S04SAH as the representative product for the family. See Figure 1.

2.1 Arithmetic Section

The arithmetic section of the processor contains the basic data manipulation functions of the S04SAH and can be divided into the following blocks:

• Arithmetic Logic Unit (ALU)

• Accumulator

• Carry Flag

• Instruction Decoder

In a typical operation data stored in the accumulator is combined in the ALU with data from another source on the internal bus (such as a register or 110 port) and the result is stored in the accumulator or another register.

The following is more detailed description of the function of each block.

INSTRUCTION DECODER

The operation code (op code) portion of each program instruction is stored in the Instruction Decoder and con- verted to outputs which control the function of each of the blocks of the Arithmetic Section. These lines control the source of data and the destination register as well as the function performed in the ALU.

ARITHMETIC LOGIC UNIT

The ALU accepts S-bit data words from one or two sources and generates an S-bit result under control of the Instruc- tion Decoder. The ALU can perform the following functions:

1-1

• Add With or Without Carry

• AND, OR, Exclusive OR

• IncremenUDecrement

• Bit Complement

• Rotate Left, Right

• Swap Nibbles

• BCD Decimal Adjust

If the operation performed by the ALU results in a value represented by more than S bits (overflow of most sig- nificant bit), a Carry Flag is set in the Program Status Word.

ACCUMULATOR

The accumulator is the single most important data register in the processor, being one of the sources of input to the ALU and often the destination of the result of operations performed in the ALU. Data to and from 110 ports and memory also normally passes through the accumulator.

2.2 Program Memory

Resident program memory consists of 1024, 2048, or 4096 words eight bits wide which are addressed by the program counter. In the S74SH and the S749H this memory is user programmable and erasable EPROM; in the S04SAHI S049AH/SOSOAH the memory is ROM which is mask programmable at the factory. The S03SAHLlS039AHLI 8040AHL has no internal program memory and is used with external memory devices. Program code is com- pletely interchangeable among the various versions. To access the upper 2K of program memory in the SOSOAH, and other MCS-4S devices, a select memory bank and a JUMP or CALL instruction must be executed to cross the 2K boundary.

There are three locations in Program Memory of special importance as shown in Figure 2.

LOCATION 0

Activating the Reset line of the processor causes the first instruction to be fetched from 10cationO.

LOCATION 3

Activating the Interrupt input line of the processor (if interrupt is enabled) causes a jump to subroutine at lo- cation 3.

LOCATION 7

A timer/counter interrupt resulting from timer counter overflow (if enabled) causes a jump to subroutine at loca- tion 7.

Therefore, the first instruction to be executed after ini- tialization is stored in location 0, the first word of an external interrupt service subroutine is stored in location 3. and the first word of a timer/counter service routines

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o 7 1 6 1 5 1 4 1 31 2 11 1 0 -RESET VECTORS

ADDRESS PROGRAM HERE

Figure 2. Program Memory Map 2.3 Data Memory

Resident data memory is organized as 64, 128, or 256 by 8-bits wide in the 8048AH, 8049AH and 8050AH. All locations are indirectly addressable through either of two RAM Pointer Registers which reside at address 0 and I of the register array. In addition, as shown in Figure 3, the first 8 locations (0-7) of the array are designated as working registers and are directly addressable by several instructions. Since these registers are more easily ad- dressed, they are usually used to store frequently accessed intermediate results. The DJNZ instruction makes very efficient use of the working registers as program loop counters by allowing the programmer to decrement and test the register in a single instruction.

By executing a Register Bank Switch instruction (SEL RB) RAM locations 24-31 are designated as the working

1-3

registers in place of locations 0-7 and arc then directly addressable. Th,is second bank of working registers may be used as an extension of the first bank or reserved for use during interrupt service subroutines allowing the reg- isters of Bank 0 used in the main program to be instantly

"saved" by a Bank Switch. Note that if this second bank is not used, locations 24-31 are still addressable as general purpose RAM. Since the two RAM pointer Registers RO and R I are a part of the working register array, bank switching effectively creates two more pointer registers (ROland RII) which can be used with RO and Rl to easily access up to four separate working areas in RAM at one time. RAM locations (8-23) also serve a dual role in that they contain the program counter stack as explained in Section 2.6. These locations are addressed by the Stack Pointer during subroutine calls as well as by RAM Pointer Registers RO and R I. If the level of subroutine nesting is less than 8, all stack registers are not required and can be used as general purpose RAM locations. Each level of subroutine nesting not used provides the user with two additional RAM locations.

63 (127)

«255))

USER RAM 32" B (96" B)

«224" B)) 32

31 BANK 1

I

WORKING DIRECTLY

REGISTERS ADDRESSABLE B"B WHEN BANK 1 - - - R l ' - - - - IS SELECTED 24 -- --AO' - - - -

. I

23

8 LEVEL STACK ADDRESSED

OR INDIRECTLY

USER RAM THROUGH

16" B R1 OR RO

(RO' OR R1') B

7 _WORKING BANKO

I

DIRECTLY REGISTERS ADDRESSABLE

8"B WHEN BANK 0 - - - R 1 - - - - IS SELECTE1D

---

0

IN ADDITION RO OR R1 (RO' OR R1')

MAY BE USED TO ADDRESS 256 ( ) B049AH, B749H, WORDS OF EXTERNAL RAM, « )) B050AH

Figure 3. Data Memory Map

SINGLE COMPONENT MCS®-48 SYSTEM

VCC VCC

INTERNAL ^Q

BUS D

D FLIP FLOP

LOW IMPEDANCE PULLDOWN CLK ^Q

WRITE

PULSE

-=-

IN

MAX -500 -400

10H -300 _ _ _ _ (MAl -200

4V OV

1/0 PIN PORTl

AND2

2V VOL

4V

LOW IMPEDANCE PULLUP HIGH IMPEDANCE PULLUP LOW IMPEDANCE PULLDOWN

These graphs are for informational purposes only and are not guaranteed minimums or maximums.

Figure 4. "Quasi-bidirectional" Port Structure

1-4

SINGLE COMPONENT MCS®-48 SYSTEM

2.4 Input/Output

The 8048AH has 27 lines which can be used for input or output functions. These lines are grouped as 3 ports of 8 lines each which serve as either inputs, outputs or bidi- rectional ports and 3 "test" inputs which can alter pro- gram sequences when tested by conditional jump instructions.

PORTS 1 AND 2

Ports I and 2 are each 8 bits wide and have identical characteristics. Data written to these ports is statically latched and remains unchanged until'rewritten. As input ports these lines are non-latching, i.e., inputs must be present until read by an input instruction. Inputs are fully TTL compatible and outputs will drive one standard TTL load.

The lines of ports I and 2 are called quasi-bidirectional because of a special output circuit structure which allows each line to serve as an input, and output, or both even though outputs are statically latched. Figure 4 shows the circuit configuration in detail. Each line is continu- ously pulled up to V CC through a resistive device of relatively high impedance.

This pullup is sufficient to provide the source current for a TTL high level yet can be pulled low by a standard TTL gate thus allowing the same pin to be used for both input and output. To provide fast switching times in a "0" to

"I" transition a relatively low impedance device is switched in momentarily (= 115 of a machine cycle) when- ever a "I" is written to the line. When a "0" is written to the line a low impedance device overcomes the light pullup and provides TTL current sinking capability. Since the pulldown transistor is a low impedance device a " I "

must first be written to any line which is to be used as an input. Reset initializes all lines to the high impedance' 'I "

state.

It is important to note that the ORL and the ANL are read!

write operations. When executed, the f,LC "reads" the port, modifies the data according to the instruction, then

"writes" the data back to the port. The "writing" (es- sentially an OUTL instruction) enables the low impedance pull-up momentarily again even if the data was unchanged from a "I." This specifically applies to configurations that have inputs and outputs mixed together on the same port. See also section 8 in the Expanded MCS-48 System chapter.

BUS

Bus is also an 8-bit port which is a true bidirectional port with associated input and output strobes. If the bidirec- tional feature is not needed, Bus can serve as either a

1-5

statically latched output port or non-latching input port.

Input and output lines on this port cannot be mixed however.

As a static port, data is written and latched using the OUTL instruction and inputted using the INS instruction. The INS and OUTL instructions generate pulses on the cor- responding RD and WR output strobe lines; however, in the static port mode they are generally not used. As a bidirectional port the MOVX instructions are used to read and write the port. A write to the port generates a pulse on the WR out~ line and output data is valid at the trailing edge of WR. A read of the port generates a pulse on the RD output line and input data must be valid at the trailing edge of RD. When not being written or read, the BUS lines are in a high impedance state. See also sections 7 and 8 in the Expanded MCS-48 System chapter.

2.5 Test and INT Inputs

Three pins serve as inputs and are testable with the con- ditional jump instruction. These are TO, TI, and INT.

These pins allow inputs to cause program branches without the necessity to load an input port into the accumulator, The TO, TI, and INT pins have other possible functions as well. See the pin description in Section 3.

2.6 Program Counter and Stack

The Program Counter is an independent counter while the Program Counter Stack is implemented suing pairs of reg- isters in the Data Memory Array. Only 10, II, or 12 bits of the Program Counter are used to address the 1024, 2048, or 4096 words of on-board program memory of the 8048AH, 8049AH, or 80S0AH, while the most significant bits can be used for external Program Memory fetches.

See Figure 5. The Program Counter is initialized to zero by activating the Reset line.

1~IAWI~I~I~I~I~I~I~I~I~I~1

I

I I

Conventional Program Counter

• Counts OOOH to 7FFH

• Overflows 7FFH to OOOH

Figure 5. Program Counter

An interrupt or CALL to a subroutine causes the contents of the program counter to be stored in one of the 8 register pairs of the Program Counter Stack as shown in Figure 6. The pair to be used is determined by a 3-bit Stack Pointer which is part of the Program Status Word (PSW).

SINGLE COMPONENT MCS®-48 SYSTEM

POIN 111

TER R23

the word. The Program Status Word is actiIally a collection of flip-flops throughout the machine which can be read or written as a whole. The ability to write to PSW allows for easy restoration of machine stalUs after a power down

22 sequence.

110

101

100

011

010

001

000

--"-

·

--"-

· :

-; ·

· ·

•

psw PCS-ll

PC4-7 PCO-3

MSB LSB

Figure 6. Program Counter Stack

21 20 19 18 .17 16 15 14 13 12 11 10 9 RS

Data RAM locations 8-23 are available as stack registers and are used to store the Program. Counter and 4 bits of PSW as shown in Figure 6. The Stack Pointer .when initialized to 000 points to RAM locations 8 and 9. The first subroutine jump or interrupt results in the program counter contents being transferred to locations 8 and 9 of the RAM array. The stack pointer is then incremented by one to point to locations 10 and 11 in anticipation of another CALL. Nesting of subroutines wihtin subroutines can continue up to 8 times without overflowing the stack.

If overflow does occur the deepest address stored (loca- tions 8 and 9) will be overwritten and lost since the stack . pointer overflows from III to 000. It also underflows from

000 to 111.

The end of a subroutine, which is signalled by a return instruction (RET or RETR), causes the Stack Pointer to be decremented and the contents of the reSUlting r~gister pair to be transferred to the Program Counter.

2.7 Program Status Word

An 8-bit status word which can be loaded to and from the accumulator exists called the Program Status Word (PSW). Figure 7 shows the information available in

1-6

MSB

SAVED IN STACK I

STACK POINTER

,

CY CARRY

AC AUXILIARY CARRY FO FLAG 0

BS REGISTER BANK SELECT

So

LSB

Figure 7. Program Status Word (PSW) The upper four bits of PSW are stored in the Program Counter Stack with every call to subroutine or interrupt vector and .are optionally restored upon return with the RETR instruction. The RET return instruction does not update PSW.

The PSW bit definitions are as follows:

Bits 0:-2: Stack Pointer bits (So' SI, S2) Bit 3:

Bit 4:

Bit 5:

Bit 6:

Bit 7:

Not used (" 1" level when read) Working Register Bank Switch Bit (BS) a Bank a

1 = Bank 1

Flag a bit . (Fa) user controlled flag which can be complemented or cleared, and tested with the conditional jump instruction JFO.

Auxiliary Carry (AC) carry bit generated by an ADD instruction and used by the decimal adjust instruction DAA .

Carry (CY) carry flag which indicates that the previous operation has resulted in overflow of the accumulator.

2.8 Conditional Branch Logic

The conditional branch logic within the processsor enables several conditions internal and external to the processor to be tested by the users program. By using the conditional jump instruction the conditions that are listed in Table I can effect a change in the sequence of the program execution.

SINGLE COMPONENT MCS®-48 SYSTEM

Table 1

Jump Conditions Device Testable (Jum On)

not all

Accumulator All zeros zeros

Accumulator Bit - I

Carry Flag 0 I

User Flags (FO. FI) - I

Timer Overflow Flag

-

Test Inputs (TO • ...!.!) 0 I

Interrupt Input (lNT) 0 -

2.9 Interrupt

An interrupt sequenc~ is initiated by applying a low "0"

level input to the INT pin. Interrupt is level triggered and active low to allow "WIRE ORing" of several interrupt sources at the input pin. Figure 8 shows the interrupt logic of the 8048AH. The Interrupt line is sampled every instruction cycle and when detected causes a "call to subroutine" at location 3 in program memory as soon as all cycles of the current instruction are complete. On 2- cycle instructions the interrupt line is sampled on the 2nd cycle only. INT must be held low for at least 3 machine cycles to ensure proper interrupt operations. As in any CALL to subroutine. the Program Counter and Program Status word are saved in the stack. For a description of this operation see the previous section. Program Counter and Stack. Program Memory location 3 usually contains an unconditional jump to an interrupt service subroutine elsewhere in program memory. The end of an interrupt service subroutine is signalled by the execution of a Return and Restore Status instruction RETR. The interrupt system is single level in that once an interrupt is detected all further interrupt requests are ignored until execution of an RETR reenables the interrupt input logic. This occurs at the beginning of the second cycle ofthe RETR instruction.

This sequence holds true also for an internal interrupt generated by timer overflow. If an internal timer/counter generated interrupt and an external interrupt are detected at the same time. the external source will be recognized.

See the following Timer/Counter section for a ·descriptkm of timer interrupt. If needed. a second external interrupt can be created by enabling the timer/counter interrupt.

loading FFH in the Counter (ones less than terminal count). and enabling the event counter mode. A "I" to

"0" transition on the T! input will then cause an interrupt vector to location 7.

INTERRUPT TIMING

The interrupt input may be enabled or disabled under Program Control using the EN I and DIS I instructions.

Interrupts are disabled by Reset and remain so until en-

abled by the users program. An interrupt request must be removed before the RETR instruction is executed upon return from the service routine otherwise the processor will re-enter the service routine immediately. Many pe- ripheral devices prevent this situation by resetting their interrupt request line whenever the processor accesses (Reads or Writes) the peripherals data buffer register. If the interrupting device does not require access by the processor. 'one output line of the 8048AH may be des- ignated as an "interrupt acknowledge" which is activated by the service subroutine to reset the interrupt request.

The INT pin may also be tested using the conditional jump instruction IN!. This instruction may be used to detect the' presence of a pending interrupt before interrupts are en- abled. If interrupt is left disabled. INT may be used as another test input like TO and T! .

2.10 Timer/Counter

The 8048AH contains a counter to aid the user in counting external events and generating accurate time delays with- out placing a burden on the processor for these functions.

In both modes the counter operation is the same. the only difference being the source of the input to the counter.

The timer/event counter is shown in Figure 9.

COUNTER

The 8-bit binary counter is presettable and readable with two MOY instructions which transfer the contents of the accumulator to the counter and vice versa. The counter content may be affected by Reset and should be initialized by software. The counter is stopped by a Reset or STOP TCNT instruction and remains stopped until started as a timer by a START T instruction or as an event counter by a START CNT instruction. Once started the counter will increment to this maximum count (FF) and overflow to zero continuing its count until stopped by a STOP TCNT instruction or Reset.

. The increment from maximum count to zero (overflow) results in the setting of an overflow flag flip-flop and in tite generation of an interrupt request. The state of the overflow flag is testable with the conditional jump instruc- tion JTF. The flag is reset by executing a JTF or by Reset.

The interrupt request is stored in a latch and then ORed with the external interrupt input INT. The timer interrupt may be enabled or disabled independently of external in- terrupt by the EN TCNT! and DIS TCNT! instructions.

If enabled. the counter overflow will cause a subroutine call to location 7 where the timer or counter service routine may be stored.

1-7

If timer and external interrupts occur simultaneously. the external source will be recognized and the Call will be to

SINGLE COMPONENT MCS®-48 SYSTEM

S

JTF

EXECUTED----~~~_+--~

RESET R

TIMER FLAG

~I:E~RFLOW ---<~-l S Q TIMER OVERFLOW TIMER INT FF

RECOGNIZED

EXECUTED ^~----~R

RESET

S TIMER

INT

DIS TCNTI ___ ~~ ENABLE

EXECUTED ~----~ R

RESET

INT~ ____________ ~

0 PIN

INT FF

CLK A L E - - - -...

LAST CYCLE 1---'

OFINST.

ENI EXECUTED.

DISI EXECUTED

RESET ---L-.J'

S INT ENABLE R

Q

Q

Q

Q

CONDITIONAL JUMP LOGIC

INTERRUPT CALL EXECUTED

CLR

0 ^Q

CLK Q

S Q

INTERRUPT IN PROGRESS R

RESET RETR EXECUTED

FF

EXTERNAL INTERRUPT RECOGNIZED

TIMER INTERRUPT RECOGNIZED

1. WHEN INTERRUPT IN PROGRESS FLIp· FLOP IS SET . ALL FURTHER INTERRUPTS ARE LOCKED OUT

INDEPENDENT OF STATE OF EITHER INTERRUPT ENABLE FLIP·Fl.OP.

2. WHILE TIMER INTERRUPTS ARE DISABLED TIMER OVERFLOW fli WILL NOT STORE ANY OVERFLOW THAT OCCURS. TIMER FLAG WILL BE SET, HOWEVER.

Figure 8. Interrupt logic

1·8

SINGLE COMPONENT MCS®-48 SYSTEM

PRESCALER

XTAL 715

LOAD OR READ CLEARED ON START TIMER

START TIMER

JUMPON TIMER FLAG

EDGE DETECTOR

START COUNTER

o

STOPT

8 BIT TIMER/

EVENT COUNTER

ENABLE---~L_ __ ~

INT

Figure 9. Timer/Event Counter location 3. Since the timer interrupt is latched it will re-

main pending until the external device is serviced and immediately be recognized upon return from the service routine. The pending timer interrupt is reset by the Call to location 7 or may be removed by executing a DIS TCNTl instruction.

AS AN EVENT COUNTER

Execution of a START CNT instruction connects the Tl input pin to the counter input and enables the counter.

The Tl input is sampled at the beginning of state 3 or in later MCS-48 devices in state time 4. Subsequent high to low transitions on Tl will cause the counter to increment.

Tl must be held low for at least I machine cycle to insure it won't be missed. The maximum rate at which the counter may be incremented is once per three instruction cycles (every 5.7 J-Lsec when using an 8 MHz crystal) -- there is no minimum frequency. TI input must remain high for at least \15 machine cycle after each transition.

AS A TIMER

Eexcution of a START T instruction connects an internal clock to the counter input and enables the counter. The internal clock is derived bypassing the basic machine cycle clock through a -;- 32 prescaler. The prescaler is reset during the START T instruction. The resulting clock in- crements the counter every 32 machine cycles. Various delays from 1 to 256 counts can be obtained by presetting the counter and detecting overflow. Times longer than 256 counts may be achieved by accumulating multiple over- flows in a register under software control. For time res-

1-9

olution less than I count an external clock can be applied to the Tl input and the counter operated in the event counter mode. ALE divided by 3 or more can serve as this external clock. Very small delays or "fine tuning"

of larger delays can be easily accomplished by software delay loops.

Often a serial link is desirable in an MCS-48 family mem- ber. Table 2 lists the timer counts and cycles needed for a specific baud rate given a crystal frequency.

2.11 Clock and Timing Circuits

Timing generation for the 8048AH is completely selfcon- tained with the exeception of a frequency reference which can be XT AL, ceramic resonator, or external clock source.

The Clock and Timing circuitry can be divided into the following functional blocks.

OSCILLATOR

The on-board oscillator is a high gain parallel resonant circuit with a frequency range of 1 to II MHz. The XI external pin is the input to the amplifier stage while X2 is the output. A crystal or ceramic resonator connected . between X I and X2 provides the feedback and phase shift required for oscillation. If an accurate frequency reference is not required, ceramic resonator may be used in place of the crystal.

For accurate clocking, a crystal should be used. An ex- ternally generated clock may also be applied to XI-X2 as the frequency source. See the data sheet for more information.

SINGLE COMPONENT MCS®-48 SYSTEM

Table 2. Baud Rate Generation

Frequency Tcy TO Prr(1/5 Tcy) Timer Prescaler

(MHz) (32 Tcy)

4 3.75f-Ls 750ns 120f-LS

6 2.50f-Ls 500ns 80f-LS

8 1.88f-Ls 375ns 60.2f-Ls

11 1.36f-Ls 275ns 43.5f-LS

Baud 4 MHz 6 MHz 8 MHz 11 MHz

Rate Timer Counts + Timer Counts + Timer Counts + Timer Counts +

Instr. Cycles Instr. Cycles Instr. Cycles Instr. Cycles 110 75 + 24 Cycles 113 + 20 Cycles 151 + 3 Cycles 208 + 28 Cycles

.01% Error .01 % Error .01% Error .01% Error

300 27 + 24 Cycles 41 + 21 Cycles 55 + 13 Cycles 76 + 18 Cycles

.1% Error .03% Error .01% Error .04% Error

1200 6 + 30 Cycles 10 + 13 Cycles 12 + 27 Cycles 19 + 4 Cycles

.1% Error .1 % Error .06% Error .12% Error

1800 4 + 20 Cycles 6 + 30 Cycles 9 + 7 Cycles 12 + 24 Cycles

.1% Error .1 % Error .17% Error .12% Error

2400 3 + 15 Cycles 5 + 6 Cycles 6 + 24 Cycles 9 + 18 Cycles

.1% Error .4% Error .29% Error .12% Error

4800 1 + 23 Cycles 2

+

STATE COUNTER

The output of the oscillator is divided by 3 in the State Counter to create a clock which defines the state times of the machine (CLK). CLK can be made available on the external pin TO by executing an ENTO CLK instruction.

The output of CLK on TO is disabled by Reset of the processor.

CYCLE COUNTER

CLK is then divided by 5 in the Cycle Counter to pro- vide a clock which defines a machine cycle consisting of 5 machine states as shown in Figure 10. Figure 11 shows the different internal operations as divided into the machine states. This clock is called Address Latch Enable (ALE) because of its function in MCS-48 sys- terns with external memory. It is provided continuous- lyon the ALE output pin.

2.12 Reset

The reset input provides a means for initialization for the processor. This Schmitt-trigger input has an internal pull- up device which in combination with an external I J.L fd capacitor provides an internal reset pulse of sufficient length to guarantee all circuitry is reset, as shown in Figure 12. If the reset pulse is generated externally the RESET pin must be held low for at least 10 milliseconds after the

1-10

.74% Error .12% Error

power supply is within tolerance. Only 5 machine cycles (6.8 f-LS @ II MHz) are required if power is already on and the oscillator has stabilized. ALE and PSEN (if EA

= 1) are active while in Reset.

Reset performs the following functions:

I) Sets program counter to zero.

2) Sets stack pointer to zero.

3) Selects register bank O.

4) Selects memory bank O.

5) Sets BUS to high impedance state (except when EA = 5V).

6) Sets Ports 1 and 2 to input mode.

7) Disables interrupts (timer and external).

8) Stops timer.

9) Clears timer flag.

10) Clears FO and F I.

II) Disables clock output from TO.

I I

I

SINGLE COMPONENT MCS®-48 SYSTEM

.

S5

~

JUMP ON TEST = lOR 0

.273 psec (3.67 MHz)

DIAGRAM OF 8048AH CLOCK UTILITIES

1.36 psec CYCLE

Sl S2 S3

1

1

INPUT

DECODE EXECUTION

INST.

INC. PC OUTPUT

J

ADDRESS

I I

INSTRUCTION CYCLE

.

Sl INPUT

I I

(1 BYTE, 2 CYCLE INSTRUCTION ONLY) PREVIOUS CYCLE-...

_Ir-...

-tI-..

S2

I

I

I

ALE

~~---~~~---~~---

PSEN' - - - ,

RD,WR ______________________________________ __

'EXTERNAL MODE

"IF ENABLED

8048AH/8049AH TIMING

Figure 10. MCS"'-48 Timing Generation and Cycle Timing 2.13 Single-Step

This feature, as pictured in Figure 13, provides the user with a debug" capability in that the processor can be stepped through the program one instruction at a time.

While stopped, the address of the next instruction to be fetched is available concurrently on BUS and the lower

1-11

half of Port 2. The user can therefore follow the program through each of the instruction steps. A timing diagram, showing the interaction between output ALE and input SS, is shown. The BUS buffer contents are lost during single step; however, a latch may be added to reestablish the lost I/O capability if needed. Data is valid at the leading edge of ALE.