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MICROSYSTEM

COMPONENTS HANDBOOK

1985

About Our Cover:

The design on our front cover is an abstract portrayal of microprocessors and associated peripherals as the building blocks which provide total systems development solutions. Intel superior technology and reliability provide easier solutions to specific development problems thereby cutting "time-to-market" and creating a greater market share.

(

Intel Corporation makes no warranty for the use of Its products and assumes no responsibility for any errors which may appear il) this document nor does It make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice.

Contact your local sales office to obtain the latest specifications before placing your order.

The following are trademarks of Intel Corporation and may only tie used to identify Intel Products:

BITBUS, COMMputer, CREDIT, Data Pipeline, GENIUS, i,~, ICE, ICS, iDBp, lOIS, 1²1CE, ILBX, 1m, iMDDX, IMMX, Inslte, Intel, Intel, InteIBOS, Intelevision, Inlellgent Identifier, intellgent Programming, Intellec, Intel/Ink, iOSp, IPDS, iRMX, ISBC, iSBX, iSDM, iSXM, KEPROM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MULTI BUS, MULTICHANNEL, MULTI MODULE, OpeNET, Plug-A-Bubble, PROMPT, Promware, QUEST, QueX, Ripplemode, RMX/80, RUPI, Seamless, SLD, SYSTEM 2000, and UPI, and the combination of ICE, ICS, iRMX, ISBC, iSBX, MCS, or UPI and a numencal suffix

MDS IS an ordering code only and is not used as a product name or trademark. MDS') is a registered trademark of Mohawk Data Sciences Corporation,

* MULTIBUS is a patented Intel bus,

Additional copies of this manual or other Intel literature may be obtained from:

© INTEL CORPORATION 1984

Intel Corporation Literature Department 3065 Bowers Avenue Santa Clara, CA 95051

CHAPTER 1

OVERVIEW Introduction

CHAPTER 2

MCS®-80/85 MICROPROCESSORS

Table of Contents

1-1

8080Al8080A-1/8080A-2, B-Bit N-Channel Microprocessor.. .. ... .... ... ... . .... 2-1 8085AH/8085AH-2/8085AH-1 B-Bit HMOS Microprocessors ... 2-10 8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer ... 2-26 8185/8185-21024 x 8-Bit Static RAM for MC5-85 ... 2-38 8205 High Speed 1 out of 8 Binary Decoder ... 2-43 8224 Clock Generator and Driver for 8080A CPU ... 2-48 8228/8238 System Controller and Bus Driver for 8080A CPU ... 2-53 8237A18237A-4/8237A-5 High Performance Programmable DMA Controller... 2-57 8257/8257-5 Programmable DMA Controller... 2-72 8259A18259A-2/8259A-8 Programmable Interrupt Controller.... .... .... .. .... ... ... 2-89 8755A18755A-2 16, 384-Bit EPROM with I/O ... 2-107 AP-59 USing the 8259A Programmable Interrupt Controller ... : ... 2-118

CHAPTER 3

IAPX 86, 88, 186, 188 MICROPROCESSORS

iAPX 86/10 16-Bit HMOS Microprocessor... 3-1 iAPX 186 High Integration 16-Bit Microprocessor.... ... .... .. .. ... ... 3-25 iAPX 88110 B-Bit HMOS Microprocessor .. . . 3-79 iAPX 188 High Integration B-Bit Microprocessor ... 3-106 80898& 16-Bit HMOS I/O Processor ... 3-161 8087/8087-218087-1 Numeric Data Coprocessor ... 3-175 80130/80130-2 iAPX 86/30,88/30.186/30.188/30 iRMX'· 86 Operating System Processors .... 3-198 80150/80150-2 iAPX 86/50.88/50, 186/50, 188/50 CP/M'-86 Operating System Processors .... 3-220 8282/8283 Octal Latch ... 3-232 8284A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors ... 3-237 828618287 Octal Bus Transceiver ... 3-245 8288 Bus Controller for iAPX 86. 88 Processors ... 3-250 82188 Integrated Bus Controller for iAPX 86, 88, 186, 188 Processors ... _ ... > • • • • • • • • • 3-257 8289/8289-1 Bus Arbiter ... 3-274 AP-67 8086 System Design ... 3-285 AP-123 Graphic CRT Design Using the Intel 8089 ... 3-348 AP-113 Getting Started with the Numeric Data Processor ... 3-420 AP-143 Using the iAPX 86/20 Numeric Data Processor in a Small Business Gomputer ... 3-481 AP-144 Three Dimensional Graphics Application of the iAPX 86/20

Numeric Data Processor ...•... 3-504 AP-186 Introduction to the 80186 ... : ... 3-543

CHAPTER 4

IAPX 286 MICROPROCESSORS

iAPX 286110 High Performance Microprocessor with Memory Management and Protection .. 4-1 80287 8Q-Bit HMOS Numeric Processor Extension ... 4-54 82258 Advanced DMA Controller Architectural Overview ... 4-79 82284 Clock Generator and Ready Interface for iAPX 286 Processors ... 4-92 82288 Bus Controller for iAPX 286 Processors ... 4-100 82289 Bus Arbiter for iAPX 286 Processor Family ... ~ ... 4-118

'Cp/M is a Trademark of Digital Research. Inc.

iii

CHAPTER 5

MEMORY CONTROLLERS DATA SHEETS

8202A Dynamic RAM Controller... 5-1 8203 64K Dynamic RAM Controller ... ,... 5-15 8206/8206-2 Error Detection and Correction Unit ... , . . .. . . .. . ... 5-30 8207 Dual-Port Dynamic RAM Controller ... 5-51 8208 Dynamic RAM Controller ... '. .. . .. .. .. .. .. . .. . . ... 5-98 USERS MANUAL

Introduction ... 5-117 Programming the 8207 ... 5-118 RAM Interface ... 5-123 Microprocessor Interfaces ... 5-132 8207 with ECC (8206) ... 5-140 Appendix ... 5-143 APPLICATION NOTES

AP-97A Interfacing Dynamic RAM to iAPX 86/88 Using the 8202A and 8203 ... 5-147 AP-141 8203/8206/2164A Memory Design ... 5-183 AP-167 Interfacing the 8207 Dynamic RAM Controller to the iAPX 186 ... 5-189 AP-168 Interfacing the 8207 Advanced Dynamic RAM Controller to the iAPX 286 ... 5-194 ARTICLE REPRINTS

AR-364 FAE News 1/84 "8208 with 186" ... 5-201 AR-231 Dynamic RAM Controller Orchestrates Memory Systems ... 5-212

-VOLUME2-

SUPPORT PERIPHERALS DATA SHEETS

8231A Arithmetic Processing Unit ... 5-219 8253/8253-5 Programmable Interval Timer ... 5-229 8254 Programmable Interval Timer ... 5-240 82C54 CHMOS Programmable Interval Timer ... 5-256 8255A!8255A-5 Programmable Peripheral Interface ... 5-273 82C55A CHMOS Programmable Peripheral Interface ... 5-294 8256AH Multifunction Microprocessor Support Controller ... 5-317 8279/8279-5 Programmable Keyboard/Display Interface ... 5-340 APPLICATION NOTES

AP-153 Designing with the 8256 ... 5-352 AP-183 8256AH Application Note ... 5-427

FLOPPY DISK CONTROLLERS .

DATA SHEETS

8272A Single/Double Density Floppy Disk Controller ... 5-444 APPLICATION NOTES

AP-116 An Intelligent Data Base System Using the 8272 ... 5-463 AP-121 Software Design and Implementation of Floppy Disk Systems ... 5-504 HARD DISK CONTROLLERS

DATA SHEETS

82062 Winchester Disk Controller ... 5-574 82064 Winchester Disk Controller with On-Chip Error Detection and Correction ... 5-601 UPI USERS MANUAL

Introduction ... ,., ... , ... 5-635 Functional Description ... ' ... 5-639 Instruction Set ... 5-656 Single-Step, Programming, and Power-Down Modes ... 5-683 System Operation ...•... 5-688 Applications ... 5-694 AP-161 Complex Peripheral Control with the UPI-42 ... 5-750 AP-90 An 8741A/8041A Digital Cassette Controller ... 5-806

iv

DATA SHEETS

8041A/8641 A/8741 A Universal Peripheral Interface 8-Bit Microcomputer ... 5-814 8042/8742 Universal Peripheral Interface 8-Bit Microcomputer. . . .. 5-826 8243 MCS-48 Input/Output Expander ... 5-840 APPLICATION NOTES

AP-182 Multimode Winchester Controller Using the 82062 ... 5-846 SYSTEM SUPPORT

ICE-42 8042 In-Circuit Emulator ... 5-910 MCS-48 Diskette-Based Software Support Package ... 5-918 iUP-200/iUP-201 Universal PROM Programmers ... 5-920

CHAPTER 6

DATA COMMUNICATIONS INTRODUCTION

Intel Data Communications Family Overview... ... ... .. .. 6-1 GLOBAL COMMUNICATIONS

DATA SHEETS

8251 A Programmable Communication Interface.. ... ... ... .... 6-3 8273/8273-4 Programmable HDLC/SDLC Protocol Controller ... 6-20 8274 Multi-Protocol Serial Controller (MPSC) ... 6-48 82530/82530-6 Serial Communications Controller (SCC) ... 6-85 APPLICATION NOTES

AP-16 Using the 8251 Universal Synchronous/Asynchronous

ReceiveriTransmitter ... 6-113 AP-36 Using the 8273 SDLC/HDLC Protocol Controller ... 6-144 AP-134 Asynchronous Communications with the 8274 Multiple

Protocol Serial Controller ... 6-191 AP-145 Synchronous Communications with the 8274 Multiple

Protocol Serial Controller ... 6-228 AP-222 Asynchronous SDLC Communications with 82530 ... 6-268 LOCAL AREA NETWORKS

DATA SHEETS

82501 Ethernet Serial Interface ... 6-288 82C502 Ethernet Tranceiver Chip Data Sheet ... 6-299 82586 Local Area Network Coprocessor ... 6-302 82588 Personal Workstation Lan Control ... 6-336 ARTICLE REPRINTS

AR-345 Build a VLSI-Based Workstation for the Ethernet

Environment ...•... 6-362 AR-346 VLSI Solutions for Tiered Office Networks ...•... 6-370 AR-342 Chips Support Two Local Area Networks ... 6-380 OTHER DATA COMMUNICATIONS

DATA SHEETS

, 8291A GPIB Talker/Listener ... 6-386 8292 GPIB Controller ... 6-415 8294A Data Encryption Unit ... 6-430 APPLICATION NOTES

AP-66 Using the 8292 GPIB Controller ... 6-442 AP-166 Using the 8291A GPIB Talker/Listener ... 6-496 ARTICLE REPRINTS

AR-208 SLI Transceiver Chips Complete GPIB Interface ... 6-528 AR-113 LSI Chips Ease Standard 488 Bus Interfacing ... 6-536 TUTORIAL

Data Encryption Tutorial ... 6-546

v

CHAPTER 7

ALPHANUMERIC TERMINAL CONTROLLERS

DATA SHEETS

8275H Programmable CRT Controller ...•... _. . . . 7-1 8276H Small System CRT Controller. . . 7-25 APPLICATION NOTES

AP-62 A Low Cost CRT Terminal Using the 8275 . \. . . 7-42 ARTICLE REPRINTS

AR-178 A Low Cost CRT Terminal Does More with Less ... 7-84

GRAPHICS DISPLAY PRODUCTS

DATA SHEETS

82720 Graphics Display Controller ... 7-91 ARTICLE REPRINTS

AR-255 Dedicated VLSI Chip Lightens Graphic Display

Design Load ....•.•... ; ... 7-128 AR-298 Graphics Chip Makes Low Cost High Resolution, Color

Displays Possible ... 7-136

TEXT PROCESSING PRODUCTS

DATA SHEETS

82730 Text Coprocessor ... 7-143 82731 Video Interface Controller ... 7-187 ARTICLE REPRINTS

AR-305 Text Coprocessor Brings Quality to CRT Displays ... 7-20p AR-297 VLSI Coprocessor Delivers High Quality Displays ... 7-214 AR-296 Mighty Chips .•...•... 7-217

vi

Numeric Index

80130/81030-2 iAPX 86/30,88/30,186/30,188/30 iRMX'· 86 Operating System Processors ... 3-198 80150/80150-2 iAPX 86/50, 88/50, 186/50, 188/50 C/PM*-86 Operating System Processors ... 3-220 80186 (iAPX 186) High Integration 16-Bit Microprocessor ... 3-25,3-543 80188 (iAPX 188) High Integration 8-Bit Microprocessor ... 3-106 80286 (iAPX 286/10) High Performance Microprocessor with Memory Management

and Protection ... 4-1 80287 80-Bit HMOS Numeric Processor Extension ... 4-54 8041A/8641A/8741A Universal Peripheral Interface 8-Bit Microcomputer ... 5-814,5-635,5-639 8042/8742 Universal Peripheral Interface 8-Bit Microcomputer ... 5-826,5-635,5-639,5-910 8080A/8080A-1/8080A-2, 8-Bit N-Channel Microprocessor ... 2-1 8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors ... 2-10 8086 (iAPX 86/10) 16-Bit HMOS Microprocessor ... 3-1,3-285 8087/8087-2/8087-1 Numeric Data Coprocessor ... 3-175,3-420,3-481,3-504,6-362 8088 (iAPX 88/10) 8-Bit HMOS Microprocessor ... 3-79 80898 & 16-Bit HMOS I/O Processor ... : ... 3-161, 3-348 8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer ... 2-26 8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 ... 2-38 8202A Dynamic RAM Controller ... 5-1, 5-147 8203 64K Dynamic RAM Controller ... 5-15,5-147,5-183 8205 High Speed 1 out of 8 Binary Decoder ... 2-43 8206/8206-2 Error Detection and Correction Unit ... 5-30,5-183,5-212 82062 Winchester Disk Controller ... 5-574,5-846 82064 Winchester Disk Controller with On-Chip Error Detection and Correction ... 5-601 8207 Dual-Port Dynamic RAM Controller ... 5-51, 5-118, 5-123, 5-132, 5-140

5-143,5-183,5-189,5-194,5-212 8208 Dynamic RAM Controller ... 5-98, 5-201 82188 Integrated Bus Controller for iAPX 86, 88, 186, 188 Processors ... 3-257 8224 Clock Generator And Driver for 8080A CPU ... 2-48 82258 Advanced DMA Controller Architectural Overview ... 4-79 8228/8238 System Controller and Bus Driver for 8080A CPU ... 2-53 82284 Clock Generator and Ready Interface for iAPX 286 Processors ... 4-92 82288 Bus Controller for iAPX 286 Processors ... 4-100 82289 Bus Arbiter for iAPX 286 Processor Family ... 4-118 8231 A Arithmetic Processing Unit ... 5-219 8237 A/8237 A-4/8237 A-5 High Performance Programmable DMA Controller ... 2-57 8243 MCS-48 Input/Output Expander ... 5-635,5-840 82501 Ethernet Serial Interface ... 6-288, 6-362, 6-38'0 82C502 Ethernet Tranceiver Chip ... 6-299 8251 A Programmable Communication Interface ...•... 6-3,6-113 8253/8253-5 Programmable Interval Timer ... '" .... '" ... 5-229 82530/82530-6 Serial Communications Controller (SCC) ... 6-85, 6-268

vii

8254 Programmable Interval Timer ... 5-240 82C54 CHMOS Programmable Interval Timer ... '," ... 5-256 8255A/8255A-5 Programmable Peripheral Interface ... " ... 5-273, 7-84 82C55 CHMOS Programmable Peripheral Interface ... 5-294 8256AH Multifunction Microprocessor Support Controller ... " ... 5-317, 5-352, 5-427 8257/8257-5 Programmable DMA Controller ... '" ... , ... 2-72

j

82586 Local Area Network Coprocessor. . . .. 6-302, 6-362, 6-370, 6-380 82588 Personal Workstation Lan Control ... 6-336 8259A/8259A-2/8259A-8 Programmable Interrupt Controller ... 2-89, 2-118 8272A Single/Double Density Floppy Disk Controller ... 5-444,5-463,5-504,7-128 82720 Graphics Display Controller ... 7-91,7-128,7-136,7-206,7-214,7-217 8273/8273-4 Programmable HDLC/SDLC Protocol Controller ... 6-20,6-144,6-380 82730 Text Coprocessor ... 6-262,7-136,7-143,7-206, 7-214, 7-217 82731 Video Interface Controller ... .7-187,7-206 8274 Multi-Protocol Serial Controller (MPSC) ... ,6-48,6-191,6-228,6-380 8275H

Programm~ble

CRT Controller ... 7-1, 7-42 8276H Small System CRT Controller ... 7-25, 7-84 8279/8279-5 Programmable Keyboard/Display Interface ... 5-340 8282/8283 Octal Latch ... 3-232 8284A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors ... 3-327 , 8286/8287 Octal Bus Transceiver ... 3-245 8288 Bus Controller for iAPX 86, 88 Processors ... , ... 3-250,6-362 8289/8989-1 Bus Arbiter ... , ... 3-274 8291A GPIB Talker/Listener ... 6-386,6-496,6-528,6-536 8292 GPIB Controller ... 6-415,6-442,6-528,6-536 8294A Data Encryption Unit ... 6-430 8755A/8755A-2 16,384-Bit EPROM with I/O ... 2-107

/

viii

Overview 1

, I I

inter

INTRODUCTION

Intel microprocessors and peripherals provide a complete solution in increasingly complex application environ- ments. Quite often, a single peripheral device will replace anywherefrom 20 to 100 TIL devices (and the associated design time that goes with them).

Built-in functions and a standard Intel microprocessor/

peripheral interface deliver very real time and perfor- mance advantages to the designer of microprocessor-

baseq

systems.

REDUCED TIME TO MARKET

When you can purchase an off-the-shelf solution that replaces a number of discrete devices, you're also re- placing all the design, testing, and debug time that goes

with them. '

INCREASED RELIABILITY

At Intel, the rate offailure for devices is carefully tracked.

Highest reliability is a tangible goal that translates to higher reliability, for your product, reduced downtime, and reduced repair costs. And as more and more functions are integrated on a single VLSI device, the resulting system requires less power, produces less heat, and requires fewer mechanical connections-again result- ing in greater system reliability.

LOWER PRODUC~ COST

By minimizing design time, increasing reliability, and

replacing numerous parts, microprocessor and peripheral solutions can contribute dramatically to lower product costs.

HIGHER SYSTEM PERFORMANCE

, Intel microprocessors and peripherals provide the highest system performance for the demands of today's (and tomorrow's) microprocessor-based applications. For example, the iAPX 286 CPU, with its on-chip memory management and protection, offers the highest per- formance for multitasking, multiuser systems.

HOW TO USE THE GUIDE

The following application guide illustrates the range of microprocessors and peripherals that can be used for the applications in the vertical column on the left. The peripherals are grouped by the 1/ 0 function they control:

CRT, datacommunication, universal (user program- mable), mass storage dynAmic RAM controllers, and CPU/bus support.

An "X" in a horizontal application row indicates

a

poten- tial peripheral or CPU, depending upon the features desired. For example, a conversational terminal could use either of the three display controllers, depending upon features like the number of characters per row or font capability. A "Y" indicates a likely candidate, for example, the 8272A Floppy Disk Controller in a small business computer.

The Intel microprocessor and peripherals family provides a broad range of time-saving, high performance solutions.

POTENTIAL CANDIDATE X-TYPICAL CANDIDATE Y

, j.lPROCESSOR DISPLAY DATACOMM UPI DISKS DRAM CONTROL SUPPORT

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COMPUTERS SM Bus Computer

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APPLICA TION

TERMINALS Conversational Graphics CRT Editing Intelligent Videotex

Printing, Laser, Impact Portable

INDUSTRIAL AUTO Robotics

Network Num Control Process Control instrumentation AVlatlon/Navlg INDUST/DATA ACO

Laboratory Instr Source Data Auto Test Medical Test Instr Security

COMMERCIAL DATA PROCESSING

POS Terminal Financial Transfer Automatic Teller Document Processing WORKSTATIONS

Office Engineering CAD

MINI MAINFRAME Processor & Control Store Database Subsys ilO Subsystem Comm Subsystem

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MCS®-SO/S5

Microprocessors 2

8080A/8080A·1/8080A·2

8·BIT N .. CHANNEl MICROPROCESSOR

• TIL Drive Capability

• 2 /-'s ( - 1 :1.3 /-'s, - 2:1.5 /-,s) Instruction Cycle

• Powerful Problem Solving Instruction Set

• 6 General Purpose Registers and an Accumulator

• 16·Bit Program Counter for Directly Addressing up to 64K Bytes of Memory

• 16·Bit Stack Pointer and Stack Manipulation Instructions for Rapid Switching of the Program Environment

• Decimal, Binary, and Double Precision Arithmetic

• Ability to Provide Priority Vectored Interrupts

• 612 Directly Addressed flO Pons

• Available in EXPRESS

- Standard Temperature Range

The Intel"' aOaOA is a complete a-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing apQlications.

The aOaOA contains 6 a-bit general purpose working registers and an accumulator. The 6 general purpose registers may be addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set or reset 4 testable flags. A fifth flag provides decimal arithmetic operation.

The aOaOA has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general purpose registers. The 16-bit stack pointer controls the addressing,of this external stack. This stack gives the aOaOA the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting.

This microprocessor has been designed to simplify systems design. Separate 16-line address and a-line bidirectional data busses are used to facilitate easy interface to memor" and I/O. Signals to control the interface to memory and 110 are provided directly by the aOaOA. Ultimate control of the address and data busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits OR-tying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation.

NOTE:

The 8080A is functionally and electrically compatible with the Intel"' 8080.

0,°0

&IDIRECTIONAl DATA BUS

Figure 1. Block Diagram

GNO

'10

RESET HOLD INT

SYNC '5V

8080A 40 3.

3.

37 36 35 34 33 32 31 30 2' 2.

27 26 25 24 23 22

2'

.. '.

+12V

'3

"

.,

Ao

WAIT READY

"

_HLDA

Figure 2. Pin Configuration

8080AI8080A·118080A·2

Table 1. Pin Description

Symbol Type Name and Function

A15.AO 0 Address Bus: The address bus provides the address to memory (up to 64K a-bit words) or denotes the I/O device number for up to 256 Input and 256 output devices Ao IS the least significant address bit.

DrDo I/O Data Bus: The data bus provides bl-dlrectlonal communication betweeen the CPU, memory, and I/O devices for Instructions and data transfers. Also, dUring the first clock cycle of each machine cycle, the aOaOA outputs a status word on the data bus that describes the current macHine cycle. Do IS the least significant bit.

SYNC 0 Synchronizing Signal: The SYNC pin provides a signal to indicate the beginning of each machine cycle DBIN 0 Data Bus In: The DBIN signal Indicates to external circUits that the data bus IS In the input mode. This

signal should be used to enable the gating of data onto the aOaOA data bus from memory or I/O READY I R!'ady: The READY signal indicates to the aOaOA that valid memory or Input data is available on the aOaOA

data bus This signal is used to synchronize the CPU With slower memory or I/O devices If after sending an address out the aOaOA does not receive a READY Input, the aOaOAw11i enter a WAITstate for as long as the READY line IS low. READY can also be used to Single step the CPU.

WAIT 0 Wait: The WAIT signal acknowledges that the CPU IS In a WAIT state.

WR 0 Write: The WR signal IS used for memory WRITE or I/O output control. The data on the data bus IS slable while the WR signal IS active low (WR ~ 0).

HOLD , I Hold: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state allows an external device to gain control of the aOaOA address and data bus as soon !\S the 8080A has completed its use of these busses for the current machine cycle. It IS recognized under the following conditions:

• the CPU is in the HALT srate.

• the CPU IS In the T2 or TW state and the READY signal is active. As a result of entering the HOLD state the CPU ADDRESS BUS (A1S-Ao) and DATA BUS (Dr Do) will be In their high Impedance state. The CPU acknowledges ItS state With the HOLD ACKNOWLEDGE (HLDA) pin

HLDA 0 Hold Acknowledge: The HLDA signal appears in response to the HOLD signal and indicates that the data and address bus will go to the high impedance state. The HLDA signal begins at·

• T3 for READ memory or input.

• The Clock Period following T3 for WRITE- memory or OUTPUT operation.

\

In either case, the HLDA signal appears after the rising edge of <1>2

INTE 0 Interrupt Enable: Indicates the content of the Internal Interrupt enable flip/flop This flip/flop may be set or reset by the Enable and Disable In\;rrupt instructions and inhibits interrupts from being accepted by tbe CPU when It IS reset It IS automatically reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an Interrupt is accepted and is also reset by the RESET signal.

INT I Interrupt Request: The CPU recognizes an interrupt request on this line at the end of the current Instruction or while halted If the CPU IS In the HOLD state or if the Interrupt Enable flip/flop is reset it will not honor the request

RESET1 I Reset: While the RESET signal IS activated, the content of the'program counter is cleared. After RESET, the program will start at location 0 In memory. The INTE and HLDA flip/flops are also reset. Note that the flags, accumulator, stack pOinter, and registers are not cleared.

Vss Ground: Reference

VDD Power: +12 ±5% Volts

Vee Power: +5 ±5% Volts.

Vss Power: -5 ±5% Volts.

<111, <1>2 Clock Phases: 2 externalfy supplied clock phases. (non TTL compatible)

2-2

inter 8080Al8080A·1/8080A·2 ABSOLUTE MAXIMUM RATINGS·

Temperature Under Bias. . . . . . . . . .. .

dOc

to +70° C Storage Temperature . . . -65°C to +150°C All Input or Output Voltages

With Respect to Vee . . . -0.3V to +20V Vcc , VOO and Vss With Respect to Vee -0.3V to +20V Power Dissipation . . . 1.5W

"NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absoluta maxi- mum rating conditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS

(TA = O"C to 70"C, VOO = +12V ±5%,

VCC = +5V ±5%, Vee = -5V ±5%, Vss =OV; unless otherwise noted)

Symbol Parameter Min. Typ. Max.

VILC Clock Input Low Voltage Vss-l Vss+o.8

VIHC Clock Input High Voltage 9.0 Vo o +l

VIL Input Low Voltage Vss-l Vss+0.8

VIH Input High Voltage 3.3 Vcc+l

VOL Output Low Voltage 0.45

VOH Output High Voltage 3.7"

loe(AV) Avg. Power Supply Current (Voo) 40 70 ICC (AV) Avg. Power Supply Current (Vcc) 60 80 IBe(AV) Avg. Power Supply Current (VBe ) .01 1

IlL Input Leakage ±10

ICL Clock Leakage ±10

IOL[2] Data Bus Leakage in Input Mode -100

-2.0

IFL Address and Data Bus Leakage +10

During HOLD -100

CAPACITANCE

(TA = 25°C, VCC = VOO =VSS = OV, Vee = -5V) Symbol Parameter Typ. Max. Unit Test Condition C", Clock Capacitance 17 25 pf fc = 1 MHz CIN I nput Capacitance 6 10 pf Unmeasured Pins COUT Output Capacitance 10 20 pf Returned to Vss NOTES:

1. The RESET SIgnal must be active for a mInimum of 3 clock cycles.

2. <l.1 S u I pp y I<l.T A ~-O.45%fC.

2-3

Unit Test Condition

V V V V

V } IOL = 1.9mA on all outputs, V IoH =-150~.

mA

mA

}O ...

^';M

T Cy '" .48 J.Lsec mA

J.LA Vss .;;;; VIN .;;;; Vcc J.LA Vss .;;;; VCLOCK .;;;; Voo J.LA Vss ';;;;VIN ';;;;VSS +0.8V mA VSS+0.8V';;;;VIN ';;;;VCC

J.LA VAOOR/OATA = Vcc V AOOR/OATA = Vss + 0.45V

,.

'O~ ---- ^r---

o. 0 +2' +50

AMBIENT TEMPERATURE (OC)

typical Supply Current v ••

Temperature, Normallzed[3]

+7&

,

, 8080Al8080A·1/8080A·2

A.C. CHARACTERISTICS (8080A)

(TA = ooe to 7ooe, VDD = +12V ±5%, Vee = +5V ±5%, VBB =-5V ±5%, vss =OV; unless otherwise noted)

,

_{'1' ·1 ·2 ·2}

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Tesl Condilion

ICy[3J Clock Penod 0.48 2.0 0.32 2.0 0.38 2.0 JAsec

Ir' If Clock Rise and Fall Time 0 50 0 25 0 50 nsec

112'1 12'1 Pulse Wldlh 60 50 60 nsec

112'2 "'2 Pulse Widlh 220 145 175 nsec

101 Delay "'1 10 "'2 0 0 0 nsec

102 Delay 12'2 to "'1 70 50 70 nsec

103 Delay "'1 10 "'2 Leading Edges 80 60 70 nsec

IDA Address Oulpul Delay From "'2 200 150 175 nsec

J

^{CL;loo pF}

too

Data Oulput Delay From "'2 220 160 200 nsec

IDC Signal Output Delay From I.e!

Ilor

"'2 (SYNC, WR, WAIT, HLDA) 120 110 120 nse~

},CL;50 pF

IDF DBIN Delay From 12'2 25 140 25 130 25 140 nsec

101[1] Delay for Input Bus to Enter Input Mode tDF tDF tDF ^nsec

IDSI Data Selup TimeDurlng 12'1 and DBIN .. 30 10 20 nsec

IDS2 Data Selup Time to 12'2 During DBIN 150 120 130 nsee

tDH[tJ Data Holt time From "'2 During DBIN [IJ [1J [IJ nsec

tiE INTE Output Delay From 12'2 200 200 200 nsec CL;50 pF

tRS READY Setup Time During "'2 120 90 90 nsec

IHS HOLD Selup Time to 12'2 140 120 120 nsec

liS INT Selup Time During 12'2. 120 . 100 100 nsec

IH Hold Time From 12', (READY, INT, HOLD) 0 0 0 nsec

IFD DelJlY Ip Float Dur\ng Hold«Address and Data 'Bus) t~e ~20' 12'iJ nsec

-

lAW Address Slable· Prior 10 WR [5J [5J [5J nsec

lOW Oulput Dala Slable Prior to WR [6J [6J [6] nsec

IWD. Oulpul Dala Slable From WR [7] [7] [7] nsec

IWA Address Stable From WR [7] [7] [7] nsec CL; 100 pF: Address, Data

51.; 50 pF: WR,HLDA,DBIN

tHF HLDA to Float Delay [8] [8] [8] nsec

tWF WR to Float Delay [9J [9] [9] nsec

tAH Address Hold Time After DBIN During HLDA -20 -20 -20 nsec __

A.C.

TESTING LOAD CIRCUIT

DEVICE

UNDER ~

TEST

'--_ _ _ _ ..J

I

C, ~ 100 pF CL = 100pF

CL INCLUDES JIG CAPACITANCE

2-4

I

8080A/8080A·1/8080A·2 WAVEFORMS

0, _ _ _ _ ...J

0,

- - - 1 - - - ' 1 1

A1SAO ---I-~~

SYNC - - - 1 - - ' 1

OBIN

- - - r - - - ' I

WR

READY

~

@I

^'

' 0 j I

~"lI-'"T- ·

!

- '" ,-i -I '" ^--='1

^'DC

^{I--:~ I,}

WAIT ---~~'D~c---+~'I-'" - - ,

f

_~,"~.~r

\

^I

..

-!~-.~I~,~'

~W _~,

- t H S - HLDA

INT---~1--H---13'

---~...:I

' ," __ 1_

lNTE

NOTE:

Timing measurements are made at the following reference voltages: CLOCK "1" = B.OV,

"0" = 1.0V; INPUTS "1" = 3.3V, "0" = O.BV; OUTPUTS "1" = 2.0V, "0" = O.BV.

WAVEFORMS (Continued)

J

'FO

~'5-AO

----+---- --

0,.°0

SYNC

DBIN

...

READY

WAIT

HOLD ~

HLDA

...

INT

INTE

8080Al8080A·1/8080A·2

-.

~~

-.

-~

2-6

NOTES: (Parenthesis gives -1, -2 specifications, respectively) 1. Data Input should be enabled with DBIN status. No bus con-

flict can then occur and data hold time Is assured.

tOH ,. SO ns or tOF, whichever Is less.

2. tCY = t03 + tr</>2 +'<1>2 + tf</>2 + t02 + tr</>l ;;. 480 ns ( - 1 :320 ns, - 2:380 ns).

TYPICAL L> OUTPUT DELAY VS. L> CAPACITANCE

,.

c

~

₀

..

::>

~ ::>

0

<l +20

+10

/

/

-10

/'"

" - SPEC -20

/

-100 -50

...\ CAPACITANCE lpf) (CACTUAL - C SPEC )

+50 +100

3. The followihg are relevant when Interfacing the BOBOA to devices havl ng V I H = 3.3V:

a) Maximum output rise time from .BV to 3.3V = l00ns@ CL

= SPEC.

b) Output delay when measured to 3.0V = SPEC +60ns@CL

= SPEC.

c) If CL = SPEC, add .6nsipF If CL > CSPEC, subtract .3nsipF (from modified delay) If CL < CSPEC.

4. tAW = 2 tCY- t03 - tr</>2 - 140 ns ( - 1 :110 ns, - 2:130 ns).

S. tow = tCY - t03 - tr</>2 - 170 ns ( - 1 :1S0 ns, - 2:170 ns) . 6. If not HLDA, two = tWA = t03 + tr</>2 + 10 ns. If HLDA, two

= tWA = tWF'

7. tHF = too + tr</>2 -SO ns).

B. tWF = too + tr</>2 - 10ns.

9. Data In must be stable for this period during DBIN T 3.

Both tOSl and tOS2 must be satisfied.

10. Ready signal must be stable for this period during T 2 or T w.

(Must be externally synchronized.)

11. Hold Signal must be stable for this period during T 2 or T W when entering hold mode, and during T 3, T 4, T 5 and T WH when in hold mode. (External synchronization is not re- quired.)

12. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be recognized on the following instruction. (External synchronization is not re- ,qulred.)

13. this timing diagram shows timing relationships only; it does not represent any specific machine cycle.

inter SOSOAISOSOA·1/&OSOA·2 INSTRUCTION SET

The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate ad- dressing modes_

Move, load, and store instruction groups provide the ability to move either 8 or 16 bits of data between memory, the six working registers and the accumulator using direct, in- direct, and immediate addressing modes.

The ability to branch to different portions of the program is provided with jump, jump conditional, and computed jumps. Also the ability to call to and return from sub- routines is provided both conditionally and unconditionally.

The RESTART (or single byte call instruction) is useful for interrupt vector operation.

Double precision operators such as stack manipulation and double add instructions extend both the arithmetic and interrupt handling capability of the 8080A. The ability to

Data and Instruction Formats

increment and decrement memory, the six general registers and the accumulator is provided as well as extended incre- ment and decrement instructions to operate on the register pairs and stack pointer. Further capability is provided by the ability to rotate the accumulator I!lft or right through or around the carry bit.

Input and output may be accomplished using memory ad- dresses as I/O ports or the directly addressed I/O provided for in the 8080A instruction set.

The following special instruction group completes the 8080A instruction set: the NOP instruction, HALT to stop pro- cessor execution and the DAA instructions provide decimal arithmetic capability. STC allows the carry flag to be di- rectly set, and the CMC instruction allows it to be comple- mented. CMA complements the contents of the accumulator and XCHG exchanges the contents of two 16-bit register pairs directly.

Data in the 8080A is stored in the form of 8-bit binary integers. All d~ta transfers to the system data bus will be in the same format.

I

D7 D6 D5 D4 D3 D2 D, Dol DATA WORD

The program instructions may be one, two, or three bytes in length. MUltiple byte instructions must be stored in successive words in program memory. The instruction formats then depend on the particular operation executed.

One Byte Instructions TYPICAL INSTRUCTIONS

I

D7 D6 D5 D4 D3 D2 D, Do

I

^{OP CODE} Register to register, memory refer- ence, arithmetic or logical, rotate, return, push, pop, enable or disable Interrupt instructions

Two Byte Instructions

I

D7 D6 D5 D4 D3 D2 D, Do

I

^OPCODE

I

D7 D6 D5 D4 D3 D2 D, Do

I

^OPERAND Immediate mode or I/O instructions Three Byte Instructions

I

D7 D6 D5 D4 D3 D2 D, DO

I

^OPCODE Jump, call or direct load and store

I

D7 D6 D5 D4 D3 D2 D, Do

I

LOWADDRESSOR OPERAND 1 instructions

I

D7 D6 D5 D4 D3 D2 D, Do

I

HIGH ADDRESSOR OPERAND 2

For the 8080A a logic "1" is defined as a high level and a logic "0" is defined as a low level.

2-7

8080Al8080A·118080A·2

Table 2. Instruction Set Summary

Clock Clock

Instruction Code [1] Operations Cycle. Instruction Code [1] Operations Cycle.

Mnemonic 0] 06 05 04 D:3 D:1 ^{01 DO} Description [2] MnemoniC 0] 06 Os 04 03 02 01 Do Description [2]

MOvE, LOAD, AND STORE JPO 1 1 1 0 0 0 1 0 Jump on parity odd 10

MOVr1,r2 0 1 0 0 0 S S S Move register to register 5 PCHL 1 1 1 0 1 0 0 1 H & L to program 5

MOVM,r 0 1 1 1 0 S S S Move register to counter

memory 7 CALL

MOVr,M 0 1 0 0 0 1 1 0 Move memory to regis- CALL 1 1 0 0 1 1 0 1 Call unconditional 17

ter 7 CC 1 1 0 1 1 1 0 0 Call on carry 11/17

MVlr 0 0 0 0 0 1 1 0 Move immediate re9j5- CNC 1 1 0 1 0 1 0 0 Call on no carry 11/17

ter 7 CZ 1 1 0 0 1 1 0 0 Call on zero 11/17

MVIM 0 0 1 1 0 1 1 0 Move immediate CNZ 1 1 0 0 0 l ' 0 0 Call on no zero 11/17

memory 10 CP 1 1 1 1 0 1 0 0 Call on positive 11/17

LXI B 0 0 0 0 0 0 0 1 Load immediate register 10 CM 1 1 1 1 1 1 0 0 Call on minus 11/17 Pair B & C CPE 1 1 1 0 1 1 0 0 Call on parity even 11/17 LXI 0 0 0 0 1 0 0 0 1 Load Immediate register 10 CPO 1 1 1 0 0 1 O. 0 Call on parity odd 11/17

Pair 0& E RETURN _I

LXI H 0 0 1 0 0 0 0 1 Load immediate register 10 RET 1 1 0 0 1 0 0 1 Return 10

PalrH&L RC 1 1 0 1 1 0 0 0 Return on carry 5111

STAXB 0 0 0 0 0 0 1 0 Store A Indirect 7 RNC 1 1 0 1 0 0 0 0 Retu rn on no carry 5111 STAXO 0 0 0 1 0 0 1 0 Store A Indirect 7 RZ 1 1 0 0 1 0 0 0 Return on zero 5111 LOAX B 0 0 0 0 1 0 1 0 Load A Indirect 7 RNZ 1 1 0 0 0 0 0 0 Return on no zero 5111 LOAXO 0 0 0 1 1 0 1 0 Load A indirect 7 RP 1 1 1 1 0 0 0 0 Return on positive 5111 STA' 0 0 1 1 0 0 1 0 Store A direct 13 RM 1 1 1 1 1 0 0 0 Return on minus 5111 LOA 0 0 1 1 1 0 1 0 Load A direct 13 RPE 1 1 1 0 1 0 0 0 Return on parity even 5111 SHLO 0 0 1 0 0 0 1 0 Store H & L direct 16 RPO 1 1 1 0 0 0 0 0 Return on panty odd 5/11 LHLO 0 0 1 0 1 0 1 0 Load H & L direct 16 RESTART

XCHG 1 1 1 0 1 0 1 1 Exchange 0 & E, H & L 4 RST 1 1 A A A 1 1 1 Restart 11

Registers INCREMENT AND DECREMENT

STACKOPS INRr 0 0 0 0 0 1 0 0 Increment register 5

PUSH B 1 1 0 0 0 1 0 1 Push register Pair B & 11 C on stack

OCRr 0 0 0 0 0 1 0 1 Decrement registe~ 5 INRM 0 0 1 1 0 1 0 0 Increment memory 10 PUSH 0 1 1 0 1 0 1 0 1 Push register PaH 0 ^& 11 OCRM 0 0 1 1 0 1 0 1 Decrement memory 10

E on stack INXB 0 0 0 0 0 0 1 1 Increment B & C 5

PUSH H 1 1 1 0 0, 1 0 1 Push register Pair ~ & 11 L on stack

registers

INXO 0 0 0 1 0 0 1 1 Increment 0 & E 5

PUSH 1 1 1 1 0 1 0 1 Push A and Flags 11 registers

PSW on stack INXH 0 0 1 0 0 0 1 1 Increment H & L 5

POPB 1 1 0 0 0 0 0 1 Pop register Pair B & 10 registers

C off stack OCXB 0 0 0 0 1 0 1 1 Decrement B & C 5

POP 0 1 1 0 1 0 0 0 1 Pop register Pair 0 & 10 E off stack

OCXO 0 0 0 1 1 0 1 1 Decrement D & E 5 OCXH 0 0 i 0 1 0 1 1 Decrement H & L '5 POPH 1 1 1 0 0 0 0 1 Pop register Pal r H & 10 ADD

L off stack AOOr 1 '0 0 0 0 S S S Add register to A 4

POPPSW 1 1 1 1 0 0 0 1 Pop A and Flags 10 AOCr 1 0 0 0 1 S S S Add register to A 4

off stack With carry

XTHL 1 1 1 0 0 0 1 1 Exchange top of 18 AOOM 1 0 0 0 0 1 1 0 Add memory to A 7

stack, H & L AOCM 1 0 0 0 1 1 1 0 Add memory to A 7

SPHL 1 1 1 1 1 0 0 1 H & L to stack pOinter 5 With carry

LXISP 0 0 1 f 0 0 0 1 Load Immediate stack 10 AOI 1 1 0 0 0 1 1 0 Add Immediate to A 7

pOinter ACI 1 1 0 0 1 1 1 0 Add immediate to A 7

INXSP 0 0 1 1 0 0 1 1 Increment stack pointer 5 With carry

OCXSP 0 0 1 1 1 0 1 1 Decrement stack 5 OAOB 0 0 0 0 1 Q 0 1 AddB&CtoH&L 10

pointer DADO 0 0 0 1 1 0 0 1 AddO&EtoH&L 10

JUMP OAOH 0 0 1 0 1 0 0 1 AddH&LtoH&L 10

JMP 1 1 0 0 0 0 1 1 Jump unconditional 10 OAOSP 0 0 1 1 1 0 0 1 Add stack pointer to 10

JC 1 1 0 1 1 0 1 0 Jump on carry 10 H&L

JNC 1 1 0 1 0 0 1 0 Jump on no carry 10 JZ 1 1 0 0 1 0 1 0 Jump on zero 10 JNZ 1 1 0 0 0 0 1 0 Jump on no zero 10 JP 1 1 1 1 0 0 1 0 Jump on positive 10 JM 1 1 1 1 1 0 1 0 Jump on minus 10 JPE 1 1 1 0' 1 0 1 0 Jump on parity even 10

2-8

inter 8080Al8080A·1/8080A·2

SUm .... ry of Proce_r Instructions (Cont.) Clock

Instruction Code [1] Operations Cycl.s Instruction Code [1 )

Mnemonic D7 Ds Ds D4 OJ D2 Dl DO Description [2] Mnemonic D7 De Ds D4 OJ II:! Dl Dc

SUBTRACT ROTATE

SUBr 1 0 0 1 0 S S S Subtract regIster 4 RLC 0 0

from A RRC 0 0

SBBr 1 0 0 1 1 S S S Subtract regIster from 4 RAL 0 0 A WIth borrow

SUBM 1 0 0 1 0 1 1 0 Subtrect memory 7 RAR 0 0

from A

SBBM 1 0 0 1 1 1 1 0 Subtract memory from 7 SPECIALS

Awlth borrow CMA 0 0

SUI 1 1 0 1 0 1 1 0 Subtract ImmedIate 7 STC 0 0

from A CMC 0 0

SBI 1 1 0 1 1 1 1 0 Subtract immedIate 7 OM 0 0

from A WIth borrow INPUT/OUTPUT

LOGICAL IN

ANAr 1 0 1 0 0 S S S And regIster with A 4 OUT XRAr 1 0 1 0 1 S S S ExcltJsive Or register 4 CONTROL

wIth A EI

ORAr 1 0 1 1 0 S S S Or regIster WIth A 4 01 CMPr 1 0 1 1 1 S S S Compare regIster WIth A 4 NOP ANAM 1 0 1 0 0 1 1 0 And memory WIth A 7 HLT XRAM 1 0 1 0 1 1 1 0 ExclUSive Or memory 7

wIth A

ORAM 1 0 1 1 0 1 1 0 Or memory WIth A 7 CMPM 1 0 1 1 1 1 1 0 Compare memory WIth

A 7

ANI 1 1 1 0 0 1 1 0 And Immediate With A 7 XRI 1 1 1 0 1 1 1 0 ExclUSive Or Immediate 7

wIth A

ORI 1 1 1 1 0 1 1 0 Or ImmedIate with A 7 CPI 1 1 1 1 1 1 1 0 Compare ImmedIate 7

wIth A NOTES:

1 DOD orSSS' B~OOO, C~OOl, D~OlO, E-Oll , H~lOO, L~lOl, Memory~llO, A~111.

2. Two possIble cycle times (6112) Indicate InstructIon cycles dependent on condItion flags.

'All mnemonIcs copyroght Clntel Corporallon 19n

2-9

1 1 1 1 1 1 1 1 0, 0 0 1

0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1

1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 1 1 0

Clock Operetlons Cycle.

Description 121

Rotate A lell 4

Rotate A roght 4

Rotate A lell through 4 carry

Rotate A right through 4 carry

Complement A 4

Set carry 4

Complement carry 4 DeCImal adlust A 4

Input 10

Output 10

Enable Interrupts 4 Disable Interrupt 4

No-operatlDn 4

Halt 7

..