LITERATURE In addition to the product line

LITERATURE

In addition to the product line Handbooks listed below. the INTEL PRODUCT GUIDE (no charge. Order No. 210846) provides an overview of Intel's complete product line and customer services.

Consult the INTEL LITERATURE GUIDE fora complete listing oflntelliterature. TO ORDER literature in the United States. write or call the Intel Literature Department. 3065 Bowers Avenue. Santa Clara. C A 95051. (800) 538-1876. or (800) 672-1833 (California only). TO ORDER literature from international locatiom. contact the nearest Intel sales office or distributor (see listings In the back of most any Intel lIterature).

1984 HANDBOOKS Memory Components Handbook (Order No. 210830)

Contain~

all application notes. article reprints. data sheets. and other

de~ign

information on RAMs. DRAMs. EPROMs. E2PROMs. Bubble Memorie,.

Telecommunication Products Handbook (Order No. 230730)

Contains all application

note~.

article reprinb. and data ,heel!> for telecommunication products.

U.S. PRICE*

$15.00

7.50

Microcontroller Handbook (Order No. 210918) 15.00

Contains all application notes. article reprints. data

,heet~.

and

de~lgn

Information for the MCS-48. MCS-51 and MCS-96 familIes.

Microsystem Components Handbook (Order No. 230843) 20.00

Contain~

applicatIOn notes. article reprints. data sheets. techmcal paper, for micropro-

ces~ors

and peripherab. (2

Volume~)

(Individual User Manuab are abo avaIlable on the 8085. 8086, 8088. 186, 286. etc. Consult the Literature GUide for price, and order numbers.)

Military Handbook (Order No. 210461)

Contains complete data sheets for all military products. Information on Leadless Chip Carriers and on Quality Assurance is

al~o

included.

Development Systems Handbook (Order No. 210940)

Contains data sheets on development systems and software, support options, and design kits.

OEM Systems Handbook (Order No. 210941)

Contains all data sheets, application notes, and article reprints for OEM boards and systems.

Software Handbook (Order No. 230786)

Contains all data sheets, applications notes, and article reprints available directly from Intel, as well as 3rd Party software.

*

Prices are for the U.S. only.

10.00

10.00

15.00

10.00

MICROSYSTEM

COMPONENTS HANDBOOK

'VOLUME 1

1984

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice.

, Contact your local sales office to obtain the latest specifications before placing your order.

The following are trademarks of Intel Corporation and may only be used to identify Intel Products:

BITBUS, COMMputer, CREDIT, Data Pipeline, GENIUS,' i,

f,

ICE, iCS, iDBP, iDIS, 1²1CE, iL.,BX, im, iMMX, Insite, Intel, intal, intaiBOS, Intelevision, inteligent Identifier, intaligent Programming, Intenec, Intellirik, iOSP, iPD~, iSBC, iSBX, iSDM, iSXM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MUL- TIBUS, MULTICHANNEL, MULTIMODULE, Plug-A-Bubble, PROMPT, Promware, QUEST, QUEX, Ripplemode, RMX/SO, RUPI, Seamless, SOLO, SYSTEM 2000, and UPI, and the combination of ICE, iCS, iRMX, iSBC, MCS, or UPI and a numerical suffix.

MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data

Sciences Corporation. " \

• MULTI BUS is a patented Intel bus.

Additional copies of this manual or other Intel literature may be obtained from:

@ INTEL CORPORATION. 1983

Intel Corporation Literature Department 3065 Bowers Avenue Santa Clara, CA 95051

CHAPTER 1

OVERVIEW

Table of Contents

Introduction. . . . • . . . • . • • . . . . • . . . • . . . • . . . • • . • . • • . • . . • . • • . . • • • • • • • • • • • • • 1-1

CHAPTER 2

MCP-80/85 MICROPROCESSORS

DATA SHEETS

8080Al8080A-11.8080A02, 8-Bit N-Channel Microprocessor ••••.••••.••••••• '... 2-1 8085AH/8085 AH-218085AH-1 8-Bit ,HMOS MicroproceSsors ••••••••••••.••••••••••• 2-10 8085A18085A-2 Single Chip 8-Bit N-Channel Microprocessors ...•••••••.•.••••••••• 2-26 8155H/8156H/8155H-2/8156H-2, 2048-Bit Static HMOS RAM

with I/O Ports and Timer ••.••••••••••••.•••••••••••••••••.•.••.••••••••••• ". 2-30

8155/8156/8155-218156-2,

2048-Blt Static MOS RAM with 1/0 Ports and'Timer ....•... 2-42

8185/8185-2,

1024 x 8-Bit Static RAM for MCS-85 •.•••.•..••.••••.•••.••.••••.••••. 2-45 8205 High Speed 1 OlJt of 8 Binary Decoder •.•..•.••• " • • . . • • • . . • . . • • . • • . • • . • • . . . . 2-50 8212 8-Bit Input/Output Port .••.•..•.•...•.••.•• , .. ,... 2-55

821618226,

4-Bit Parallel Bidirectional Bus Driver ••• '... 2-63

821818219

Bipolar Microcomputer Bus Controllers for MCs-aO and MCS-85 Family ... 2-68 8224 Clock Generator and Driver for 8080A CPU ..•••.•.•••••••..•.•••••.•••.•..•. 2-79

8228/8238

System Controller and Bus Driver for 8080A CPU ...•..••...•.••..•.• 2-84 8237A18237A-4/8237A~ High Performance Programmable DMA Controller... 2-88

8257/8257-5

Programmable DMA Controller •...•...••...• ". • • . • • . . • .• 2-103 8259A18259A-2/8259A-8 Programmable Interrupt Controller .•.••..•.•.•••... ,., •.... 2-120 8355/8355-2, 16,384-Bit ROM with I/O ...•...•...•..•..•..••.• 2-138 8755A18755A-2, 16,384-Bit EPROM with I/O ... 2-146

CHAPTER 3

IAPX 86, 88, 186, 188 MICROPROCESSORS

APPLICATION NOTES

AP-113 Getting Started with the Numeric Data Processor... 3-1 AP-122 Hard Disk Controller Design USing the Intel 8089 ...•... ~ . . . . • . . • . •• • . • . . • 3-62 AP-123 Graphic CRT Design Using the iAPX 86/11 ..•....•.. ^{0 • 0 0 • • 0 0} • • • • • • 0 • • 0 • • • • • 3-123 AP-143 Using the iAPX

86/20

Numeric Data Processor

in a Small Business Computer ... ⁰ . . . : , . . • . . . . . 3-194 AP-144 Three Dimensional Graphics Application of the

iAPX 86/20 Numeric Data PrOcessor ••.•••• ⁰ • • • • • • • • • • • • 0 • • • • • • • • • • • • 0 • • • • • 3-217 AP-186 Introduction to the 80186 0 0 0 0 • • 0 • • • • • • 0 • • • • • • • • • • • • • • • • • • • • • •

o. o. o.

^{0 0} • • • • • 3-256 DATA SHEETS

iAPX 86/10 16-Bit HMOS Microprocessor ^{0 0 0 ' 0 0 0 0 0 0 • • 0 0 • 0 0 • 0 0 0 • • 0 0 0 • 0 0 • 0 • 0 • 0}

o.

^{0 0 "} 3-334 iAPX 186 High Integration 16-Bit Microprocessor 0 0 ' 0 0 • 0 0 0 0 0 • 0 0 0 0 0 • 0 0 0 • • • 0 0 0 0 • 0 0 0 0 0 3-358 iAPX 88/10 8-Bit HMOS Microprocessor ^{0 0 0 0 0} 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 • o • • • 0 0 0 0 . . 3-412 iAPX 188 High Integration 8-Bit Microprocessor 0 0 • • • 0 • 0 0 0 0 0 0 0 0 0 0 • • 0 • • 0 0 • 0 0 • 0 • 0 0 0 0 0 3-439 8089 8/16-Bit HMOS I/O Processor 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • 0 • 0 0 0 0 • 0 0 0 0 0 0 0 0 0 • 0 • 0 0 ~ 0 0 0 •

o.

^3-494

8087 Numeric Data Coprocessor 0 0 • • 0 " 0

o.

^{0 0 " 0} • • • • • • • • 0 " 0 • • 0 0 ~ ⁰ . . . 0 • • • • 3-508 80130/8013(}'2 iAPX 86/30, 88/30, 186/30, 188/30 iRMX 86 . '

Operating System Processors ^{0 • • 0 • • • 0} • • : . 0 . 0 . 0 • • 0 0 . 0 . . . . 0 • • 0 0 . 0 • • : 0 • • • • • • • • • 3-529 80150/8015(}'2 iAPX 86/50, 88/50. 186/50,

188150

CPlM*-86 '

Operating System Proc:essors ... ^{0 0 0 0 0 • 0} • • • • • • • 0 • 0 0 : 0 • • • • • 0 • • 0 • 0 • ' . ' . 0 • • •

o.

3-551 828218283 Octal Latch . 0 • • 0 • • • • 0 • • • ~', • • • • • • 0 • • • • • • • • • • • • • • ' . 0 • • • • • • • • • • • • • • • • • • • • 3-562 82~Al8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors 0 • • • • 0, • • • • • •

o.

3-567 8286/8287 Octal Bus Transceiver ... ⁰ . . . ~ ^{. . . .} , : . . . ' . . . : . . . . 3-575 8288 Bus Controller for iAPX 86, 88 Processors . 0 . . 0 • • • • 0 . . 0 0 • • • 0 • • • • 0 . . . o . 3-580 8289/8289-1 Bus Arbiter 0 0 . 0 0 • • • • • 0 , ' 0

o.

0 ' , • • • • 0 ; • • 0 0 . . . 0 • • 0 . ' • • • • • 0 " 0 " , ' 0 "

o. o.

3-587

CHAPTER 4

IAPX 286 MICROPROCESSORS

, DATA SHEETS

iAPX 286/10 High Performance Microprocessor • ,

with Memory Management and Protection .... ^{0 0 0} . . . o . . . ' • • • • 0 . . . 0 . : . 0 . . 4-1 80287 80-Bit HMOS Numeric Processor Extension .. 0 0 0 0 • • • • • 0 • • 0 0 • • 0 • • 0 • • • • • • • • • • • 4-52 82284 Clock Generator and Ready Interface for iAPX 286 Processors ^{o • •} 0 0 • • • • • • • • 0 " 4-76 82288 Bus Controller for iAPX 286 Processors

o.

⁰ • • • • • • • • 0 • • • 0 • 0 • • • • • • • • • • • • • • 0 • • 0 • 4-83 'CP/M-S6 is a Trademark of Digital Research.,1nc,

CHAPTERS

IAPX 432 MICROMAINFRAME™

DATA SHEETS

iAPX 43201/43202 Fault Tolerant General, Data Processor ...•... ,: : .... . iAPX 43203 Fault Tolerant Interface, Processor •... " ...••. ',' ... . iAPX 43204/43205 Fal!It''rolerant 'aus Interface and Memory Control Units ... .

CHAPTER 6

MEMORY CONTROLLERS APPLICATiON NOTES

5-1 5-53 5-85

AP-97A Interfacing Dynamic RAM to 'IAPX' 86/88 Using the 8202A & 8203 ..•...•... 6-1 AP-141 8203/8206/2164A Memory Design':... ... ...•. 6-37 AP-167 Interfacing the 8207 DYnamic RAM Controller to the iAPX 186 ..•... 6-43 AP-168 Interfacing the 8207 Advanced Dynamic RAM Confroller to' the iAPX 286 ... 6-48 ARTICLE REPRINTS

AR'-231 Dynamic RAM Controller Orchestrates Memory Systems ...•...•... 6-55

TECHNICAL PAPERS ' '

System Oriented RAM Controller' ...• : • . . . 6-62 , NMOS DRAM Controller ... :... 6-73 DATA SHEETS

8202A Dynamic RAM Controller ... ~ ... ~ .. ; .... ; . . . 6-77 8203 64K Dynamic RAM Controller .... , . ',' . . . . .. . . • . . . • . . . • . . 6-91 82C03 CMOS 64K Dynamic RAM Controller ...• ," 6-106 8206/8206-2 Error Detection and Correction Unit ...•... 6-119 8207 Advanced Dynamic RAM Controller .... :. ' .... , ... : . . . .. 6-152 8208 Dynamic RAM Controller ... , ... ' ...•.. 6-199 USERS MANUAL

Introduction ... : ... '; ... ::: ... 6-218 Programming the 8207 ....•. : ... ' ... .' ...•.... 6-219 RAM Interface ... : ... ::' ...•... ; ... 6-224 Microprocessor Interfaces ...•... : ...•.... 6-233 8207 with ECC (8206) ... : ... ,... 6-241 Appendix, .... : ... : ...• ' ...•... 6-244

SUPPORT PERIPHERALS APPLICATION NOTES

-VOLUME2-

, AP-153 DeSigning with the 8256 ... 6-248

DATA SHEETS ' ,

8231 A Arithmetic processing Unit ... 6-321 8253/8253-5 ProgrammablE! Interval Timer ...•... 6-331 8254 Programmable Interval Timer ... ' .. ' ... 6-342 8255A18255A-5 Programmable Peripheral Interface ... 6-358 8256AH Multifunctional Universal Asynchronous Receiver Transmitter (MUART) ... 6-379 8279/8279-5 Programmable Keyboard/Display Interface ... ; • . . . .• 6-402 82285 Clock Generator and Ready Interface for I/O Coprocessors ... 6-414 FLOPPY DISK CONTROLLERS '"

APPLICATION NOTES

AP-116 An 'Intelligent Data Base System Using the 8272 ... , ...•... 6-421 AP~121 Software Desigriand Implementation of Floppy Di'sk Systems ... 6-455 DATA SHEETS

8271/8271-6 Programmable Floppy Disk Controller ... , ...•.•... 6-524 8272A Single/Double Density Floppy Disk Controller ...•... 6-553 HARD DISK CONTROLLERS

DATA SHEETS , ,

82062 Winchester Disk Controller ... : ... '." . : : . . .. . . .. .. . . .. 6-572

i I

Introduction •...•...•... '6-598 Functional Description ... ,... 6-602 Instruction Set ...•...•... 6-619 Single-Step, Programming, and Power-Down Modes ... 6-646 System Operation ...•.•..•...•.•...•... 6-651 Applications . ~ . . . • . • . . . • . • . . . .. 6-657 DATA SHEETS

8041A18641A18741A Universal Peripheral Interface 8-Bit Microcomputer ...•.. 6-777 8042/8742 Universal Peripheral Interface 8-Bit Microcomputer •... : ... 6-789 8243 MCS-48 InpuVOutput Expander ... ; . . . .. 6-803 8295 Dot Matrix Printer Controller .• . . . • . . • . . • . . . • . . . .. 6-809 SYSTEM SUPPORT

ICE-428042 In-Circuit Emulator ... : ...•... 6-818 MCS-48 Diskette-Based Software Support Package .... . . • . . . .. 6-826 iUP-2oo/iUP-201 Universal PROM Programmers ...•...•... 6-828

CHAPTER 7

DATA COMMUNICATIONS INTRODUCTION

Intel Data Communications Family Overview ...•.. 7-1 GLOBAL COMMUNICATIONS

APPLICATION NOTES

AP-16 Using the 8251 Universal Synchronous/Asynchrono'us Receiver/Transmitter. . . . 7-3 AP-36 Using the 8273 SDLC/HDLC Protocol Controller... 7-33 AP-134 Asynchronous Communications with the 8274 Multiple Protocol

Serial Controller ... 7-79 AP-145 Synchronous Communications with the 8274 Multiple Protocol

Serial Controller ... '... ... ... .... ... .. . .. ... 7-116 DATA SHEETS

8251A Programmable Communication Interface ... :... 7-155 8273/8273-4 Programmable HDLC/SDLC Protocol Controller ... 7-172 8274 Multi-Protocol Serial Controller (MPSC) ... 7-200 82530/8253-6 Serial Communications Controller (SCC) ... 7-237 LOCAL AREA NETWORKS

ARTICLE REPRINTS

AR-186 LAN Proposed for Work Stations ... : . . . .. 7-266 AR~237 System Level Fu!,)ctions Enhance Controller ... 7-272 DATA SHEETS

82501 Ethernet Serial Interface ... 7-276 82586 Local Area Network Coprocessor ... 7-287 OTHER DATA COMMUNICATIONS

APPLICATION NOTES

AP-66 Using the 8292 GPIB Controller ... \ ... 7-322 AP-166 Using the 8291 A GPIB Talker/Listener ... : •... 7-375 ARTICLE REPRINTS

AR-208 LSI Transceiver Chips Complete GPIB Interface. . . .. 7-407 . AR-113 LSI Chips Ease Standard 488 Bus Interfacing ... ,... 7-414 TUTORIAL

, Data Encryption Tutorial ... .'... 7-424 DATA SHEETS

8291A GPIB Talker/Listener ... 7-425 8292 GPIB Controller ... 7-454 8293 GPIB Tranceiver ... ; ...•... 7-469 8294A Data Encryption Unit ... :... 7-481

CHAPTER 8

ALPHANUMERIC TERMINAL CONTROLLERS APPLICATION NOTES

AP-62 A Low Cost CRT Terminal Using the 8275 .,. '" . . .. . . .. ... . . .. ... .. . .. 8-1 ARTICLE REPRINTS

AR-178 A Low Cost CRT Terminal Does More with Less... 8-43 DATA SHEETS

8275 Programmable CRT Controller ... 8-50 8276 Small System CRT Controller ... :... 8-74 GRAPHICS DiSpLAY PRODUCTS

ARTICLE REPRINTS

AR-255 Dedicated VLSI Chip Lightens Graphic Display Design Load ... 8-91 AR-298 Graphics Chip Makes Low Cost High Resolution. Color Displays Possible .... 8-99 DATA SHEETS

82720 Graphics Display Controller ... 8-106 TEXT PROCESSING PRODUCTS

ARTICLE REPRINTS

AR-305 Text Coprocessor Brings Quality to CRT Displays ... 8-144 AR-296 Mighty Chips ... 8-151 AR-297 VLSI Coprocessor Delivers High Quality Displays ... ' ... , .. 8-156 DATA SHEETS

82730 Text Coprocessor ... : .•... 8-159 82731 Video Interface Controller ...•... 8-199

CHAPTER 9

PACKAGING 9-1

Overview 1

Intel microprocessors and peripherals provide a complete solution in increasingly complex application ellviran- ments. Quite often, a single peripheral device will replace anywhere from 20 to 100 TIL devices (and the a:ssociated design time that goes with them).

Built-in functions and,a standard Intel microprocessor!

peripheral interface deliver very real time and per/or- mance advantages to the designer of microprocessor- based systems.

. REDUCED TIME TO MARKET

i

When you can purchase an off-the-shelf solution that replaces a number of discrete devices, you're also re- placing aU the design, testing, and debug time that goes

with them. '

INCREASED RELIABILITY

At Intel, the rate offailure for devices is carefuJly tracked.

Reliability is a tangible goal, and today we're measuring field failures in terms of parts per million/ That translates to higher reliability for your product, reduced downtime, and reduced repair costs. And as more and more func- tions are integrated on a single VLSI device, the resulting system requires less power, produces less heat, and requires fewer mechanical connections-again resulting in greater system reliability. '"

LOWER PRODUCT COST

By minimizing design time, increasing reliability, and

solutions can contribute dramaticaUy to a lower product cost.

HIGHER SYSTEM PERFORMANCE

Intel microprocessors ,and peripherals provide the highest system performance for the demands of today's (and' tommorrow's) microprocessor-based applications. For example, the iAPX 286 CpU, with its on-chip memory management and protection, offers

th~

highest perfor- mance for multitasking,' multiuser systems .

HOW TO USE THE GUIDE

The foJlowing application guide illustrates the range of microprocessors and peripherals that can be used for the applications in the vertical column on the left. The peri- pherals are grouped by the I/O function they control:

CRT, datacommunication, universal (user programma- ble). mass storage, dynamic RAM's, and CPU/bus support.

An "X" in a horizontal application row indicates a poten- tial peripheral or CPU, depending upon the features desired. For example, a conversational terminal could use either of the three display controUers, depending upon features like the number of characters per row or font capability. A "Y" indicates a likely candidate, for example, the 8272A Floppy Disk ControUer in a smaJl business computer.

The Intel microprocessor and peripherals family provides a broad range of time-saving, high performance solutions.

1-1

....

~

POTENTIAL CANDIDATE X-TYPICAL CANDIDATE Y

"PROCESSOR DISPLAY DATACOMM UPI DISKS DRAM CONTROL SUPPORT

t')

APPLICATION ,~ ~ ~ .... C\I

CD ~ ~ ~

;! r!

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coco l O C \ I ( ' ) . . . - < 0 ( 1 ' ) " " " , . . . . ( 1 ) ( 1 ' ) ( 1 ) " " " N N i C O (f')CO ... CO...,.. 1 1 ) , . . . CD CD co U) U) I'- I'- I'- It) It) I'- I'- ' " It) It) It) .... .... I'- 0 0 0 0 0 It) It) t')' O O C O C D CDC\IC\IC\I C \ l C \ I C \ I C \ I C \ I C \ I C \ I C \ I O O C \ l C \ l C\I'C\IC\IC\IC\I C\I C\I

co CD,... or- C\I co CD co co CI) CD.COCO ex) ex) CD CD Q) co CD co co CD co CD co-co

PERIPHERALS I ,I I I I I I I I I I I I I .

Printers

Plotters

I X I X I X I X I I I I I X I I I I X I TTT xl x'l T T l I I I I X I

Keyboards

,MASS STORAGE I I ,I I I T I I I I I I I T 'T T I T I I I I I I I I

Hard Disk

Mini Winchester

Ixi Ivi I L I I I I I I I I 1 I I '·Iv

Tape

Cassette I I I I

t x T X

Floppy/Mini

COMMUNICATIONS I I I· I I I I I I I I I I I I I r I

PBX

LANS

IXIXIXIXI I I I I I IXI IX X V X X

Modems

Bjsync,

11·.11 I I X X X X"

SOlC/HOlC

Serial BackPlane

I I I· I I T X X X X X

Central Office

Network Control

V I IX IV X X X X X X

OFFICE/BUS

Copier/FAX

Word Processor

X xlVIVlvl X V X X X V X X X X y Y

Typewriter

Elect. Mail

XIXIXI X V

X.

X X X

Transaction System

Data Entry'

X X I ^X I ^X I X ,X X X X X X . X V

COMPUTERS

. SM Bus Computer

~

IYI XIVIXIXIX Y Y X X xlxlxTxTx

xlxTvlvlxlxlX~X '~Yr

Portable PC

Home Computer

lX X I X I X I X I X X X I X V X X Yi V

"PROCESSOR DISPLAY DATACOMM UPI DISKS DRAM CONTROL SUPPORT

'"

APPUCATION ;;; ~

0

~ ~

w

~

m

~ ~ ~

~

0 0 < <

^{0 ~}

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^~

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N

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cow CO COco CO w~~~~~~~m~~~ ~N"'~W"''''~''''''CO'''NNW'''CO~CO''' ~ ... ~olQooo ~ ~ ~ '"

ii~~ t!3~~~~~~~~~~~ii~~~~~~ ~ ~ ~

TERMINALS

I r

Conversational

Graphics CRT I I V I V I V I I Y I V I X I X I X I I X I I X X I X I X I X X I X I V I V

I I I

Editing

Intelligent

L

X

LX

V V I .

I

Y X X

J

X I I X I X I X X I X I I X I X I Y I V I X I I Videotex

Printing. Laser. Impact I X I X X I X I I I X I X I X I I I I I I X X X I I I I V I Y I I I Portable

INDUSTRIAL AUTO

J

Robotics

Network X X X X X XX X X X V X

I

Num Control

Process Control X X X X X V .X X X X Y X

I

X X X X

Instrumentation

AVlationlNavig X X X X X X ~

x

~

INDUST/DATA ACQ

Laboratory Instr /

Source Data X

I I

X

I I I I I I I J I J J I I

V J

J J I I

I I J

J

XJ Auto Test

Medical XIXIXIXIXI IVI I I I I I I I IX VIXI I I I I I I IXIX

Test Instr

Secunty I X X X X VX I X

COMMERCIAL DATA

PROCESSING I I I I I

J

I

POS Terminal

Financial Transfer I I X X X X X X X X X V X X

Automatic Teller

Document Processing X X X X X X X X X X V X

WORKSTATIONS _

Office / . . . .

Engineering x I x x x x y ~ X ^{~ ~ ~ ~} X y Y ~ ~ ~ ~ ~ x

CAD

MINI MAINFRAME I I I I

J

Processor & Control store

DatabaseSubsys

I

IXI IVIX XI I I I

I I I I

IXI I I

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I I I~I~I I I I I I 1/0 Subsystem _

Com",. Subsystem

I

X

I

V

I

V

I I I I

X

I I. I

X

I I

X

I

X

I

X

I I I I I

X

I I I I I I

•

MCS®...sO/85 Microprocessors

. Microprocessors

!

Section

2

"

I.' .[

~ " ,,'(,1/1',"

.",.:

..

.

8080A/8080A·1/8080A·2 '

8·BIT N·CHANNEL MICROPROCESSOR

• TTL Drive Capability

• 2 /AS ( - 1 :1.3 /AS; - 2:1.5 /As) Instruction Cycle

• 16·Bit Stack Pointer and Stack Manipulation Instructions for Rapid Switching of the Program Environment

• Powerful Problem Solving Instruction

Set .

• Decimal, Binary, and Double Precision Arithmetic

• 6 G~meral Purpose Registers and an • Ability to Provide Priority Vectored

Accumulator. Interrupts

• 16.Bit Program Counter for Directly - 512 Directly Addressed 1/0 Ports Addressing up to 64K Bytes of • Available in EXPRESS

Memory - Standard Temperature Range

The Intel® 8080A is a complete 8-bit parallel central processing unit (CPU). It 'is fabricated on a single LSI chip using Intel's n-channel silicon gate MOS process. This offers thil user a high performance solution to control and processing applications.

The 8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose registers may be addressed individually or in pairs providing both single and double precision operators\Arithmetic and logical instructions set or reset 4 testable flags. A fifth flag provides decimal arithmetic operation.

The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/retrieve the contents of the accumulator. flags. program counter. and all of the 6 general purpose registers. The 16-bit stack pointer controls the addressing of this external stack. This stack gives the 8080A the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting .

This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line bidirectional data busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to rT)emory and I/O are provided directly by the 8080A. Ultimate control of the address and data busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits OR-tying these busses with other contrOlling devices for (DMA) direct memory access or multi-processor operation.

NOTE:,

The 8080A is functionally and electrically compatible With the Intel® 8080.

BmJ~fC~l"oNAL

DATA BUS

Figure 1. Block Diagram

2-1

A"

A"

A"

A12

As A,

a080A A,

+12V A, A, Ao WAIT READY

"

21 HUlA

Figure 2. Pin Configuration

inter 8080Al8080A·1/8080A·2 Table, 1. Pin Description

'Symbol ~pe. Name alldFunction

A,s-Ao 0 Address Bus: The address bus provides the address to memory (up to 64K 8-bit words) or denotes the 1/0 device number for up to 2/i6 input and 256 output devices. Ao IS the least sIgnificant address bit DrDo ^1/0 Data Bus: The data bus prOVIdes bi-directional communicatIon betweeen thl! CPU, memory, and 1/0

devices for instructions and data transfers. Also, during the fi,st clock cycle of each machine cycle, the a080A outputs a status word on the data bus that describes the current machine cycle. Do is the least SIgnifIcant bit '

SYNC 0 Synchronizing Sign~l: The SYNC pin provides a SIgnal to indicate the beginning of each machine cycle.

DBIN 0 Data Bus In: The DBIN signal indicates to external CIrcuits that the data bus is In the input mode. ThIS signal should be used to enable the gating of data onto the 8080Adata bus from memory or,I/O.

READY I Ready: The READY signal Indicates to the 8080A that valid memory or Input data is avaIlable dn the 8080A data bUS. ThIS signal is used to synchrOnize the CPU with slower memory or 1/0 devices. If after sending an address out the 8080Adoes not receIve a R~ADY Input, the 8080Awill enter a WAITstate for as long as the READY hne is low. READY can also be used to Single step the CPU

WAIT 0 Wait: The WAIT signal acknowledges that the CPU IS In a WAITstate.

WR 0 Write: The WR signal is used for'memory WRITE or 1/0 output control. The data on the data bus is stable while the WR signal is active low (WR

=

0).

HOLD I Hold: The HOLD Signal requests the CPU to enter the HOLD state. The HOLD state allows an external device to gain control of the 8080A addressand data bus as soon as the 8080A has completed its use of these busses for the current machine cycle. It is recognized under the following condItIons:

• the CPU is in the HALTstate.

• the CPU is in. the T2 or TW state and the READY signal is active. As a result of entering the HOLD state the CPU ADDRESS BUS (A,s-Ao) and DATA BUS (07-00) will be in their high Impedance state. The CPU acknowledges ItS state with the HOLD ACKNOWlEDGE (HLDA) pin.

HLDA 0 Hold Acknowledge: The HLDA signal appears in response to the HOLD signal and indicates that the data and address bus will go to the, high impedance state. The HLDA signal begins at:

• T3 for READ memory or Input

• The Clock Period following T3 for WRITE memory or OUTPUT operation,

•

In either case, the HLDA signal appears after the rising edge of <1>2'

INTE 0 Interrupt Enable: Indicates the content of the Internal interrupt enable flip/flop. ThIS fliplflop may be set or reset by the Enable and Disable Interrupt instructions and inhibits interrupts from being accepted' by the CPU when it is reset It is automatically reset (disabling further interrupts) at time T1 of the instruction fetch cycle (Ml) whe~ an interrupt is accepted and IS also reset by the RESET sIgnal.

INT I Interrupt Request: The CPU recognizes an interrupt request on this line at the end of the current instruction or while halted. If the CPU is in the,HOLD state or if the Interrupt Enable fllplflop is reset it will not honor the request

RESET' I Reset: While the RESET sIgnal IS activated, the content of the program counter IS cleared. After RESET, the program will start at locatIon 0 in memory. The INTE and HLDA fliplflops are also reset Note that the flags, accumulator, stack pOinter, and regIsters are not cleared.

Vss

Gro.und: Reference.

Voo

Power: +12 ±5% Volts.

Vee

Power: +5 ±5% Volts

Vee

Power: -5 ±5% Volts.

<1>1. <1>2 Clock Phases: 2 externally supplied.clock phases. (non TTL compatIble)

2-2 AFN·OO735C

ABSOLUTE MAXIMUM RATINGS·

'Temperature Under Bias . . . O°C to +70° C Storage Temperature " . . . _65°C to +150°C All Input or Output Voltages

With Respect to VBB ... -0.3V to +20V Vcc. VD D and Vss With Respect to VBB -0.3V to +20V Power Dissipation . . . . .. . . . 1.5W

-NOTICE:

Stresses

above those listed under "Absolute Maximum Ratings" may cause permanent damage to the d.evice. This is

a stress

rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operational sections of this specification is not, implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. ,

D.C. CHARACTERISTICS

(TA

=

O°C to 70°C. Voo

=

+12V ±5%.

Vee = +5V ±5%. Vee = "":5V ±5%, Vss =OV; unless otherwise noted) Test Conditior

} IOL ; 1.9mA on all outputs.

~--~--+---~---r---+----r---r--~ IOH=-l50~A.

~~~-+---1-~---+~-+~~1---~

} Operation f-~::::...::~:...t--=---='-=--+---t----il----t--- Tcy;.48 f.lS~c

~~~-+---~--1---+---+----1---

CAPACITANCE

(TA = 25'C. VCC = VOO =VSS = OV. Vee = -5V) Symbol Parameter Typ. Max. Unit Test Condition Cq, Clock Capacitance 17 25 pf tc ~ 1 MHz CIN I nput Capacitance 6 10 pt Unmeasured Pins COUT Output Capacitance 10 20 pt Returned to Vss NOTES:

1. The RESET signal must' be active for a minimum of 3 clock cycles.

2. <lol supply / <loT A = -0,45%f c,

2-3

'5

Vss .;; VIN .;; VCC Vss .;; VCLOCK .;; VOD Vss';;VIN';;Vss+O.8V Vss+O.8V';;VIN';;V

c

^C

VADDR/DATA ~ VCC VADDR/DATA

=

Vss + 0.45V

I, I

'O~~

050.'---::'2::-5 ---+750:----+:::75 AMBIENT TEMPERATURE rei Typical Supply Current vs.

Temperature, Normalized(3)

AFN·00735C

8080Al8080A·1/8080A·2

A.C. CHARACrERISTICS (8080A)

(TA = O°C to 70°C, VDD = +12V ±S%, Vee = +SV ±S%, Vee '= -SV :±;S'l-:'., Vss =OV; unless otherwise noted)

.1 .~

Symbol Parameter Min. Max. Min. Max.

tCy[3] Clock Period 0.48 2.0 0.32 2.0

tr,tf Clock Rise and Fall Time 0 50 0 25

t"'l "'1 Pulse Width 60 50

t"'2 "'2 Pulse Width 220 145

tDl Delay "'1 to "'2 0 0

tD2 Delay "'2 to "'1 70 60

tD3 Delay "'1 to "'2 Leading Edges 80 60

tDA Address Output Delay From "'2 200 150

too Data Output Delay From "'2 220 180

tDC Signal Output Delay From ¢1 or "'2 (SYNC, WR, WAIT, HLDA) 120 110

tDF DBIN Delay From "'2 25 140 25 130

tDI[I] Delay for Input Bus to Enter Input Mode tDF tDF

tDSl Data Setup Time During "'1 and DBIN 30 10

tDS2 Data Setup Time to "'2 During DBIN 150 120

tDH[I] Data Holt time From "'2 DUring DBIN [I] [I]

tiE INTE Output Delay From "'2

,

200 200

tRS READY Setup Time During "'2 120 90

tHS HOLD Setup Time to "'2 140 120

tiS INT Setup Time During "'2 120 100

tH Hold Time .from "'2 (READY, INT, HOLD) 0 0

tFD Delay to Float During Hold (Address and Data Bus) 120 120'

tAW Address Stable Prior to WR [5] [5]

tow Output Data Stable Prior to WR [6] [6]

two Output Data Stable From WR [7] [7]

tWA Address Stable From WR [7] [7]

tHF H LOA to Float Delay [8] [8]

tWF WRlo Float Delay [9] [9]

tAH Address Hold Time After DBIN During HLDA, - 20 -20

A.C.

TESTING LOAD CIRCUIT

DEVICE ^UNDER _TEST

In, _I

'-____ -' I

CL ~ 100 pF

CL 100 pF

CL INCLUDES JIG CAPAClTANCE

2-4

·2 ·2

Min. Max. Unit Test Condition 0.38 2.0 /-Isec

0 50 nS,ee

60 nsec

175 nsec

0 nsec

70 nsec

70 nsec

175 nsec

}CL=100 PF 200 nsec

I 120 nsec

} CL=50 pF 25 140 nsec

tDF nsec

~

20 nsec

130 nsec [I] nsec

200 nsec CL=50 pF

90 nsec

120 nsec

100 nsec

0 nsec

120 nsec

[5] nsec

-

[6] nsec [7] nsec

[7] nsec CL = 100 pF: Address, Data CL = 50 pF: WR,HLDA,DBIN

[8] nsec

[9] nsec

-20 nsec

-

^I

AFN-00735C

inter 8080A/8080A·1/8080A·2 WAVEFORMS

0, _ _ _ _ ..J

9,

---'I-~

A'5 AO ---1--~

SYNC ...

- - - 1 - - ' 1

DBIN ____________________________ +--JI

READY

HOLD

INTE

NOTE:

Timing measurements lire made at the following reference voltages: CLOCK "1" = B.OV,

"0"

=

1.0V; INPUTS "1"

=

3.3V, "0"

=

O.BV; OUTPUTS "1"

=

2.0V, "0"

=

O.Sv.

2-5 AFN·OO735C

! \

WAVEFORMS (Continued)

.,

'.

A1IIAe I

0,,00 SYNC

OBIN

1111

READY

WAIT

HOLD

...

HLDA

INT I -

INTE I

·,.,', '\'

NOTES: (Parenthesis gives -1. -2 speclflcatiql)~. ~~C\t!\(eM,!

2-6

1. Data Input should be enabled with'OBIN status. No bus con- flict can then occur and data hold time Is assured.

tOH = 50 ns or tOF. whichever is less.

2. tCY = tD3 + trt/>2

-l;\f,2

+ tft/>2 + t02 + tr.,,1 .. 480 ns ( - 1 :320 ns • ..: 2:380 ns).

TYPICAL A OUTPUT DELAY VS. A CAPACITANCE

!

>

~ Q

I .,

• CAPACITANCE (pI) (C4CTUAL -CSflECJ

+100

3. The followthg are relevant when intertacif)g the 8080A to devices having VIH = 3.3V: "

a) Maximum output rise time from

.av

to 3.3V = 100ns @ CL

= SPEC.

b) Output delay when measured to 3.0V = SPEC +80n8@CL

= SPEC.

c) If CL = SPEC. add .6nalpF if CL

>

CSPEC. subtract .3nalpF (from modified delay) If CL < CgPEC'

4. tAW = 2 tCY- too - trt/>2 - 140 ns ( - 1 :110 ns. - 2:130 ns).

5. tow = tCY - tD3 - trt/>2 - 170 n8 ( - 1:150 ns. -; 2:170 n8).

6. If not HLDA. two = twA = t03 + tr<f>2 + 10 ns. If HLDA. two

= tWA = tWF·

7. tHF = tD3 + trt/>2 -50 ns).

a.

tWF = too + tr.,,2 - IOns.

9. Data Ifi must be stable for this period during DBIN T3' Both tOS1 and tOS2 must be satisfied ..

10. Ready signal must be stable for this period during Ta or Tw.

(Must be externally synchronized.)

11. Hold signal must be stable for this period during T 2 or TW when entering hold mode. and during T3. T4. Ts and TWH

\\(hen in ·hold mode. (External synchronization is not re- qUired.)

12. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be recognized on the following instruction. (Extemal synchronization is not re-

quired.) •

13. This timing diagram shows timing relationships only; it does not represent any spe!lific machine cycle.

AFN·OO735C

INSTRUCTION SET

The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate ad- dressing modes_

Move, load, and store instruction groups provide the ability to move either 8 or 16 bits of data between memory, the six working registers and the accumulator using direct, in- direct, and immediate addressing modes_

The ability to branch to different portions of the program is provided with jump, jump conditional, and computed jumps_ Also the ability to call to and return from sub- routines is provided both conditionally and unconditionally_

The RESTART (or single byte call instruction) is useful for interrupt vector operation_

Double precision operators such as stack manipulation and double add instructions extend both the arithmetic and interrupt handling capability of the 8080A_ The ability to

Data and Instruction Formats

increment and decrement memory, the six general registers and the accumulator is provided as well as extended incre-.

ment and decrement instructions to operate on the register pairs and stack pointer. Further capability is provided by the ability to rotate the accumulator left or right through or around the carry bit.

Input and output may be accomplished using memory ad- dresses as 1/0' ports or the directly addressed I/O provided for in the BOBOA instruction set.

The following special instruction group completes the BOBOA instruction set: the NOP instruction, HALT to stop pro- cessor execution and the DAA instructions provide decimal arithmetic capability. STC allows the carry flag to .be di- rectly set, and the CMC instruction allows it to be comple- mented. CMA complements the contents of the accumulator and XCHG exchanges the contents of two 16-bit register pairs directly.

Data in the BOBOA is stored in the form of B-bit binary integers. All data transfers to the system data bus will be in the same format.

I

D7 D6 D5 D4 D3 D2 D, Dol DATA WORD

The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored in successive words in program memory. The instruction formats then depend on the particular operation executed.

One Byte Instructions· TYP!CAl INSTRUCTIONS

I

D7 D6 D5. D4 D3 D2 D1YDl OP CODE Register to register, memory refer- ence, arithmetic or logical, rotate, return, push, pop, enable or disable Interrupt instructions

Two Byte Instructions

I

D7 D6 D5 D4 D3 D2 D, Do

I

^{OP CODE}

I

D7 D6 D5 D4 D3 D2 D, Do

I

^OPERAND Immediate mode or I/O instructions Three Byte Instructions

I

D7 D6 D5 D4 D3 D2 D, Do

I

^{OP CODE} Jump, call or direct load and store

I

D7 D6 D5 D4 D3 D2 D, Do

I

lOW ADDRESSOR OPERAND 1 instructions

I

D7 D6 D5 D4 D3 D2 .D, Do

I

HIGH ADDRESS OR OPERAND 2

For the B080Aa logic "1" is defined as a high level and a logic "0" is defined as a low level.

2-7

AFN·00735C

8080Al~80A.1'8080A.2

Table

2~

Instruction Set Summary

Clock ClOck

In .. ructlon Coda [1] Operellons CycIaa Inelrucllan Code [1) Operation. Cyclea MnanIcInIc 0,.

De

Ds D4

D:!

D:z Dl

Do

Description (2) Mnemonic 0,.

De

Ds D4

D:!

D:z Dl

Do

Daecrlpt,on [2)

MOVE, LOAD. AND

STORE'

^JPO 1 1 1 0 0 0 1 0 Jump on parity ~ 10

MOVr1,r2 0 1 D D 0 ,S S S Move register to register 5 PCHL 1 1 1 0 1 0 0 1 H & L to program 5

MOVM,r

9

1 1 1 0 S S S Move register to counter

memory 7 CALI.

MOVr,M 0 1 0 0 0 1 1 0 Move memory to regis-

ter 7

CALL 1 1 0 0 1 1 0 1 Call unconditional 17 bc 1 1 0 1 1 1 0 0 Call on carry 11/17 MYlr 0 0 0 0 0 1 1 0 Move Immedlste regis- ONC 1 1 0 1 0 1 0 0 Call on no carry 11/17

ter 7 CZ 1 1 0 0 1 1 0 0 Call onzaro 11/17

MVIM 0 0 1 1 0 1 1 0 Move immediate ONZ 1 1 0 0 0 1 0 0 Call on no zarO 11/17

memory 10 CP 1 1 1 1 0 1 0 0 ,Call on positive 11/17

LXIB 0 0 0 0 0 0 0 1 Load Immediate register 10 CM 1 1 1 1 1 1 0 0 Call on minus 11/17

PairB&C CPE 1 1 1 0 1 1 0 0 Calion partty even 11/17

LXI 0 0 0 0 1 0 0 0 1 Load immediate register 10 CPO 1 1 1 0 0 1 0 0 Call on parity odd 11/17

PalrO&E RETURN

LXIH 0 0 1 0 0 0 0 1 Load Immedlste register 10 PairH&L

STAXB 0 0 0 0 0 0

i

0 Store A Indirect 7

RET 1 1 0 0 1 0 0 1 Raturn 10

RC 1 1 0 1 1 0 0 0 Ratu," on carry 5/11 RNC 1 1 0 1 0 0 0 0 Return on no carry 5/11 STAXO 0 0 0 1 0 0 1 0 Store A indirect 7 RZ 1 1 0.0 1 0 0 0 Return on zaro 5/11 LDAXB 0 0 0 0 1 0 1 0 Load A Indirect 7 RNZ 1 1 0 0 0 0 0 0 Return on no zaro 5/11 LOAXO 0 0 0 1 1 0 1 O. Load A Indirect 7 RP 1 1 1 1 0 0 0 0 Return on positive 5/11' STA 0 0 1 1 II 0 1 0 Store A direct 13 RM 1 1 1 1 1 0 0 0 Return on minus 5111 LOA 0 0 1 1 1 0 I, 0 Load A direct 13

SHLO 0 0 1 0 0 0 f 0 Store H & L direct 16

RPE 1 1 1 0 1 0 0 0 Return on parity even 5111 RPO 1 1 1 0 0 0 0 0 Raturn on DaritY odd 5111 lHLD 0 0 1 0 1 0 1 0 Loed H & L direct 16 RESTART

XCHG 1 1 1 0 1 0 1 1 Exchange 0 & E, H & L 4 RST 1 1 A A A 1 1 1 Restert 11

Registers INCREMENT AND IlliCRIOMENl

STACKOPS INRr 0 0 0 0 0 1 0 0 Increment register 5

PUSHB 1 1 0 0 0 1 0 1 Push register Pair B & 11 OCRr 0 0

o

0 0 1 0 1 Decrement register 5

Con stack INRM

o

0 1 1 0 1 0 0 Increment memory 10

PUSH 0 1 1 0 1 0 1 0 1 Push register Pair 0 & tl DCRM 0 0 1 1 0 1 0 1 Decrement memory 10' E on steck INxa 0

o

0 0 0 0 1 1 Increment B & C " 5

PUSHH 1 1 1 0 0 1 0 1 Push register Pair H & 11 registers

Lon steck INXO 0 0 0 1 0 0 1 1 Increment 0 & E 5

PUSH 1 1 1 1 0 1 0 1 Puah A and Flags 11

PSW on steck I _INXH 0 0 1 0 0 0 1 1 Increment H & L ^registers 5

POPB 1 1 0 0 0 0 0 1 Pop register Pair B & 10 registers

C olf stack DCXB 0 0 0 0 1 0 1 1 Decrement B & C 5

POP 0 1 1 0 1 0 0 0 1 Pop register Palr 0 & 10 Eolf steck

DCXO 0 0 0 1 1 0 1 1 Decrement 0 & E_ 5 DCXH 0 0 1 0 1 0 1 1 Decrement H & L 5 POPH 1 1 1 0 0 0 0 1 Pop reglst~r Pair H & 10

L olf steck

ADD

ADDr 1 0 0 0 0 S S S Add register to A 4 POPPSW 1 1 1 1 0 0 0 1 Pop A and FIll!/' 10

off steck

Acer 1 0 0 0 1 S S S Add register to A 4 with carry

XTHL 1 1 1 0 0 0 1 1 Exchange top of 18 ADOM 1 0 0 0 0 1 1 0 Add memory to A 7

stack, H& L ADCM 1 0 0 0 1 1 1 0 ,Add memory to A 7

SPHL 1 1 1 1 1 0 0' 1 H & L to stack pointer 5 with carry

LXISP 0 0 1 1 0 0 0 1 Load Immediate steck 10 AOI 1 1 0 0 0 1 1 0 Add immediate to A 7

pointer ACI 1 1 0 0 1 1 1 0 Add immediate to A 7

INXSP 0 0 1 1 0 0 1 1 "Increment stack pointer 5 DCXSP 0 0 1 1 1 0 1 1 Decrement steck 5

with carry

OAOB 0 0 0 0 1 0 0 I, AddB&CtoH&L 10

pOinter DADO 0 0 0 1 1 0 0 1 AddO&EtoH&L 10

JUMP OADH 0 0 1 0 1 0 0 1 AddH&LtoH&L, 10

JMP 1 1 0 0 0 0 1 1 Jump unconditional 10 OAOSP 0 0 1 1 1 0 0 1 AcId stack pointer to 10

, JC 1 1 0 1 1 0 1 0 Jump on carry 10 H&L

JNC 1 1 0 1 0 0 1 0 Jump on no carry 10 JZ 1 1 0 0 1 0 1 0 Jump on zero 10 JNZ 1 1 0 0 0 0 1 0 Jump on no zero 10 JP 1 1 1 1 0 0 1 0 Jump on positive 10 JM 1 1 1 1 1 0 1 0 Jump on minus 10 JPE 1 1 1 0 1 0 1 0 Jump on partty even 10

2-8

AFN-0073SC

intJ 8080Al8080A·1/8080A·2

Summary of Procauor In_Ion. (Cont.) Clock

In_Ion Code [1J Operatlone Cycl •• Instruction Code III

Mnamonlc Dr D6 Ds D4 D:l D:! D,

Do

^De_lpllon [2J Mnemonic Dr D6 Os D4 D:l D2 D, DC

SUBTRACT ROTATE

SUBr

,

0 0 1 0 S S S Subtract register 4 RLC 0

from A RRC 0

SBBr 1 0 0 1 1 S S S Subtract register from 4 RAL 0 Awlth borrow

SUBM 1 0 0 1 0 1 1 0 Subtract memory 7 RAR 0

from A

SBBM 1 0 0 1 l ' 1 1 0 Subtract memory from 7 SPECIALS

A with borrow CMA 0

SUI 1 1 0 1 0 1 1 0 Subtract Immediate 7 STC 0

from A CMC 0

SBI 1 1 0 1 1 1 1 0 Subtract Immediate 7 OM 0

from A with borrow INPUT/OUTPUT

LOGICAL IN

ANAr 1 0 1 0 0 S S S And register with A 4 OUT XRAr 1 0 1 0 1 S S S Exclusive Or register 4 CONTROL

with A EI

ORAr 1 0 1 1 0 S S S Or ragister with A 4 01 CMPr 1 0 1 1 1 S S S Compara register with A 4 NOP ANAM 1 0 1 0 0 1 1 0 And memory with A 7 HLT XRAM 1 0 1 0 1 1 1 0 Exclusive Or memory 7

with A

DRAM 1 0 1 1 0 1 1 .0 ·Or memory with A 7 CMPM 1 0 1 1 1 1 1 0 Compare memory with

A 7

ANI 1 1 1 0 0 1 1 0 And immediate with A 7 XRI 1 1 1 0 1 1 1 0 Exclusive Or immediate 7

with A

ORI 1 1 1 1 0 1 1 0 Or Immediate with A 7 CPI 1 1 1 1 1 1 1 0 Compare immediate 7

with A NOTES:

1. DOD orSSS: B=OOO, C=OOI, 0=010, E=OII, H=I00, L=101, Memory=110, A=111.

2. l\vo possible cycle times (6/12) indicate Instruction cycles dependent on condition flegs.

"All mnemonics copyright Clntel Corporation 19n

2·9

1 1 1 1 0 0

0 0 0 0 1 1 1 0 0 0

,

1 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0

Clock Operations Cycle.

Description 121

Rotate A left 4

Rotate A right 4

Rotete A left through 4 carry

Rotate A rrght through 4 carry

Complement A 4

Set carry 4

Complement carrY 4 Decimal ad'ust A 4

Input 10

Output 10

Enable Interrupts 4 Disable Interrupt 4

No-operation 4

Hall 7

AFN·00735C

intJ

8085AH/8085AH-218085AH-1 8-BIT HMOS MICROPROCESSORS

• Single +5V Power Supply with 10%

Voltage Margins

• 3 MHz, S MHz and 6 MHz Selections Available

• 20% Lower Power Consumption than 8085A for 3 MHz and 5 MHz

• 1.3 fJ-S Instruction Cycle (8085AH); O.S fJ-s (8085AH-2); 0.67 /.LS (8085AH-1)

• 100% Compatible with 808SA

• 100% Software Compatible with S080A

• On-Chip Clock Generator (with External Crystal, LC or RC Network)

• On-Chip System Controller; Advanc:;ed Cycle Status. Information Available for Large System Control

• Four Vectored Interrupt Inputs (One is Non-Maskable) Plus an

8080A-Compatible Interrupt

• Serial In/Serial Out Port

• Decimal, Binary and Double Precision Arithmetic

• Direct Addressing Capability to 64K Bytes of Memory

• Available in EXPRESS

- Standard Temperature Range - Extended Temperature Range

The Intel® 8085AH is a complete 8 bit parallel Central Processing Unit (OPU) implemented in N-channel, depletion load, silicon gate technology (HMOS). Its instruction set is 100% software compatible with the8080A microprocessor, and it is designed to improve the present 8080A's performance by higher system speed. Its high level of system integration allows a minimum system of three IC's [8085AH (CPU), 8156H (RAM/IO) and 8355/8755A (ROM/PROM/IO)) while maintaining total system expandability. The 8085AH-2 and 8085AH-1 are faster versions of the 8085AH.

The 8085AH incorporates all of the features that the 8224 (clock generator) and 8228 (system controller) provided for the 8080A, thereby offering a high level of system integration~

The 8085AH uses a multiple)<ed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The on-chip address latches of 8155H/8156H/8355/8755A memory products allow a direct interface with the 8085AH.

x, x,

INTA RST65

:~: ::, * :: ^}REGISTER

REG REG ARRAY

S1 ACK POINTER 11S1

PROGRAM COUNTER (161 INCREMENTER/DECREMENTER

AODRESS LATCH ~ 1161

Al~-Aa ADDRESS BUS

.0.07-.0.00 ADDRESS/DATA BUS

Figure 1. 8085AH CPU Functional Block Diagram

Vee HOLD HLDA eLK (OUT) RESET IN READY 101M

RST65 S,

RST55 Ri5

INTR We

INTA ALE

ADO So

AD, A,S

A,.

A13

AD. A12

All AlO Ag AS

Figure 2. 8085AH Pin Configuration

Intel Corporation Assumes No Responslbilty for the Use of Any CircUitry Other Than Circuitry Embodied In an Intel Product. No Other Circuit Patent Licenses 81'8 Implied.

elNTEL CORPORATION, 1981

2-10