Intel LITERATURE

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Intel the Microcomputer Company:

When Intel invented the microprocessor in 1971, it created the era of microcomputers. Whether used as microcontrol/ers in automobiles or microwave

ovens, or as personal computers or supercomputers, Intel's microcomputers have always offered leading-edge technology. In the second half of the 1980s, Intel architectures have held at least a 75% market share of microprocessors at 16 bits and above.

Intel continues to strive for the highest standards in memory, microcomputer components, modules, and systems to give its customers the best possible competitive advantages.

MICROPROCESSOR AND PERIPHERAL HANDBOOK VOLUME'll PERIPHERAL

1989

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Table of Contents

Alphanumeric Index '" . . . ix CHAPTER 1

Overview ,

Introduction ... . . . 1-1 CHAPTER 2

8086 Microprocessor Family DATA SHEETS

808616-Bit HMOS Microprocessor... ... ... 2-1 80C86A 16-Bit CHMOS Microprocessor. . . 2-31 80C86AL 16-Bit CHMOS Microprocessor. . . 2-60 8088 8-Bit HMOS Microprocessor. . . 2-89 80C88A 8-Bit CHMOS Microprocessor. . . .. 2-119 80C88AL 8-Bit CHMOS Microprocessor ... , 2-151

8087/8087 -2/8087 -1 Numeric Data Coprocessor ... 2c 183

82C84A CHMOS Clock Generator and Driver for 80C86, 80C88 Processors ... 2-205 82C88 CHMOS Bus Controller. . . .. 2-214 8237 A High Performance Programmable DMA Controller

(8237 A, 8237 A-4, 8237 A-5) . . . .. 2-222 82C37A-5 CHMOS High Performance Programmable DMA Controller... 2-241

8259A18259A-2/8259A-8 Programmable Interrupt Controller. . . . .. . . .. 2-259

82C59A-2 CHMOS Programmable Interrupt Controller . . . .. 2-283 CHAPTER 3

80286 Microprocessor Family DATA SHEETS

80286 High Performance Microprocessor with Memory Management and

Protection . . . 3-1 80287 80-Bit HMOS Numeric Processor Extention . . . 3-56 82258 Advanced Direct Memory Access Coprocessor ... 3-82 82288 Bus Controller for 80286 Processor

(82288-12,82288-10,82288-8) ... 3-141 82C288 Bus Controller for 80286 Processors

(82C288-12, 82C288-1 0, 82C288-8) . . . .. 3-161 82C284 Clock Generator and Ready Interface for 80286 Processors

(82C284-12, 82C284-10, 82C284-8) ... 3-182 CHAPTER 4

INTEL386™ Family DATA SHEETS

386™ High Performance Microprocessor with Integrated Memory Management. . . 4-1 80387 80-Bit CHMOS III Numeric Processor Extension. . . .. 4-133 82380 High Performance 32-Bit DMA Controller wi I ntegrated System

Support Peripherals... 4-171

82385 High Performance 32-Bit Cache Controller ... 4-292

386SXTM Microprocessor ... . . . .. 4-354

80387SX 80-Bit Numeric Processor Extension ... 4-450

82310/82311 Micro Channel Compatible Peripheral Family. . . .. 4-488

82303 110 Support Chip. . . .. 4-509

82304110 Support Chip. . . .. 4-519

82306 Local Channel Support Chip. . . .. 4-534

82307 DMAIMicro Channel Arbitration Controller. . . .. 4-545

82308 Micro Channel Bus Controller (BC) ... , 4-557

82309 Address Bus Controller (ABC) ... 4-588

Table of Contents (Continued)

82706 Intel Video Graphics Array. . . .. 4-618 82335 High Integration Interface Device for 386SX™ Microprocessor Based

PC-AT System. . . .. 4-636 82230/82231 High Integration AT*-Compatible Chip Set. . . .. . . . .. 4-667 376™ High Performance 32-Bit Embedded Processor. . . .. 4-705 82370 Integrated System Peripheral. . . .. . . .. . . .. 4-796 CHAPTERS

Memory Controllers DATA SHEETS

8203 64K Dynamic RAM Controller. . . 5-1 8206 Error Detection and Correction Unit. .. . . 5-17 8207 Dual-Port Dynamic RAM Controller ... :. . . 5-39 82C08 CHMOS Dynamic RAM Controller. . . 5-86 APPLICATION NOTES

Interfacing the 8207 Dynamic RAM Controller to the 80186 AP-167 ... , . . . .. 5-115 Interfacing the 8207 Advanced Dynamic RAM Controller to the 80286 AP-168 5-121 CHAPTER 6

Support Peripherals DATA SHEETS

8231A Arithmetic Processing Unit. . . .. . . .. . . 6-1 8253/8253-5 Programmable IntervalTimer . . . .. . . 6-14 8254 Programmable Interval Timer . . . .. . . 6-25 82C54 CHMOS Programmable Interval Timer... ... 6-46 8255A18255A-5 Programmable Peripheral Interface : . . . 6-63 82C55A CHMOS Programmable Peripheral Interface ... 6-87 8256AH Multifunction Microprocessor Support Controller. . . .. 6-110 8279/8279-5 Programmable Keyboard/Display Interface. . . .. 6-134 82389 Message Passing Coprocessor, A MULTIBUSTM II Bus Interface Controller; 6-150 CHAPTER 7

Floppy Disk Controllers DATA SHEETS

8272A Single/Double Density Floppy Disk Controller. . . .. . . .. . . .. . 7-1 82077 Single Chip Floppy Disk Controller. . . 7-32 APPLICATION NOTES

An Intelligent Data Base System Using the 8272 AP-116 ... 7-87 Software Design and Implementation of Floppy Disk Systems AP-121 ... 7-128 CHAPTERS

Hard Disk Controllers DATA SHEET

82064 CHMOS Winchester Disk Controller with On-Chip Error Detection and

Correction. . . .. . . . 8-1 APPLICATION NOTE

Multimode™ Winchester Controller Using the CHMOS 82064 AP-402... 8-33 CHAPTER 9

Universal Peripheral Interface Slave Microcontrollers DATA SHEETS

UPITM-452 CHMOS Programmable I/O Processor (80/83/87452) .. . . 9-1 UPITM-41, 42: 8041 AH/8042AH/8741 AH/8742AH Universal Peripheral Interface

8-Bit Slave Microcontroller ... 9-54

Table of Contents

(Continued)

8243 MCS®-48 Input/Output Expander .. . . . .. . . .. . . .. . 9-73 APPLICATION NOTES

Applications Using the 8042 UPITM Microco,ntroUer . . . 9-79 Complex Peripheral Control with the UPITM-42 AP-161 ;... 9-83 An 8741 AH/8041 A Digital Cassette Controller AP-90 . . . . .. . . ... . .. . .. • . . . .. ... 9-138 UPITM-452 Accelerates iAPX 286 Bus Performance AP-281 .. ... . . .. . .. . ... .. ... 9-145 SYSTEM SUPPORT

ICETM-42 8042 In-Circuit Emulator .... 0' • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ~ • • • • • 9-165 iUP-200AliUP-201A Universal PROM Programmers ...•... :... 9-173

CHAPTER 10

Graphics Coprocessor Family

DATA SHEETS

82706 Intel Video Graphics Array ... . 82716IVSDD Video Storage and Display Device ... . 82786 CHMOS Graphics Coprocessor ... : ... ; ... . APPLICATION NOTES

10-1 10-2 10-4 A Low Cost and High I'ltegration Graphics System Using 82716 AP-268 . . . .. 10-49 82786 Hardware Configuration AP-270 ... 10-101 An Introduction to Programming the 82786 Graphics Coprocessor AP-408 ... 10-162 82786 Design Example Interfacing to the IBM

PCI

AT Computer AP-409 ..•. : ... 10-222

CHAPTER 11 . . .

Development Tools for the 8051, 8096, 8086/186/188, 80286, an.d 80386

LANGUAGES AND SOFTWARE DEVELOPMENT TOOLS

8051 Software Packages Fact Sheet ... . 8096 Software Development Packages Fact Sheet ... . VAXIVMS Resident Software Development Packages Data Sheet ... . 8086/80186 SOftware Development Packages Fact Sheet ... . 8087 Support Library Data Sheet ... . PSCOPE-86 for DOS High-Level Application Program Debugger Data Sheet •...

iC-86 C Compiler Fact Sheet ... . 286 Software Development Packages Data Sheet ... . Ada-386 Cross Development for the 386™ Fact Sheet ... . Intel386TM Development Support Family Fact Sheet ... . AEDIT Source Code and Text Editor Fact Sheet ..•...

iPA TTM Performance Analysis Tool Fact Sheet. ...•...

IN-CIRCUIT EMULATORS

11-1 11-4 11-7 11-15 11-19 . 11-23 11-30 11-33 11-51 11-55 11-59 11-61 ICETM 5100/452 In-Circuit Emulator Fact Sheet ... ; .. 11-65 ICETM 51001044 In-Circuit Emulator Fact Sheet. . . .. 11-69 ICETM 5100/252 In-Circuit Emulator Fact Sheet.. .. . . . .. ... . . .. . . .. ... . .. .. 11-73 ICETM 5100/451 In-Circuit Emulator Fact Sheet. . . .... .. ... .•. . . .. . .. . .. .. 11-77 VLSiCETM-96 In-Circuit Emulator Fact Sheet... . .. .... .. . .. . .. .. . . .. . . . .. . .... 11-81 Real-Time Transparent 80C196 In-Circuit Emulator Fact Sheet. . . .. 11-84 ICETM-196KB/xX In-Circuit Emulators Fact Sheet ... . . . .. . ... 11-86 ICETM-186 In-Circuit Emulator Fact Sheet ;... ... . .. . . .. 11-90 ICETM-188 In-Circuit Emulator Fact Sheet ... . . . .. 11-94 1²1CETM In-Circuit Emulation System Fact Sheet. . . • . . . .. 11-98 ICETM-286 In-Circuit Emulator Fact Sheet ...•... 11"101 Intel386TM Family Development Support Fact Sheet ... 11-104

Alphanumeric Index

286 Software Development Packages Data Sheet. . . .. 11-33 376™ High Performance 32-BitEmbedded Processor. . . .. . . . .. 4-705 386SXTM Microprocessor. . . .. . . .. 4-354 386™ High Performance Microprocessor with Integrated Memory Management ... 4-1 80286 High Performance Microprocessor with Memory Management and Protection. . . 3-1 80287 80-Bit HMOS Numeric Processor Extention ... 3-56 80387 80-Bit CHMOS III Numeric Processor Extension ... 4-133 80387SX 80-Bit Numeric Processor Extension. . . .. 4-450 8051 Software Packages Fact Sheet . . . 11-1 808616-Bit HMOS Microprocessor... ... 2-1 8086/80186 Software Development Packages Fact Sheet . . . .. 11-15 8087 Support Library Data Sheet ... 11-19 8087/8087-2/8087-1 Numeric Data Coprocessor. . . .. 2-183 8088 8-Bit HMOS Microprocessor. . . 2-89 8096 Software Development Packages Fact Sheet. . . .. . . 11-4 80C86A 16-Bit CHMOS Microprocessor ... 2-31 80C86AL 16-Bit CHMOS Microprocessor ... . . . 2-60 80C88A 8-Bit CHMOS Microprocessor... ... 2-119 80C88AL 8-Bit CHMOS Microprocessor ... 2-151 8203 64K Dynamic RAM Controller ... " . . . 5-1 8206 Error Detection and Correction Unit ... 5-17 82064 CHMOS Winchester Disk Controller with On-Chip Error Detection and Correction .. 8-1 8207 Dual-Port Dynamic RAM Controller. . . • . . . 5-39 82077 Floppy Disk Controller. . . .. 4-617 82077 Single Chip Floppy Disk Controller . . . 7 -32 82230/82231 High Integration AT*-Compatible Chip Set. . . .. 4-667 82258 Advanced Direct Memory Access Coprocessor. . . 3-82 82288 Bus Controller for 80286 Processor (82288-12, 82288-10, 82288-8) . . . .. 3-141 82303 I/O Support Chip .. . . .. 4-509 823041/0 Support Chip ... 4-519 82306 Local Channel Support Chip. . . .. 4-534 82307 DMAIMicro Channel Arbitration Controller . . . .. 4-545 82308 Micro Channel Bus Controller (BC) . . . .. . . .. 4-557 82309 Address Bus Controller (ABC) ... , . . . .. 4-588 82310/82311 Micro Channel Compatible Peripheral Family ... 4-488 8231 A Arithmetic Processing Unit. . . .. . . 6-1 82335 High Integration Interface Device for 386SXTM Microprocessor Based PC-AT

System . . . .. 4-636 82370 Integrated System Peripheral. . . .. 4-796 8237 A High Performance Programmable DMA Controller (8237 A, 8237 A-4, 8237 A-5) . .. .. 2-222 82380 High Performance 32-Bit DMA Controller w/lntegrated System

Support Peripherals. . . .. . . .. . . .. 4-171 82385 High Performance 32-Bit Cache Controller . . . .. 4-292 82389 Message Passing Coprocessor, A MUL TIBUSTM II Bus Interface Controller. . . .. 6-150 8243 MCS®-48 Input/Output Expander. . . 9-73 8253/8253-5 Programmable Interval Timer. . . 6-14 8254 Programmable Interval Timer. . . 6-25 8255A18255A-5 Programmable Peripheral Interface . . . 6-63 8256AH Multifunction Microprocessor Support Controller ... :... 6-110 8259A18259A-2/8259A-8 Programmable Interrupt Controller. . . .. 2-259 82706 Intel Video Graphics Array... 4-618 82706 Intel Video Graphics Array ... . . . 10-1 82716IVSDD Video Storage and Display Device... 10-2 8272A Single/Double Density Floppy Disk Controller . . . 7-1

ix

Alphanumeric Index (Continued)

82786 CHMOS Graphics Coprocessor. . . .. . . 10-4 82786 Design Example Interfacing to the IBM PC/AT Computer AP-409 ... 10-222 82786 Hardware Configuration AP-270 ... 10-101 8279/8279-5 Programmable Keyboard/Display Interface. . . .. 6-134 82C08 CHMOS Dynamic RAM Controller ... 5-86 82C284 Clock Generator and Ready Interface for 80286 Processors

(82C284-12, 82C284-1 0, 82C284-8) ... '" 3-182 82C288 Bus Controller for 80286 Processors (82C288-12, 82C288-10, 82C288-8)... 3-161 82C37 A-5 CHMOS High Performance Programmable DMA Controller ... 2-241 82C54 CHMOS Programmable Interval Timer. . . 6-46 82C55A CHMOS Programmable Peripheral Interface ... 6-87 82C59A-2 CHMOS Programmable Interrupt Controller. . . .. 2-283 82C84A CHMOS Clock Generator and Driver for 80C86, 80C88 Processors. . . .. . . .. 2-205 82C88 CHMOS Bus Controller. . . .. . . .. 2-214 A Low Cost and High Integration Graphics System Using 82716 AP-268. . . • . . . .. 10-49 Ada-386 Cross Development for the 386™ Fact Sheet. .. . . .. 11-51 AEDIT Source Code and Text Editor Fact Sheet ... 11-59 An 8741 AH/8041 A Digital Cassette Controller AP-90 . . . .. . . .. . . .. 9-138 An Intelligent Data Base System Using the 8272 AP-116 . . . .. . . .. . . 7-87 An Introduction to Programming the 82786 Graphics Coprocessor AP-408 ... 10-162 Applications Using the 8042 UPITM Microcontroller . . . 9-79 Complex Peripheral Control with the UPITM-42 AP-161 ... 9-83 iC-86 C Compiler Fact Sheet ... : ... ;... 11-30 ICETM 5100/044 In-Circuit Emulator Fact Sheet. . . .. 11-69 ICETM 5100/252 In-Circuit Emulator Fact Sheet. ." ... " ... ; . . . .. 11-73 ICETM 5100/451 In-Circuit Emulator Fact Sheet... 11-77 ICETM 5100/452 In-Circuit Emulator Fact Sheet. ... 11-65 ICETM-186 In-Circuit Emulator Fact Sheet ... 11-90 ICETM-188 In-Circuit Emulator Fact Sheet. . . .. . . .. 11-94 ICETM-196KB/xX In-Circuit Emulators Fact Sheet. . . .. 11-86 ICETM-286 In-Circuit Emulator Fact Sheet ... 11-101 ICETM-42 8042 In-Circuit Emulator... 9-165 Intel386TM Development Support Family Fact Sheet. . . . .. . . .. . . .. . . .. 11-55 Intel386™ Family Development Support Fact Sheet. ... 11

c

104 Interfacing the 8207 Advanced DynamiC RAM Controller to the 80286 AP-168 . ; . . . ... 5-121 Interfacing the 8207 Dynamic RAM Controller to the 80186 AP-167 . . . .. 5-115 iPATTM Performance Analysis Tool Fact Sheet ... 11-61 iUP-200A/iUP-201 A Universal PROM Programmers. . . .. 9-173 1

2

1CETM In-Circuit Emulation System Fact Sheet ... ;... 11-98 Multimode™ Winchester Controller Using the CHMOS 82064 AP-402 ... 8-33 PSCOPE-86 for DOS High-Level Application Program Debugger Data Sheet. . . .. 11-23 Real-Time Transparent 80C196 In-Circuit Emulator Fact Sheet ... 11-84 Software Design and Implementation of Floppy Disk Systems AP-121 ... 7-128 UPITM-41, 42: 8041 AH/8042AH/8741 AH/8742AH Universal Peripheral Interface 8-Bit

Slave Microcontroller . . . ... . . 9-54

UPITM-452 Accelerates iAPX 286 Bus Performance AP-281 ...•... 9-145

UPITM-452 CHMOS Programmable I/O Processor (80/83/87452). . . 9-1

VAXIVMS Resident Software Development Packages Data Sheet ..•...•... 11-7

VLSiCETM-96 In-Circuit Emulator Fact Sheet ... 11-81

Any of the following products may appear in this publication. If so, it must be noted that such products have counterparts manufactured by Intel Puerto Rico, Inc., Intel Puerto Rico II, Inc., and/or Intel Singapore, Ltd. The product codes/part numbers of these counterpart products are listed below next to the corresponding Intel Corporation product codes/part numbers.

Intel Corporation Intel Puerto Rico, Inc.

Intel Singapore, Ltd. Intel Corporation Intel Puerto Rico, Inc.

Intel Singapore, Ltd.

Intel Puerto Rico II. Inc. Intel Puerto RIco II, Inc.

Product Codes/

Product Codes/ Product Codes/ Product Codes/

Product Codes/ Product Codes / Part Numbers

Part Numbers Part Numbers Part Numbers

Part Numbers Part Numbers

376SKIT p376SKIT KM2 pKM2

903 p903 KM4 pKM4

904 p904 KM8 pKM8

913 p913 KNLAN pKNLAN

914 p914 KT60 pKT60

923 p923 KWI40 pKWI40

924 p924 KW40 pKW40

952 p952 KW80 pKW80

953 p953 MI pMl

954 p954 M2 pM2

ADA ICE pADAICE M4 pM4

B386MI pB386Ml M8 pM8

B3B6M2 pB3B6M2 MDS6lO pMDS6lO

B386M4 pB386M4 MDX3015 pMDX3015

B3B6M8 pB386MB MDX3015 pMDX3015

C044KIT pC044KIT MDX3016 pMDX3016

C252KIT pC252KIT MDX3016 pMDX3016

C28 pC28 MDX457 pMDX457

C32 pC32 MDX457 pMDX457

C452KIT pC452KIT MDX458 pMDX458

D86ASM pD86ASM MDX458 pMDX458

D86C86 pD86C86 MSA96 pMSA96

D86EDI pD86EDI NLAN pNLAN

DCM9111 pDCM9111 PCLINK sPCLINK

DOSNET pDOSNET PCX344A pPCX344A

FI pFI R286ASM pR286ASM

GUPILOGICIID pGUPILOGICIID R286EDI pR286EDI

H4 pH4 R286PLM pR286PLM

1044 plO44 R286SSC pR286SSC

I252KIT pI252KIT R86FOR pR86FOR

I452KIT pI452KIT RCB44lO sRCB4410

I86ASM pI86ASM RCX920 pRCX920

ICE386 pICE386 RMX286 pRMX286

IllOI0 pIllOlO RMXNET pRMXNET

Ill086 pIll086 S301 pS301

Ill086 TIll086 S386 pS386

IllIII pIll111 SBCOlO pSBCOlO

III 186 pIlI I 86 SBCOl2 pSBCOl2 sSBCOl2

III 186 TlII186 SBC020 pSBC020

1II198 pIlll98 SBC028 pSBC028

1II212 pIll212 SBC040 pSBC040

111286 pIll286 SBC056 pSBC056

Ill286 TlII286 SBClO8 pSBCI08

Ill515 pIll515 SBCII6 pSBC116

III 520 TIll 520 SBCI8603 pSBC18603 sSBCI8603

Ill520 pIlI520 SBCI86410 pSBCI86410

Ill531 pIll53 I SBCI8651 pSBCI8651 sSBCI8651

Ill532 pIll532 SBCI86530 pSBCI86530

1II533 pIll533 SBCI8678 pSBC18678

Ill621 pIII62 I SBCI8848 pSBCI8848 sSBCI8848

III707 pIII707 SBCI8856 pSBCI8856 sSBCI8856

1II707 TIII707 SBC208 pSBC208 sSBC208

1II815 pIll8I5 SBC214 pSBC214

INA961 pINA96I SBC215 pSBC215

IPAT86 pIPAT86 SBC220 pSBC220 sSBC220

KAS pKAS SBC221 pSBC221

KC pKC SBC286lO pSBC286lO sSBC286lO

KH pKH SBC286I2 pSBC28612

KMI pKMI SBC28614 pSBC28614

xi

Intel Corporation Intel Puerto Rico II, Inc. Intel Corporation Intel Puerto Rico II, Inc.

Product Codesj

Product Codes j Product Codesj Product Codesj

Product Codes j Product Codes j

Part Numbers Part Numbers Part Numbers Part Numbers Part Numbers Part Numbers

SBC28616 pSBC286l6 SBCMEM310 pSBCMEM310

SBC300 pSBC300 SBCMEM3l2 pSBCMEM3l2

SBC30l pSBC30l SBCMEM320 pSBCMEM320

SBC302 pSBC302 SBCMEM340 pSBCMEM340

SBC304 pSBC304 SBE96 pSBE96

SBC307 pSBC307 SBX2l7 pSBX2l7

SBC3l4 pSBC3l4 SBX2l8 pSBX2l8

SBC322 pSBC322 SBX270 pSBX270

SBC324 pSBC324 SBX3ll pSBX311

SBC337 pSBC337 SBX328 pSBX328

SBC34l pSBC34l SBX33l pSBX33l

SBC386 pSBC386 sSBC386 SBX344 pSBX344

SBC386ll6 pSBC386ll6 SBX350 pSBX350

SBC386l20 pSBC386l20 SBX35l pSBX35l

SBC3862l pSBC3862l SBX354 pSBX354

SBC38622 pSBC38622 SBX488 pSBX488

SBC38624 pSBC38624 SBX586 sSBX586

SBC38628 pSBC38628 SCHEMAIIPLD pSCHEMAIIPLD

SBC3863l pSBC3863l SCOM pSCOM

SBC38632 pSBC38632 SDK5l pSDK5l

SBC38634 pSBC38634 SDK85 pSDK85

SBC38638 pSBC38638 SDK86 pSDK86

SBC428 pSBC428 sSBC428 SXM2l7 pSXM2l7

SBC464 pSBC464 SXM286l2 pSXM286l2

SBC517 pSBC5l7 SXM386 pSXM386

SBC5l9 pSBC5l9 sSBC5l9 SXM544 pSXM544

SBC534 pSBC534 sSBC534 SXM552 pSXM552

SBC548 pSBC54S SXM95l pSXM95l

SBC550 TSBC550 SXM955 pSXM955

SBC550 pSBC550 SYPl20 pSYPl20

SBC550 pSBC550 SYP30l pSYP30l

SBC552 pSBC552 SYP302 pSYP302

SBC556 pSBC556 sSBC556 SYP31090 pSYP3l090

SBC569 pSBC569 SYP311 pSYP3ll

SBC589 pSBC589 SYP3847 pSYP3847

SBC604 pSBC604 SYR286 pSYR286

SBC608 pSBC608 SYR86 pSYR86

SBC6l4 pSBC6l4 SYSl20 pSYSl20

SBC6l8 pSBC6l8 SYS3l0 pSYS310

SBC655 pSBC655 SYS3ll pSYS3ll

SBC66ll pSBC66ll T60 pT60

SBC8010 pSBC8010 ^" TA096 pTA096

SBC80204 pSBC80204 TA252 pTA252

SBC8024 pSBC8024 sSBC8024 TA452 pTA452

SBC8030 pSBC8030 Wl40 pWl40

SBC8605 pSBC8605 sSBC8605 W280 pW280

SBC86l2 pSBC86l2 W40 pW40

SBC86l4 pSBC86l4 W80 pW80

SBC8630 pSBC8630 sSBC8630 XNX286DOC pXNX286DOC

SBC8635 pSBC8635 sSBC8635 XNX286DOCB pXNX286DOCB

SBC86C38 sSBC86C38 XNXIBASE pXNXIBASE

SBC8825 pSBC8825 sSBC8825 XNXIDB pXNXIDB

SBC8840 pSBC8840 XNXIDESK pXNXIDESK

SBC8845 pSBC8845 sSBC8845 XNXIPLAN pXNXIPLAN

SBC905 pSBC905 XNXIWORD pXNXIWORD

SBCLNKOOl pSBCLNKOOl

OVERVIEW.

INTRODUCTION

Intel microprocessors and peripherals provide a complete solution in increasingly complex application environ- ments. Quite often, a single peripheral device will replace anywhere from 20 to 100 TTL devices (and the associated design time that goes with them).

Built-in functions and standard Intel microprocessor/

peripheral interface deliver very real time and perfor- mance advantages to the designer of microprocessor- based systems.

REDUCED TIME TO MARKET

When you can purchase an off-the-shelf solution that replaces a number of discrete devices, you're also replac- ing all the design, testing, and debug time that goes with them.

INCREASED RELIABILITY

At Intel, the rate offailure for devices is carefully tracked.

Highest reliability is a tangible goal that translates to higher reliability for your product, reduced downtime, and reduced repair costs. And as more and more functions are intergrated on a single VLSI device, the resulting system requires less power, produces less heat, and requires fewer mechanical connections-again re- sulting in greater system reliability.

LOWER PRODUCTION COST

By minimizing design time, increasing reliability, and

I

replacing numerous parts, microprocessor and peripheral solutions can contribute dramatically to lower product costs.

HIGHER SYSTEM PERFORMANCE

Intel microprocessors and peripherals provide the highest system performance for the demands of today's (and tomorrow's) microprocessor-based applications. Forexam- pie, the 80386 32 bit offers the highest performance for multitasking, multiuser systems. Intel's peripheral pro- ducts have been designed with the future in mind. They support all of Intel's 8, 16 and 32 bit processors.

HOW TO USE THE GUIDE

The following application guide illustrates the range of microprocessors and peripherals that can be used for the applictions in the vertical column of the left. The peripherals are grouped by the I/O function they control.

CRT datacommunication, universal (user programmable), mass storage dynamic RAM controllers, and CPU/ bus support.

An "X" in a horizontal application row indicates a potential peripheral or CPU, depending upon the features desired. For example, a conversational terminal could use either of the three display controllers, depending upon features like the number of characters per row or font capability. A "Y" indicates a likely candidate, for example, the 8272A Floppy Disk Controller in a small business computer.

The Intel microprocessor and peripherals family provides a broad range of time-saving, high performance solutions.

CACHE MEMORY

DYNAMIC RAM

Get Your Kit Together!

Intel's Microsystem Components Kit Solution

*

*

I

MICRO- PROCESSOR 8088/80C88 8086/80C86 80186 80188 80286 386'·fL 386SX'·fL

SUPER CHIP SET 82310/11 82230/31 82335 82350

NUMERIC PROCESSORS 8087 80287 80387 80387SX

CPU SUPPORT 8231A 8253 8254/82C54 8255A/82C55A 8256AH 8279 82389 82370

DMA 8253 8237 82285 82380 82560

~-,,,""

CACHE CONTROL

~!:.& .. :;;i

MEMORY SUPPORT 8203 8206 8207 82C08

"""""-,,,

CRT CONTROL 82706 82716 82786

r.:.a$. ~."';'h'''''''''''''~f"'~

SPECIAL PERIPHERAL CONTROL UPI'· 8041A/8741A

*

*

*

* *

*

*

*

" FLOPPY DISK

. '

~~~~ROL

~~ 82077 [""".1"

HARD DISK CONTROL 82064

GLOBAL COMMUNICATIONS 8251A

82050 82510 8273 8274 8291 A/92/94 82530

;: 8044/8344/8744 ':",y"

r ' LOCAL AREA

, NETWORKING

.t W

82C501 82586 82588 82560 82590/92 i iMCC

L~'0.".

^i,)

~. INSTRUMENTATION

*;'

BUS (GPIB) ,

.: 8291

< 8292

l~LU~'L.;.,:::

!!;I TELE-

P, COMMUNICATIONS 2910/11/12 ... " 29C13/C14/C16/C17

4.Mt29C48

...,... 29C53AA ISP 188 89024 89C024XE

*11)1

JlJj

Memory Controllers 5

8203

64K DYNAMIC RAM CONTROLLER

•

Provides All Signals Necessary to

•

Fully Compatible with Intel® 8080A, Control 64K and 16K Dynamic 8085A, iAPX88, and iAPX 86 Family

Memories Microprocessors

•

Directly Addresses and Drives Up to 64

•

Decodes CPU Status for Advanced Devices Without External Drivers Read Capability in 16K Mode with the

•

Provides Address Multiplexing and 8203-1 and the 8203-3.

Strobes

•

Provides System Acknowledge and

•

Provides a Refresh Timer and a Transfer Acknowledge Signals Refresh Counter

•

Refresh Cycles May be Internally or

•

Provides Refresh! Access Arbitration Externally Requested (For Transparent Refresh)

•

Internal Clock Capability with the

Internal Series Damping Resistors on 8203-1 and the 8203-3

•

All RAM Outputs

The Intel® 8203 is a Dynamic RAM System Controller designed to provide all signals necessary to use 64K or 16K Dynamic RAMs in microcomputer systems. The 8203 provides multiplexed addresses and address strobes, refresh logic, refresh/access arbitration. Refresh cycles can be started internally or externally. The 8203-1 and the 8203-3 support an internal crystal oscillator and Advanced Read Capability. The 8203-3 is a

±5% Vee part.

A~-AH7

AlO-AL7

REFRESH

C"""".

iffi i > C S - - - l

"" 5'======:1

COlUWN ADDRESS

""'"'ss .ow

So

Figure 1. 8203 Block Diagram

5-1

. - 0 GENERATOR

0iiS0 W, AiS2 R/33

"'"

""

SACK

.. ex

210444-1

Al, OuT,

210444-2

Figure 2.

Pin Configuration

November 1987 Order Number: 210444-006

intJ

⁸²⁰³

Table 1. Pin Descriptions Symbol Pin

Type Name and Function

No.

ALa 6 ADDRESS LOW: CPU address inputs used to generate memory row

AL1 8 address.

AL2 10

AL;3 12

AL4 14

ALs 16

AL6 18

AHa 5 ADDRESS HIGH: CPU address inputs used to generate memory

AH1 4 column address.

AH2 3

AH3 2

AH4 1

AHs 39

AH6 38

Bo/AL7 24 BANK SELECT INPUTS: Used to gate the appropriate RAS output for B1/0P1/ 25 a memory cycle. B1 /OP1 option used to select the Advanced Read

AH7 Mode. (Not available in 64K mode.) See Figure 5.

When in 64K RAM Mode, pins 24 and 25 operate as the AL7 and AH7

address inputs. .

PCS 33 I PROTECTED CHIP SELECT: Used to enable the memory read and write inputs. Once a cycle is started, it will not abort even if PCS goes inactive before cycle completion.

WR 31 I MEMORY WRITE REQUEST.

RD/S1 32 I MEMORY READ REQUEST: S1 function used in Advanced Read mode selected by OP1 (pin 25).

REFRQ/ 34 I EXTERNAL REFRESH REQUEST: ALE function used in Advanced

ALE Read mode, selected by OP1 (pin 25).

OUTo 7 0 OUTPUT OF THE MULTIPLEXER: These outputs are designed to OUT1 9 0 drive the addresses of the Dynamic RAM array. (Note that the OUT 0-7 OUT2 11 0 pins do not require inverters or drivers for proper operation.)

OUT3 13 0

OUT4 15 0

OUTs 17 0

OUT6 19 0

WE 28 0 WRITE ENABLE: Drives the Write Enable inputs of the Dynamic RAM array.

CAS 27 0 COLUMN ADDRESS STROBE: This output is used to latch the Column Address into the Dynamic RAM array.

RASa 21 0 ROW ADDRESS STROBE: Used to latch the Row Address into the RAS1 22 0 bank of dynamic RAMs, selected by the 8203 Bank Select pins (Bo, RAS2/ 23 0 B1 /OP1). In 64K mode, only RASa and RAS1 are available; pin 23 OUT7 operates as OUT 7 and pin 26 operates as the Bo bank select input.

RAS3/BO 26 I/O

XACK 29 0 TRANSFER ACKNOWLEDGE: This outputis a strobe indicating valid data during a read cycle or data written during a write cycle. XACK can be used to latch valid data from the RAM array.

inter ⁸²⁰³

Table 1. Pin Descriptions (Continued) Symbol Pin

Type Name and Function

No.

SACK 30 0 SYSTEM ACKNOWLEDGE: This output indicates the beginning of a memory access cycle. It can be used as an advanced transfer acknowledge to eliminate wait states. (Note: If a memory access request is made during a refresh cycle, SACK is delayed until XACK in the memory access cycle).

XO/OP2 36 I/O OSCILLATOR INPUTS: These inputs are designed for a quartz crystal X1/ClK 37 I/O to control the frequency of the oscillator. If XO/OP2 is shorted to pin 40 (Vecl or if XO/OP2 is connected to

+

12V through a 1 Kfl. resistor then X1 /ClK becomes a TTL input for an external clock. (Note: Crystal mode for the 8203-1 and the 8203-3 only).

16K/64K 35 I MODE SELECT: This input selects 16K mode or 64K mode. Pins 23-26 change function based on the mode of operation.

Vee 40 POWER SUPPLY:

+

5V.

GND 20 GROUND.

FUNCTIONAL DESCRIPTION

transitions are synchronous with respect to this clock reference, except for the trailing edges of the CPU handshake signals SACK and XACK.

The 8203 provides a complete dynamic RAM con- troller for microprocessor systems as well as expan- sion memory boards.

The 8203 has two modes, one for 16K dynamic RAMs and one for 64Ks, controlled by pin 35.

,--

^{Xo WE}

I CAS

cs=l=

_1KU ^t::I

I _{~ 5% RASO}

I _X1

I _CS.,L. 8203-1

RAS1 or

68011 T 8203-3

-=-

^1·5% _{_I} ^{I RAS2}

-=-

^RAS3

XACK Cs<10pF

Fundamental XTAL SACK

210444-4 Figure 3. Crystal Operation for

the 8203·1 and 8203·3

All 8203 timing is generated from a single reference clock. This clock is provided via an external oscilla- tor or an on-chip crystal oscillator: All output signal

5-3

CPU memory requests normally use the RD and WR inputs. The Advanced-Read mode allows ALE and S1 to be used in place of the RD input.

Failsafe refresh is provided via an internal timer which generates refresh requests. Refresh requests can also be generated via the REFRQ input.

An on-chip synchronizer/arbiter prevents memory and refresh requests from affecting a cycle in prog- ress. The READ, WRITE, and external REFRESH requests may be asynchronous to. the 8203 clock;

on-chip logiC will synchronize the requests, and the arbiter will decide if the requests should be delayed, pending completion of a cycle in progress.

16K/64 Option Selection

Pin 35 is a strap input that controls the two 8203 modes. Figure 4 shows the four pins that are multi·

plexed. In 16K mode (pin 35 tied to Vee or left open), the 8203 has two Bank Select inputs to se- lect one of four RAS outputs. In this mode, the 8203 is exactly compatible with the Intel 8202A Dynamic RAM Controller. In 64K mode (pin 35 tied to GND), there is only one Bank Select input (pin 26) to select the two RAS outputs. More than two banks of 64K dynamic RAMs can be used with external logic.

8203

Other Option Selections

The 8203 has two strapping options. When OP1 is selected (16K mode only), pin 32 changes from a RD input to an S1 input, and pin 34 changes from a REFRQ input to an ALE input. See "Refresh Cycles"

and "Read Cycles" for more detail. OP1 is selected by tying pin 25 to

+

12V through a 5.1 K!l. resistor on the 8203-1 or 8203-3 only.

When OP2 is selected, the internal oscillator is dis- abled and pin 37 changes from a crystal input (X1) to a ClK input for an external TTL clock. OP2 is select- ed by shorting pin 36 (XO/OP2) directly to pin 40 (Vee). No current limiting resistor should be used.

OP2 may. also be selected by tying pin 36 to

+

12V through a 1 K!l. resistor.

Refresh Timer

The refresh timer is used to monitor the time since the last refresh cycle occurred. When the appropri- ate amount of time has elapsed, the refresh timer will request a refresh cycle. External refresh re- quests will reset .the refresh timer.

Refresh Counter

The refresh counter is used to sequentially refresh all of the memory's rows. The 8-bit counter is incre- mented after every refresh cycle.

Pin # 16K Function 64K Function 23 RAS2 Address Output (OUT 7) 24 Bank Select (Bo) Address Input (Al7) 25 Bank Select (B1) Address Input (AH7)

26 RAS3 Bank Select (Bo)

Figure 4. 16K/64K Mode Selection

Inputs Outputs

B1 Bo RASo RAS1 RAS2 RAS3

16K 0 0 0 1 1 1

Mode 0 1 1

b

1 1

1 0 1 1 0 1

1 1 1 1 1 0

64K

-

^{0 0 1}

- -

Mode

-.

^{1 1 0}

- -

Figure 5. Bank Selection

Address Multiplexer

The address multiplexer· takes the address inputs and the refresh counter outputs, and gates them . onto the address outputs at the appropriate time.

The address outputs, in conjunction with the RAS and CAS outputs, determine the address used by . the dynamic RAMs for read, write, and refresh cy-

cles. During the first part of a read or write cycle, Alo-Al7 are gated to OUT o-OUT 7, then AHo-AH7 are gated to the address outputs ..

During a refresh cycle, the refresh counter is gated onto the address outputs. All refresh cycles are RAS-only refresh (CAS inactive, RAS active).

To minimize buffer delay, the information on the ad- dress outputs is inverted from that on the address inputs.

OUT o-OUT 7 do not need inverters or buffers unless additional drive is required.

Synchronizer! Arbiter

The 8203 has three inputs, REFRQ/ Al~in 34), RD (pin 32) and WR (pin 31). The RD and YVR inputs allow an external CPU to request a memory read or write cycle, respectively. The REFRQ/ ALE input al- lows refresh requests to be requested external to the 8203.

All three of these inputs may be asynchronous with respect to the 8203's clock. The arbiter will resolve conflicts between refresh and memory requests, for both pending cycles and cycles in progress. Read and write requests will be given priority over refresh requests.

System Operation

The 8203 is always in one of the following states:

a) IDLE b) TEST Cycle c) REFRESH Cycle

d)

READ Cycle e) WRITE Cycle

The 8203 is normally in the IDLE state. Whenever one of the other cycles is requested, the 8203 will

Description Pin # Normal Function Option Function

B1/0P1 (16K only)/ AH7 25

XO/OP2 36

Bank (RAS) Select

Crystal Oscillator (8203-1 and 8203-3)

Advanced-Read Mode (8203-1, -3) External Oscillator

8203

leave the IDLE state to perform the desired cycle. If no other cycles are pending, the 8203 will return to the IDLE state.

Test Cycle

The TEST Cycle is used to check operation of sever- al 8203 internal functions. TEST cycles are request- ed by activating the PCS, RD and WR inputs. The TEST Cycle will reset the refresh address counter and perform a WRITE Cycle. The TEST Cycle should not be used in normal system operation, since it would affect the dynamic RAM refresh.

Refresh Cycles

The 8203 has two ways of providing dynamic RAM refresh:

1) Internal (failsafe) refresh 2) External (hidden) refresh

Both types of 8203 refresh cycles activate all of the RAS outputs, while CAS, WE, SACK, and XACK re- main inactive.

Internal refresh is generated by the on-chip refresh timer. The timer uses the 8203 clock to ensure that refresh of all rows of the dynamic RAM occurs every 2 milliseconds (128 cycles) or every 4 milliseconds (256 cycles). If REFRO is inactive, the refresh timer will request a refresh cycle every 10-16 microsec- onds.

External refresh is requested via the REFRO input (pin 34). External refresh control is not available when the Advanced-Read mode is selected. Exter- nal refresh requests are latched, then synchronized to the 8203 clock.

The arbiter will allow the refresh request to start a refresh cycle only if the 8203 is not in the middle of a cycle.

When the 8203 is in the idle state a simultaneous memory request and external refresh request will re- sult in the memory request being honored first. This 8203 characteristic can be used to "hide" refresh cycles during system operation. A circuit similar to Figure 7 can be used to decode the CPU's instruc- tion fetch status to generate an external refresh re- quest. The refresh request is latched while the 8203 performs the instruction fetch; the refresh cycle will start immediately after the memory cycle is complet- ed, even if the RD input has not gone inactive. If the CPU's instruction decode time is long enough, the 8203 can complete the refresh cycle before the next memory request is generated.

5-5

If the 8203 is not in the idle state then a simulta- neous memory request and an external refresh re- quest may result in the refresh request being hon- ored first.

So

~r---

^REFRO

6085A 5, . 8203

, SACK 0'

CAS

210444-5 Figure 7. Hidden Refresh

Certain system configurations require complete ex- ternal refresh requests. If external refresh is request- ed faster than the minimum internal refresh timer (tREF), then, in effect, all refresh cycles will be caused by the external refresh request, and the in- ternal refresh timer will never generate a refresh re- quest.

Read Cycles

The 8203 can accept two different types of memory Read requests:

1) Normal Read, via the RD input

2) Advanced Read, using the S1 and ALE inputs (16K mode only)

The user can select the desired Read request con- figuration via the B1/0P1 hardware strapping option on pin 25.

Normal Read Advanced Read

Pin 25 B11nput OP1 (+12V)

Pin 32 RD Input S1 Input Pin 34 REFRO Input ALE Input

# RAM Banks 4 (RASo_3) 2 (RAS2_3)

Ext. Refresh Yes No

Figure 8. 8203 Read Options

Normal Reads are requested by activating the RD input, and keeping it active until the 8203 responds with an XACK pulse. The RD input can go inactive as soon as the command hold time (tCHS) is met.

Advanced Read cycles are requested by pulsing ALE while S1 is active; if S1 is inactive (low) ALE is ignored. Advanced Read timing is similar to Normal Read timing, except the falling edge of ALE is used as the cycle start reference.

8203

If a Read cycle is requested while a refresh cycle is in progress, then the 8203 will set the internal delayed-SACK latch. When the Read cycle is even- tually started, the 8203 will delay the active SACK transition until XACK goes active, as shown in the A.C. timing diagrams. This delay was designed to compensate for the CPU's READY setup and hold times. The delayed-SACK latch is cleared after ev- ery READ cycle.

Based on system requirements, either SACK or XACK can be used to generate the CPU READY signal. XACK will normally be used; if the CPU can tolerate an advanced READY, then SACK can be used, but only if the CPU can tolerate the amount of advance provided by SACK. If SACK arrives too ear- ly to provide the appropriate number of WAIT states, then either XACK or a delayed form of SACK should be used.

Write Cycles

Write cycles are similar to Normal Read cycles, ex- cept for the WE output. WE is held inactive for Read cycles, but goes active for Write cycles. All 8203 Write cycles are "early-write" cycles; WE goes ac- tive before CAS goes active by an amount of time sufficient to keep the dynamic RAM output buffers turned off.

General System Considerations

All memory requests (Normal Reads, Advanced Reads, Writes) are qualified by the PCS input. PCS should be stable, either active or inactive, prior to the leading edge of RD, WR, or ALE. Systems which use battery backup should pull up PCS to prevent erroneous memory requests.

In order to minimize propagation delay, the 8203 uses an inverting address multiplexer without latch- es. The system must provide adequate address set- up and hold times to guarantee RAS and CAS setup and hold times for the RAM. The tAD A.C. parameter should be used for this system calculation.

The Bo-B1 inputs are similar to the address inputs in that they are not latched. Bo andB1 should not be changed durin~ memory cycle, since they directly control which RAS output is activated.

The 8203 uses a two-stage synchronizer for the memory request inputs (RD, WR, ALE), and a sepa- rate two stage synchronizer for the external refresh input (REFRQ). As with any synchronizer, there is always a finite probability of metastable states in- ducing system errors. The 8203 synchronizer was

designed to have a system error rate less than 1 memory cycle every three years based on the full operating range of the 8203.

A microprocessor system is concerned when the data is valid after RD goes low. See Figure 9. In order to calculate memory read access times, the dynamic RAM's A.C. specifications must be exam- ined, especially the RAS-access.time (tRAd and the CAS-access time (tcAd. Most configurations will be CAS-access limited; i.e., the data from the RAM will be stable tcc max (8203)

+

tCAC (RAM) after a mem- ory read cycie is started. Be sure to add any delays (due to buffers, data latches, etc.) to calculate the overall read access time.

Since the 8203 normally performs "early-write" cy- cles, the data must be stable at the RAM data inputs by the time CAS goes active, including the RAM's data setup time. If the system does not normally guarantee sufficient write data setup, you must ei- ther delay the WR input signal or delay the 8203 WE output.

Delaying the WR input will delay all 8203 timing, in- cluding the READY handshake signals, SACK and XACK, which may increase the number of WAIT states generated by the CPU.

Ao~ _, '---:-,

- - - ' ^/ f4:.---tRLDV~

,..---,

,

D A T A - - - «

B -

, :

L . . - - t R A C - - - "

, ,

RAS---',\ ^! I

,

I tCAC I ' - - f

CAS---""'\ ! I

210444-6

Figure 9. Read Access Time

If the WE output is externally delayed beyond the CAS active transition, then the RAM will use the fail- ing edge of WE to strobe the write data into the RAM. This WE transition should not occur too late during the CAS active transition, or else the WE to CAS requirements of the RAM will not be met.

The RASo_3, CAS, OUTO_7' and WE outputs con- tain on-chip series damping resistors (typically 20n) to minimize overshoot.

8203

Some dynamic RAMs require more than 2.4V VIH.

Noise immunity may be improved for these RAMs by

adding pull-up resistors to the 8203's outputs. Intel RAMs do not require pull-up resistors.

DYNAMIC RAM ARRAY

-

A8-1S AlO-6 OITiO-6

f-

~

^{AHO-6 --,I AO-6}

ALE BO_1 D'N

B088 B203 DouT

(16K MODE) WE

:::

^WE

ADO_7 CAS CAS

Ll

RD AAS

P

^{RD/51 RASO}

-

^{DIN DOUT}

WR WR

T.

RAS1~ - , \ r - - -

RAS2

+

-c SACK RAS3

I""

^AD-6

XACK

D'N

f=:

^{CAS WE}

_l...l

^DOUT

I--- DcNDOUT ^RAS

T

L...,r---

+

r""

AO-6

D'N

~

^{CAS WE}

D'

^DOUT

L-.. i--o RAS OINDOUT

Tl:

~ -

BAL Ab-6

D'N

~ ^{WE } N}

DIN DoUT ~T

DIN Dour Dour

CAS DiN

~~A

^{RAS DIN DouT D'N Dour Dour}

₁

^Dour

T-r 1 1

DATA BUS DATA IN / LATCH \ .

-

\I

210444-7 Figure 10. Typical 8088 System

5-7

inter

8284A

ROY

OTHER READY INPUTS

8288

8086

XACK READ WRITE

I I I

I

MULTlBUS·

TYPe SYSTEM

BUS

"'OC MWTC

BHEN

DATA

8203

I I ^READ

I ^WRITE

.

UP

^A17-419 X~:~~R I-+-+---I-~_i>_---I

HIGH BYTE WRITE

/:--="'--"J IlEMORY

DO

16

.58.

BYlES

OJ

,.

210444-8

Figure 11. 8086/256K Byte System