Propriétés électriques et modélisation des dispositifs MOS avanvés : dispositif FD-SOI, transistors sans jonctions (JLT) et transistor à couche mince à semi-conducteur d'oxyde amorphe. Electrical properties and modeling of advanced MOS devices : FD-SOI de

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Propriétés électriques et modélisation des dispositifs MOS avanvés : dispositif FD-SOI, transistors sans

jonctions (JLT) et transistor à couche mince à

semi-conducteur d’oxyde amorphe. Electrical properties and modeling of advanced MOS devices : FD-SOI

device, Junctionless Transistor, and

Amorphous-Oxide-Semiconductor Thin Film Transistor

So Jeong Park

To cite this version:

So Jeong Park. Propriétés électriques et modélisation des dispositifs MOS avanvés : dispositif FD- SOI, transistors sans jonctions (JLT) et transistor à couche mince à semi-conducteur d’oxyde amorphe.

Electrical properties and modeling of advanced MOS devices : FD-SOI device, Junctionless Transistor, and Amorphous-Oxide-Semiconductor Thin Film Transistor. Autre. Université de Grenoble; 239 - Korea University, 2013. Français. �NNT : 2013GRENT075�. �tel-00954637�

THÈ SE

Pour obtenir le grade de

DOCTEUR DE L’UNIVERSITÉ DE GRENOBLE

Spécialité : Nano Electronique et Nano Technologies (NENT)

Arrêté ministériel : 7 août 2006

Et de

DOCTEUR DE KOREA UNIVERSITY

Spécialité : Nano Electronique

Présentée par

So Jeong PARK

Thèse dirigée par Laurent MONTÈ S et Gérard GHIBAUDO codirigée par Gyu-Tae KIM

préparée au sein du Laboratoire IMEP-LAHC dans l'É cole Doctorale EEATS

et de Nano Device Laboratory Korea University

Propriétés électriques et modélisation des dispositifs MOS avancés:

FD-SOI dispositif, transistors sans jonctions (JLT) et transistor à couche mince semi-conducteur oxyde amorphe

Thèse soutenue publiquement le 23 Octobre 2013, devant le jury composé de :

Mme. Mireille MOUIS

DR CNRS Alpes-IMEP/INPG, Président

M. Moongyu JANG

DR ETRI, Rapporteur

M. Jong Tae PARK

DR Incheon National University, Rapporteur

M. Gyu-Tae KIM

DR Korea University, Co-directeur de thèse

M. Laurent MONTÈ S

MCF CNRS Alpes-IMEP/INPG, Co-directeur de thèse

M. Gérard GHIBAUDO

DR CNRS Alpes-IMEP/INPG, Directeur de thèse

Dissertation for the Degree of Doctor of Philosophy

Electrical properties and modeling of Advanced MOS devices:

FD-SOI Tri-gate device, Junctionless Transistor, and Amorphous-Oxide-Semiconductor Thin Film Transistor

Presented by So Jeong Park

School of Electrical Engineering Graduate School

Korea University

February 2014

金 奎 兌 敎授指導 博 士 學 位 論 文

Electrical properties and modeling of Advanced MOS devices:

FD-SOI Tri-gate device, Junctionless Transistor, and Amorphous-Oxide-Semiconductor Thin Film Transistor

이 論文을 工學博士 學位論文으로 提出함.

2014 年 2 月

高麗大學校 大學院 電子電氣工學科

朴 炤 貞

1

Dissertation for the degree of Doctor of Philosophy

Electrical properties and modeling of Advanced MOS devices:

FD-SOI Tri-gate device, Junctionless Transistor, and Amorphous-Oxide-Semiconductor Thin Film Tran- sistor

By So Jeong PARK

October 2013

International co-supervising program between Korea University and Grenoble INP

Thesis Advisors:

Gyu-Tae KIM

School of Electrical Engineering, Korea University, Seoul 136-701, Republic of Korea

Laurent MONTÈ S and Gérard GHIBAUDO

IMEP-LAHC, Grenoble INP-MINATEC, 3 Parvis Louis Néel, 38016 Grenoble, France

Contents

ABSTRACT ... 6

INTRODUCTION... 8

CHAPTER 1 THEORETICAL BACKGROUND ... 18

1 DOWN SCALING OF MOSFET ... 19

1.1 General down-scaling rules of MOSFET ... 19

1.2 Scaling effects on device performance ... 20

2 MOBILITY ... 23

2.1 Conductivity mobility ... 24

2.2 Effective mobility ... 25

3 DOMINANT SCATTERING EFFECTS IN MOSFET ... 26

4 THE EFFECT OF TEMPERATURE ON ELECTRICAL CHARACTERISTICS IN MOSFET ... 28

4.1 Variation of threshold voltage with temperature ... 28

4.2 Variation of subthreshold slope with temperature ... 30

4.3 Variation of carrier concentration with temperature ... 30

5 THE SERIES RESISTANCE AND THE VARIATION OF CHANNEL LENGTH IN MOSFET ... 31

6 THE SUBSTRATE BIAS EFFECT ON ELECTRICAL CHARACTERISTICS IN MOSFET ... 32

7 CONDUCTION IN AMORPHOUS OXIDE SEMICONDUCTOR THIN FILM

3

CHAPTER 2 EXPERIMENTAL BACKGROUND ... 37

1 MEASUREMENT TECHNIQUE TO AVOID ERRORS ... 38

1.1 The limit of voltmeter ... 38

1.2 The guarding technique ... 38

2 ELECTRICAL CHARACTERIZATION AND ANALYSIS ... 40

2.1 Y-function ... 40

2.2 The split C-V method ... 41

2.3 Defining the threshold voltage ... 42

2.4 Defining the series resistance and the effective channel length ... 42

2.4.1 TLM method ... 42

2.4.2 Four-probe method ... 43

2.5 Defining the trap density ... 44

2.5.1 Trap density from subthreshold swing ... 44

2.5.2 Trap density from 1/f noise ... 44

2.6 2-D numerical simulations ... 46

CHAPTER 3 SIDEWALL MOBILITY AND SERIES RESISTANCE IN MULTI- CHANNEL TRI-GATE MOSFET ... 48

1 INTRODUCTION ... 49

2 EXPERIMETAL DETAILS ... 49

3 RESULTS AND DISCUSSION ... 51

3.1 Sidewall mobility in multi-channel tri-gate MOSFET ... 51

3.2 Series Resistance in multi-channel tri-gate MOSFET ... 58

4 CONCLUSION ... 63

CHAPTER 4 IMPACT OF CHANNEL WIDTH ON BACK BIASING EFFECT IN

TRI-GATE MOSFET ... 66

1 INTRODUCTION ... 67

2 EXPERIMETAL DETAILS ... 67

3 RESULTS AND DISCUSSION ... 69

3.1 Back biasing effect on I-V characteristics and gate-to-channel capacitance ... 69

3.2 2-D numerical simulation of the back biasing effect in tri-gate MOSFET ... 74

4 CONCLUSION ... 78

CHAPTER 5 BACK BIASING EFFECTS IN TRI-GATE JUNCTIONLESS TRANSISTORS ... 81

1 INTRODUCTION ... 82

2 EXPERIMETAL DETAILS ... 83

3 RESULTS AND DISCUSSION ... 83

3.1 The back bias effect on JLTs ... 83

3.2 The back bias effect on narrow JLTs ... 85

3.3 2-D numerical simulation results of the back bias effect ... 86

4 CONCLUSION ... 88

CHAPTER 6 STATIC ELECTRICAL CHARACTERIZATION AND LOW FREQUENCY NOISE OF A-INHFZNO THIN FILM TRANSISTORS ... 92

1 INTRODUCTION ... 93

2 EXPERIMETAL DETAILS ... 93

3 RESULTS AND DISCUSSION ... 94

3.1 Static characteristics at room and low temperatures ... 94

3.2 LF Noise characteristics ... 101

5

4 CONCLUSION ... 105

CONCLUSIONS & PERSPECTIVE ... 109

APPENDIX 1: IMPEDANCE STUDY WITH BACTERIOPHAGE SOLUTION... 112

APPENDIX 2: PREAMP FOR SIMPLE MEASUREMENT ... 117

APPENDIX 3: ZNO NANOROD GAS SENSORS ... 120

APPENDIX 4: EXAMPLE OF FLEX-PDE SIMULATION SCRIPT ... 123

PUBLICATION LIST ... 125

국문초록 ... 128

RÉ SUMÉ FRANÇ AIS ... 131

ABSTRACT

ABSTRACT

Novel advanced metal-oxide semiconductor (MOS) devices such as fully-depleted-silicon-on- insulator (FD-SOI) Tri-gate transistor, junctionless transistor, and amorphous-oxide-semiconductor thin film transistor were developed for continuing down-scaling trend and extending the functionality of CMOS technology, for example, the transparency and the flexibility. In this dissertation, the electri- cal characteristics and modeling of these advanced MOS devices are presented and they are analyzed.

For the theoretical basis, at first, the scaling effect in MOS devices was briefly covered. With down- scaling trends, CMOS devices technology has scaling effects such as short channel effects and narrow channel effects. While the device scale is shrunk, the general scaling rule can be applied to keep the device performance. And mobility, the important parameter to characterize the device can be defined as conductivity mobility and the mobility in metal-oxide semiconductor field effect transistor (MOSFET). The effective mobility in MOSFET is affected by several scattering mechanisms, which mainly consist of lattice scattering, ionized impurity scattering, and surface roughness scattering. Ac- cordingly, the effect of dominant scattering effects is shown as device operation influenced by tem- perature and the effective field. Besides, the performance of the device is varied by the series re- sistance and the substrate bias. At last, the conduction in amorphous oxide semiconductor thin film transistor incorporating the band-tail states was introduced.

For the measurement of the electrical characteristics of MOSFET, the proper measurement equipment should be utilized. It is worth to note that several kinds of voltmeter have different measurement limit each other. The practical tips for precise measurements such as the guarding technique are also im- portant to avoid possible measurement errors. The electrical parameters can be extracted by the char- acterization methods such as Y-function and C-V measurement technique. In addition, there are ex- traction methods for electrical parameter, for example, the threshold voltage, the series resistance and trap density. 2-dimensional (2-D) numerical simulation is also indispensable tool for the proper physi- cal interpretation of electrical characteristics in MOSFET.

The sidewall mobility trends with temperature in multi-channel tri-gate MOSFET showed that the

sidewall conduction is dominantly governed by surface roughness scattering. The degree of surface

roughness scattering was evaluated with modified mobility degradation factor. With these extracted

parameters, it was noted that the effect of surface roughness scattering can be higher in inversion-

mode nanowire-like transistor than that of FinFET. The series resistance of multi-channel tri-gate

MOSFET was also compared to planar device having same channel length and channel width of mul-

ti-channel device. The higher series resistance was observed in multi-channel tri-gate MOSFET. It

ABSTRACT

7

The impact of channel width on back biasing effect in n-type tri-gate MOSFET on SOI material was also investigated. The suppressed back bias effects was shown in narrow device (W

= 20 nm) due to higher control of front gate on overall channel, compared to the planar device (W

= 170 nm).

The variation of effective mobility in both devices was analyzed with different channel interface of the front channel and the back channel. In addition, 2-D numerical simulation of the the gate-to- channel capacitance and the effective mobility successfully reconstructed the experimental observa- tion. The model for the effective mobility was inherited from two kinds of mobility degradations, i.e.

different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility.

With comparison to inversion-mode (IM) transistors, the back bias effect on tri-gate junctionless tran- sistors (JLTs) also has been investigated using experimental results and 2-D numerical simulations.

Owing to the different conduction mechanisms, the planar JLT shows more sensitive variation on the performance by back biasing than that of planar IM transistors. However, the back biasing effect is significantly suppressed in nanowire-like JLTs, like in extremely narrow IM transistors, due to the small portion of bulk neutral channel and strong sidewall gate controls.

Finally, the characterization method was comprehensively applied to a-InHfZnO (IHZO) thin film transistor (TFT). The series resistance and the variation of channel length were extracted from the transfer curve. And mobility values extracted with different methods such as split C-V method and modified Y-function were compared. The static characteristic evaluated as a function of temperature shows the degenerate behavior of a-IHZO TFT inversion layer. Using subthreshold slope and noise characteristics, the trap information in a-IHZO TFT was also obtained. Based on experimental results, a numerical model for a-IHZO TFT was proposed, including band-tail states conduction and interface traps. The simulated electrical characteristics were well-consistent to the experimental observations.

For the practical applications of novel devices, the electrical characterization and proper modeling are essential. These attempts shown in the dissertation will provides physical understanding for conduc- tion of these novel devices.

Keywords: advanced MOS transistors, multi-channel tri-gate MOSFET, junctionless transistor, side-

wall mobility, surface roughness scattering, series resistance, electrostatic coupling, channel width

variation, back bias effect, 2-D numerical simulation, a-InHfZnO, thin film transistor (TFT), DC char-

acteristics, electrical parameter extraction, low frequency noise (LFN), numerical simulation.

INTRODUCTION

INTRODUCTION

The most important trend of CMOS technology is to decrease the minimum feature size and cost-per- function. According to the ITRS roadmap, the minimum feature size of MOSFET in 2026 is predicted as 6 nm [1]. The CMOS scaling consists of two approaches, geometrical scaling and equivalent scal- ing. Geometrical scaling reduces the physical feature size according to Moore’s law, inspiring semi- conductor industry. The equivalent scaling improves the performance of the devices and is increasing- ly important from nowadays and new design/processing or software solutions are needed for the scal- ing. As the size of device is shrunk extensively, more efforts to maintain the performance of devices is dedicated against short channel effects, dopant-induced fluctuation in threshold voltage, etc [2-4]. For example, high-k gate dielectric has been used to scale down the equivalent oxide thickness (EOT) with keeping tolerable gate leakage current. Metal gate electrodes are employed in the CMOS device of recent generation for efficient gate control to channel since even degenerately doped polysilicon gate reduces metal-oxide-semiconductor capacitance with its depletion layer [5]. Higher-k dielectric and appropriate metal gates are required for further scaling as shown in Fig. 1. In addition, metal gate provides low gate resistance and efficient heat sink which is for power aspect. To improve the channel carrier low-field mobility, strained silicon is also used as a channel material [6, 7] and higher mobility materials, for example, SiGe, Ge, and III-V compound semiconductor will be used. (Fig. 1) Instead of thick body partially-depleted-silicon-on-insulator (PD-SOI) or bulk MOSFET, ultra-thin body fully-

2011 ITWG Table Timing 2007 2010 2013 2016 2019 2021

Figure 1 2011 ITRS “Equivalent Scaling” Process Technologies Timing [1]

INTRODUCTION

9

depleted-silicon-on-insulator (FD-SOI) and multiple-gate MOSFET are expected as potential device to eliminate the variation threshold voltage corresponding to increased doping concentration.

On the other hand, various channel material, device architecture and technologies are required to meet the need of ultra-low power consumption and new functionality. For example, thin film transistor (TFT) is a promising device for flexible and transparent electronic circuit. The active channel material is deposited at low temperature (< 600

C), thus glass substrate and flexible substrate can be used and the channel material is amorphous. TFT can be widely used for large-area transparent and flexible display [8, 9] which are challenging with conventional semiconductor processing. For these applica- tions, TFT is feasible device type since the required device performance such as response speed and the driving current is not quite critical while it is not used for integrated circuits owing to its low channel mobility.

For the realization of these advanced devices, it is required to investigate their electrical properties compared to classical transistor and to optimize their performance. To perform this task, physical pa- rameters of these new devices should be evaluated based on analysis method of classical silicon de- vices which has been enormously investigated during previous decades. The development of their de- vice model and the investigation of special mechanisms governing their electrostatics accompanying with special electrical properties and non-conventional effects should be carried

Figure 2 Multigate MOSFETs (a) SOI FinFET (b) SOI triple-gate MOSFET (c) SOI Π-gate

MOSFET (d) SOI Ω-gate MOSFET (e) SOI gate-all-around MOSFET (f) A bulk tri-gate

MOSFET [10]

INTRODUCTION

out.

Fully-depleted silicon-on-insulator (FD-SOI) Trigate device is one of the new potential structures for continuing scaling down CMOS technology [10]. Indeed, FD-SOI structure eliminates punch-though effect with the shallow source/drain region and it can be free from the high channel doping problem [11]. It is very difficult to control the concentration of channel doping in extremely small device and spatial random dopant fluctuation seriously degrades the device reliability. Low channel doping con- centration of FD-SOI device also enables to achieve enhanced channel mobility. Furthermore, the par- asitic capacitance between interconnect metal lines and substrate is reduced owing to the buried oxide and the switching speed is enhanced. The reduction of parasitic devices, called as latch-up phenome- non in CMOS ICs is another benefit of using FD-SOI structure. With FD-SOI structure, the imple- mentation of multi-gate structure can also be interesting to enhance device performance. Multi-gate MOSFET shows the best subthreshold swing and significant reduction of off-state current [12, 13]. It shows better control of short channel effects [14] since the influence by drain field on the channel is reduced [15]. As shown in Fig. 2, the multi gate MOSFET includes FinFET, tri-gate MOSFET, Π-gate MOSFET, Ω-gate MOSFET, gate-all-around MOSFET, and a bulk tri-gate MOSFET. In recent device simulation studies, it was shown that the gate-all-around device with gate length of 3 nm could work well without significant short channel effects [16]. In addition, multi-gate device, having large chan- nel width, can be used to drive higher current than single gate device. For double gate SOI device, threshold voltage is low, compared to the bulk single gate SOI device and DIBL effect is reduced [17].

FinFET also shows many advantages such as increased drive current, reduced short channel effect and shorter access time for memory applications [18].

In 2011, among multigate structure, Trigate MOSFET was introduced to the mass industrial produc- tion by announcement, Intel will use tri-gate structure for 22-nm technology. Trigate means that a sin- gle gate electrode folded to cover three sides of transistor [19]. The gate is a common gate, thus, three gates are electrically connected and apply the same gate bias. A Trigate MOSFET shows improved gate electrostatic control to the channel and this effectively reduces short channel effects [20, 21]. It provides strong gate control over not only at the top surface channel but also on two sidewall channels (lateral channels) [22, 23]. Due to their gate control property, they have less stringent requirements for the silicon channel dimensions and larger driving current per unit area of the silicon wafer can be achieved [21, 24]. Especially, the introduction of metal gate on the trigate structure enhances the on- current and eliminates the leakage current as well as inverter delay. In narrow trigate transistors, it was shown that the device has the immunity against substrate effects caused by drain-induced virtual substrate biasing and hot carrier-induced charge build-up in the buried oxide [25]

On the other hand, the formation of ultra-shallow junctions with abrupt high channel doping concen-

INTRODUCTION

11

transistor (JLT) can be free from this difficulty since it doesn’t have junctions or doping concentration gradient corresponding to junction (Fig. 3). In addition, JLTs using silicon nanowires are compatible with CMOS process.

The junctionless transistor is a “normally on” device, however, the difference of the work function between the gate electrode and the channel silicon make the flatband voltage V

and the threshold voltage V

shifted. Below threshold, JLT is fully depleted and the carrier concentration of a part of channel of JLT reaches initial doping concentration N

at its threshold voltage. As increasing the gate voltage the region where carrier concentration is same with N

becomes larger in cross-section of the channel. Finally when the channel cross section is full with region of carrier concentration n=N

, the gate bias corresponds to the flat band voltage. The conduction mechanism in JLT was presented in Fig.

3(b).

The fabrication of JLTs is very simple since only one doping concentration is needed from source re- gion to drain region. The subthreshold slope of JLTs are excellent, exhibiting 64 mV/decade at room temperature and very close value to the ideal value of subthreshold slope in the temperature range of 225-475 K [26]. Different from the general concerning, the mobility is not seriously degraded by high doping concentration in JLTs since the electric field in the channel is almost zero, allowing bulk mo- bility values [27]. The carrier mobility of JLT is lower than that of IM device at room temperature ow- ing to the mobility dominantly governed by ionized impurity scattering. However, the decrease of mobility in JLT is less than 7 % when the temperature is increased up to 200

C while it was about 36 % with IM device [28]. Furthermore, high I

/I

ratio, lower DIBL and reduced short-channel ef-

Figure 3 (a) Longitudinal cross-section schematic of a junctionless transistor, showing the

doping profiles and (b) Drain current (log scale) versus gate voltage in a heavily-doped

junctionless transistor [18]

INTRODUCTION

fects were reported in nanowire-like JLTs [29,30]. It can be expected that the variation of the thresh- old voltages of JLTs is below 35 mV with recent technology controlling channel thickness below 0.2 nm since the variation of threshold voltage is not severe when the channel thickness of JLT is small enough [31]. The variation of L

caused by gradient of doping concentration at junction boundary is not observed in JLT.

However, JLTs are more sensitive than undoped IM devices to doping fluctuation due to its high dop- ing concentration [32]. Moreover, Rios et al reported that JLT devices show degraded gate control and short-channel behaviours and increased off current while they exhibit better mobility at moderate dop- ing concentration [33]. There is also a theoretical approach showing significant variation of threshold voltage in JLTs due to the dopant fluctuation when L

= 20 nm [34].

Another candidate for advanced MOS device technology, transparent amorphous oxide semiconductor (AOS) based TFTs have gotten great interest for the applications in flexible displays, flat-panel dis- plays, optical sensor, solar cells, transparent and/or flexible electronic devices since they can be fabri- cated on plastic substrates at relatively low temperature [9, 35]. They also can be used for the highly uniform and large-area displays with low cost [36]. Among the AOS TFT, a-InGaZnO (a-IGZO) TFT has been intensively studied because it exhibits high mobility, a good on/off ratio and sufficient elec- trical stability [37]. It is mostly used for the application of switching/driving devices in active-matrix liquid crystal display (AMLCD) and active-matrix organic light emitting diode display (AMOLED) back planes due to its excellent electrical properties, compared to a-Si TFT [9].

The scaling effects on electrical properties of a-IGZO TFTs were investigated by Cho et al [38]. They

examined the threshold voltage shift, subthreshold swing degradation and the field-effect mobility in

scaled-down devices owing to short-channel effect and contact resistance. Stability issue in AOS TFTs

INTRODUCTION

13

has also been intensively studied by researchers. In many research results, the variation of threshold voltage in AOS TFT after electrical stress comes from charge trapping/detrapping at, or close to, channel/insulator interface [39-41]. It takes times, from few minutes to few hours, to recover the orig- inal properties of AOS TFT [42, 43] and, in some cases, heating treatment is required for the recovery.

It is reported that using passivation layer improves the stability of AOS TFT [44, 45]. For what con- cerns the dielectric layer, high-k material increases the gate capacitance, leading to low subthreshold swing though high trap density. But most of high-k dielectric has issues of high leakage current, low breakdown voltage and rough surface [46, 47]. Park et al reported that the introduction of Hf to chan- nel materials enables to fabricate highly stable and high performance TFT devices. Concerning the reliability of AOS TFT, the investigation of interface states is also important. Low frequency noise measurements in AOS TFTs have provided meaningful trap information in AOS TFTs [48-50]

The objective of this thesis lies on the development of the advanced semiconductor device models and the characterization of the conduction mechanisms in these devices. This thesis covers three kinds of devices: inversion-mode trigate FD-SOI MOSFET, Junctionless transistor and AOS TFT. In chapter 1, the trend of device technology and effects corresponding to scaling are briefly introduced with theo- retical background of the thesis. And some measurement precautions and electrical characterization methods, needed to study the electrical conduction in devices are followed in chapter 2.

In Chapter 3, the sidewall mobility and the series resistance in multi-channel tri-gate MOSFET are discussed via low temperature characteristics and examined by 2-D numerical simulation.

The impact of channel width on back biasing effect in multi-channel tri-gate MOSFET and the analy- sis of mobility behavior corresponding to interface quality are presented in chapter 4.

The back bias effect on tri-gate junctionless transistors (JLTs) using experimental results and 2-D nu- merical simulations are described in chapter 5.

In chapter 6, electrical characterization of amorphous InHfZnO (a-IHZO) TFTs through static charac-

teristic, low frequency noise characteristic and 2-D numerical simulation are summarized.

INTRODUCTION

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INTRODUCTION

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INTRODUCTION

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INTRODUCTION

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CHAPTER 1 THEORETICAL BACKGROUND

CHAPTER 1

1 THE SCALING OF MOSFET

1.1 GENERAL DOWN-SCALING RULES OF MOSFET 1.2 Scaling effects on device performance

2 MOBILITY

2.1 Conductivity mobility 2.2 Effective mobility

3 DOMINANT SCATTERING EFFECTS IN MOSFET

4 THE EFFECT OF TEMPERATURE ON ELECTRICAL CHARACTERISTICS IN MOSFET 4.1 Variation of threshold voltage with temperature

4.2 Variation of subthreshold slope with temperature 4.3 Variation of carrier concentration with temperature

5 THE SERIES RESISTANCE AND THE VARIATION OF CHANNEL LENGTH IN MOSFET 6 THE SUBSTRATE BIAS EFFECT ON ELECTRICAL CHARACTERISTICS IN MOSFET

7 CONDUCTION IN AMORPHOUS OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR (AOS TFT)

THEORETICAL BACKGROUND

In this chapter, the general scaling rule in MOSFET to maintain the performance of the device is in-

troduced. However, practically, the effect of scaling on the operation of the device such as short chan-

nel effect or narrow channel effect is common in I-V characteristics of MOSFET. Carrier mobility, an

important parameter to evaluate the device performance can be determined from several concepts. The

effective mobility in MOSFET is influenced by the scattering mechanisms which mainly consist of

lattice scattering, ionized impurity scattering, and surface roughness scattering. The device operation

is also affected by temperature, series resistance, and substrate bias. At last, the conduction mecha-

nism in amorphous oxide semiconductor thin film transistor is described.

CHAPTER 1 THEORETICAL BACKGROUND

19

1 DOWN SCALING OF MOSFET

1.1 General down-scaling rules of MOSFET

As the channel length of MOSFET is decreased, proper adjustment of other device parameters is needed to maintain the device performance. When the channel length is reduced, depletion widths of source and drain region meet each other and electrons are pulled by drain field from the source, which is called as punch-through effect. To prevent this effect, higher channel doping is required. For P-type substrate (N

≪ N

), the depletion layer width at source/drain is given as [1];

A R bi s p

d

qN

V w V

w 2 (  )



 

(1.1)

where w

is the depletion layer (m) of p-type silicon, 

is the dielectric permittivity (F/m) of the semiconductor, V

is the built-in potential, V

is a reverse-biased voltage. However, introducing more dopants to the channel increases the threshold voltage V

because of higher body factor  (V

),

SB F F

FB

T

V V

V   2    2   (1.2a)

ox D s

C

 qN

  ² (1.2b)

V

is the flat-band voltage, 

is the Fermi potential, V

is source-to-bulk voltage and C

Channel length L L/S

Channel width W W/S

Gate-oxide thickness t

t

/S

Substrate doping N

N

Drain current I

) I

× S Input capacitance C

C

/S Maximum switching frequency f ∝ I

/C

f × S

Cell area A ∝ WL A/S

Table 1 Down scaling

rules of MOSFET when

the gate length is re-

duced by S times.

CHAPTER 1 THEORETICAL BACKGROUND

is the gate-oxide capacitance (F/m

). In order to keep reasonable threshold voltage value, the thickness of the gate oxide should be reduced. Accordingly, the input capacitance is increased and it is fixed by reduced channel width. The down scaling rules when the gate length is reduced by S times are sum- marized in Table 1.

1.2 Scaling effects on device performance

For a given current density, the channel mobility of short channel device is related to the drift velocity for given electric fields E as;

v

= -μ

E (for electrons) (1.3a) v

= μ

E (for holes) (1.3b)

At low electric fields, the drift velocity has linear relation with the electric field as shown in Eq. (1.3a) and Eq. (1.3b). However, when the electric field is high, the drift velocity trend saturated to a constant value, deviating from the linear relation. It occurs before the pinch-off condition. In extremely short devices, the saturated velocity severely limits the drain current.

Drain induced barrier lowering (DIBL), the one of the short channel effects, is the origin of punch- through effect. As shown in Fig 2, it causes the barrier at source end to reduce by high drain bias and

Figure 1 Inversion drift velocity versus longitudinal field for various transverse fields. [2]

CHAPTER 1 THEORETICAL BACKGROUND

21

the substantial increase of the drain current [3]. With punch-through effect, DIBL is presented by the reduction of threshold voltage and the increase of off-state current with drain voltage. For short chan- nel devices, the subthreshold drain current increases with drain voltage while subthreshold swing is increased as a result of threshold voltage shift. On the other hand, the subthreshold drain current is not changed with drain voltage in long channel device [4]. For extreme case of DIBL, the device doesn't turn-off.

The narrow width effect (NWE) is another scaling related effect. It corresponds to an increase of the threshold voltage when the channel width is below 1μm in device using LOCal Oxidation of Silicon isolation. When the channel width is comparable to the edge effect region, the wider depletion region

Figure 2 The energy-band diagram from source to drain at V

> 0 V for (a) long channel and (b) short channel in transistor. Dashed line for V

= 0 V [3].

(a) (b)

0.0 0.5 1.0 1.5

10^-6 10^-5 10^-4 10^-3 10^-2

I

(A)

V

(V)

V_ds = 0.05 V V_ds = 1 V

0.0 0.5 1.0 1.5

10^-11 10^-9 10^-7 10^-5 10^-3 10^-1

I

(A)

V

(V)

L = 30 nm L = 100 nm

V_ds= 0.05 V V_ds= 1 V

L = 100 nm L = 30 nm

Figure 3 Drain characteristics of MOSFETs showing DIBL effects. (a) Transfer curves with L

= 30 nm at V

= 0.05 V and V

= 1 V. (b) Transfer curves with L = 30 nm and L = 100 nm at

V

= 1 V.

CHAPTER 1 THEORETICAL BACKGROUND

by the gate voltage is observed. As a result, the depletion charge by gate voltage is increased and the

(a) (b)

Figure 4 (a) transfer characteristic (b) extracted access resistances of 60 nm-gate length Fin- FET for different fin widths (W

) [5]

Shallow Trench Isolation MESA isolation

Figure 5 Variation of the threshold voltage with various channel widths for shallow trench

isolation and MESA isolation. [6, 7]

CHAPTER 1 THEORETICAL BACKGROUND

23

trench isolation, the threshold voltage decreases with narrow channel width due to the gate fringing field [6]. In contrast, the thin channel device using MESA isolation shows increased threshold voltage with narrow channel configuration which eliminates effects of positive oxide fixed charge in BOX [7].

In SOI device, the narrow channel width is useful for better controllability for short channel effect.

FinFET with narrow channel width exhibits limited DIBL and improved transport properties with small variation of threshold voltage [5, 8]. For gate-all-around nanowire devices, the subthreshold swing was reduced with using very narrow nanowire [9]. However, as the channel width is reduced, series resistance increases, which causes the decrease of drain current [10]. In multi-gate FETs, the device with heavily doped channel may present corner effect. As gate voltage is increased, the top corner of channel reaches inversion before top and sidewall surface channel is formed due to the over- lap of electric field from top gate and sidewall gate. Figure 6 shows the derivative of transconductance curves for multi-gate FET with various channel doping concentrations from 10

to 5 × 10

cm

. The corner effect is illustrated by the derivative of transconductance curve having two humps when chan- nel doping is high, corresponding to channel formation at top corner and surface. However, the corner effect is eliminated in a device with low channel doping concentration [11].

2 MOBILITY

Carrier mobility is a macroscopic transport property characterizing semiconductor materials as well as device performance. Mobility can be affected by microscopic properties such as the effective mass and the degree of carrier scattering. For multiple scattering mechanisms, the net mobility  is de- rived from the various mobilities, by Mathiessens's rule;

Figure 6 The derivative of transconductance

in Ω-FET with various channel doping con-

centrations from 10

to 5 × 10

cm

[11].

CHAPTER 1 THEORETICAL BACKGROUND







2 1

1 1 1





 ^(1.4)

There are several kinds of mobility according to the definition method such as the conductivity mobil- ity, Hall mobility, and effective mobility in MOSFET.

2.1 Conductivity mobility

The conductivity mobility is determined by measuring carrier concentration and the conductivity. For n-type semiconductor, the relationship between the conductivity  (S/cm) and the conductivity mo- bility 

(cm

/Vs) given by:[12]

qn 



(1.5)

where, q is the electron charge, n is the electron concentration (/cm

).

The conductivity mobility comes from the drift of group of carriers by external electric field E. For example, when the external field in x-direction E

is applied to a group of carriers, the group of car- riers is forced by

qE

to move in x-direction. The average velocity of the group of carrier is called average particle drift velocity

v

.

.

The conductivity mobility 

is defined as the proportionality constant of the drift velocity to the electric field E

. The net motion of the group of carriers is accelerated by the external field, however, there are many scattering sites such as crystal defects, vacancies, dislocations, impurities in a solid.

Thus, the velocity of electrons is saturated with a constant electric field E

.

n x x

x

p qt E E

v







(1.6)

E_x

(a) (b)

Figure 7 Drift of an electron as a result of thermal motion. (a) When there is no electric

field, the electron randomly moves but ends up with no net displacement; (b) when an elec-

tric field is applied, the electron drifts opposite to the direction of the field and has a net

displacement (and therefore a drift velocity).

CHAPTER 1 THEORETICAL BACKGROUND

25

where,

p

is the average momentum per electron, t is the mean free time, and m

is the effective mass of electron.

From the drift, the current density J

is defined by:







 _x

x

qn v

J (1.7)

where - q is the charge of electron and n

v

is the number of electrons crossing a unit area per unit time [13].

And the current density is expected to be proportional to the applied electric field with Ohm’s law as;

x

x

E

J

 (1.8)

Applying Eq (1.6) and (1.7) to Eq. (1.8), the relation between the conductivity mobility and the con- ductivity shown in Eq. (1.5) is established.

2.2 Effective mobility

When the carrier flow is limited in the inversion layer the mobility is low, compared to the bulk mo- bility due to the interface effect and thin thickness of the inversion layer.

The effective mobility 

is obtained at low drain voltage as:

d n eff d

V WQ

L



I

 (1.9)

where I

is the drain current and Q

is the channel charge density (C/m

), and V

is the drain voltage.

There are two ways to obtain the channel charge density Q

. The channel charge density Q

can be approximated by just multiplying the effective oxide capacitance per unit area C

(F/m

) with over- drive gate voltage at strong inversion V

(

V

V

) as:

gt ox

n

C V

Q

(1.10)

It is simple but there are difficulties to obtain the exact value of C

and the threshold voltage V

. Another way is to obtain Q

directly from the measurement of gate-to-channel capacitance.





 Vg s

gs gs

n

C dV

Q (1.11)

where C

is the gate-to-channel capacitance per unit area. Usually, it provides better results, com- pared to the previous one [12].

As described in (Eq 1.6), the mobility is proportionality constant of velocity to electric field. When

the field is low, the velocity is linearly increased with electric field and the mobility is constant. How-

CHAPTER 1 THEORETICAL BACKGROUND

ever, at high field, the velocity is saturated to constant value. When the electric field is between these two regimes, the effective mobility is given as;

n C n

eff

E E

0

] ) / ( 1 [





 (1.12)

where 

is the low field mobility and E

is the critical field. n is 2 for electrons and 1 for holes in silicon [3, 14]. The effective mobility is higher with lower channel doping concentration owing to reduced normal field and low threshold voltage.

The effective mobility 

includes mobility degradation by the several scattering mechanisms such as phonon scattering, ionized impurity scattering and surface roughness scattering. The scattering effect is varied by the transverse field by gate bias and it can be presented in MOSFET by empirical relation as [15];

2 2 1

0

) (

) (

1

eff  

V

V

V

V





  (1.13)



, 

are mobility degradation factors which are affected by gate oxide thickness and doping con- centration. While classical effective channel mobility is presented by only first-order mobility degra- dation factor 

, recent MOSFETs have been scaled down and the second-order mobility 

degra- dation factor is required since the drain current is significantly degraded at high field. It is known that this degradation is due to surface roughness scattering [16].

Mo bi lit y (cm

/Vs )

10³

10²

10¹⁴ 10¹⁵ 10¹⁶ 10¹⁷ 10¹⁸ 10¹⁹

Impurity concentration (cm

)

Silicon

μ_n

Figure 8 Electron mobility in silicon as a function of impurity concentration

CHAPTER 1 THEORETICAL BACKGROUND

27

There are several scattering mechanisms which influence the mobility of MOSFET. They are phonon scattering (lattice scattering), Coulomb scattering (Ionized impurity scattering), and surface roughness scattering. Depending on the temperature and the effective electric field or the carrier concentration, different scattering mechanism governs the mobility behavior of MOSFET. The universal mobility

Coulomb

scattering Surface

roughness scattering

Phonon scattering

Low

High Temperature

Total Mobility

EFFECTIVE FIELD E

MO BIL ITY

Figure 9 Schematic diagram of effective mobility as a function of the effective field E

with three scattering mechanisms, Phonon scattering, Coulomb scattering, and Surface rough- ness scattering

T (K) (log scale) μ (cm

/Vs)

(log scale)

scattering

Lattice scattering

T

T

Figure 10 Approximate temperature dependence of mobility with both lattice and impurity

scattering

CHAPTER 1 THEORETICAL BACKGROUND

behavior according to these scattering mechanisms depends on the effective field as shown in Fig. 9 [17].

At given temperature, crystalline lattice is vibrating with thermal energy. These vibrations are repre- sented by particle called as "phonon". When a carrier moves in vibrating crystal lattice, this carrier is scattered by this vibration. As temperature increases, more vibration occurred and the mobility is re- duced since the scattering rate increases. The mobility limited by phonon scattering is decreased with temperature (μ ~T

in silicon) [3].

One of important scattering mechanisms for carrier transport is ionized impurity scattering. When temperature is low, lattice scattering is less important due to reduced lattice vibration, thus, ionized impurity scattering becomes the dominant scattering mechanism. In contrast with the effect of lattice scattering, the mobility increases with temperature (Fig. 10) since a carrier which moves fast with higher thermal energy less interacts with a charged ion than one moving slowly. The mobility approx- imately depends on the temperature as T

in silicon, owing to ionized impurity scattering. When the concentration of ionized impurities is high, the mobility limited by impurity scattering is shown at higher temperatures.

Phonon scattering always involves the mobility behavior and, especially, it dominantly affects the ef- fective mobility at room temperature. When the carrier concentration is not high, Coulomb scattering is important for the determination of the effective mobility while the surface roughness scattering be- come important with high carrier concentration. Surface roughness scattering strongly affects the mo- bility behavior when the transistor is in strong inversion regime.

Surface roughness in the MOS structure is related to the random fluctuation of surface, which is rep- resented by atomic step, between oxide insulator and channel silicon. The fluctuation creates the di- poles at the interface, inducing electrical potentials. It is expected the surface roughness always exists at the interface between insulator and channel due to the misfit of the lattice spacing and the existence of interfacial stress due to the difference in thermal expansion coefficient.

4 THE EFFECT OF TEMPERATURE ON ELECTRICAL CHARACTERISTICS I N MOSFET

4.1 Variation of threshold voltage with temperature

The threshold voltage in MOSFET is defined as the sum of the flat band voltage, the surface potential of 2 

, and the voltage drop across the oxide (Fig. 11(a));

ox B A B s

fb

th

C

V qN

V 2 ( 2 )

2  







(1.14)

CHAPTER 1 THEORETICAL BACKGROUND

29 ox

B A B s

ox ms f

C qN C

Q 2 ( 2 )

2  







where V

is the flat-band voltage, 

the Fermi potential, 

is the dielectric permittivity of the semiconductor, N

is the substrate doping level (/m

), C

is the gate oxide capacitance (F/m

), Q

is the fixed oxide charges (C/m

), and 

is the work function difference between the gate material and the semiconductor. Because 

, Q

and C

are independent of temperature, the derivative of threshold voltage with temperature is given as;











 



B A s ox B

th

qN

C dT

d dT dV





 1

2 (1.15)

And 

is given as;



 



 

i B A

n N q kT ln

 (1.16)

Since, n

N

N

exp(

E

/ 2 kT )







 



q

E T

dT

d

B B

2

1 

 (1.17)

Adopting above equation to the equation of derivative of threshold voltage, E

E

E E

qψ

qψ

(a) (b)

Figure 11 (a) Energy-band diagram and (b) the derivative of the threshold voltage with

temperature as a function of the oxide thickness d with various doping concentration [3].