NVAX CPU Chip

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NVAX CPU Chip

Functional Specification·

The NVAX CPU Chip is a high-perform~r..ce,single-chipimplerru:tntatioI1 of ^the,·VAX Ar~itecture for use in low-end and mid-range systems. :"

Revlslon/Update Information: This is Revision 12 of this specification, wtiichsUP$r~d.esJ1evi,sion 1.1 re- leased in August 1991. The inform ation in this speelfication)eflects pass 2 of the NVAX CPU chip. Only the Electrioal Charact~ti.sti¢s:,Ctita:pter was updated from:,f1evision'·1.1 to Revision 1 .2.

DIGITAL CONFIDENTJA'C'

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This information shall not be discloSed to persons otherthan.~~GITAL:emptoy.es;br·\1erirJ.y.;d-tStribute.d ~ithin ' DIGITAL. Distribution is restricted to persons auth.?r~ed aOO ;~signat~ by tmt·'o.tjgif1alij1g'btg~~iz~~qn ... 1hi$> ..

document shall not be transmitted ,electronically, copied unle~"auti:lo~~igh1atinffOf9ariizatioFi~'orleft unattended. When not in use,

this

doelim&rit§hafI'-'be stored;'in al()Ckecr*-r.s~~;:atr •• ·; The"-restrictionsare enforced until this document is reclassif!,~~by:the~~,inating .organizati!?",!:, '~'. ~:-"'~::::';11;0:'.:;~'·<:· "~0i;C ^:',. ^{'.. :.}

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.... ' ... Semiconductor- Engi'A$sring Group Digital Equipment CorpOteit~on, HudsonrMasSClchusetts

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items without written permission.

The information in this document may be changed without notice and is not a commitment by Digital . Equipment Corporation. Digital Equipment Corporation is not responsible for any errors in this document.

This specification does not describe any program or product that is currently available from Digital Equipment Corporation, nor is Digital Equipment Corporation committed to implement this specification in any program or product.' -Digital Equipment Corporation makes no commitment that this document accurately describes any product it might ever make.

Printed in U .SA

" The fonowing are trademarks ot:Digttal Equipment Corporation:

DEC DECnet DECUS MicroVAX MicroVMS PDP

. ^, ULTRIX ULTRIX-32 UNIBUS VAX VAXBI VAXcluster

VAXstation

VMS

VT

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3.3.3.1.7 P%CPU_SUPPRESS_L • 3-20 3.3.3.1.8 101_SUPPRESS_L • 3-21 3.3.3.1.9 102_SUPPRESS_L • 3-21 3.3.3.1.10 PO,4CPU_GRANT_L • 3-21 3.3.3.1.11 101_GRANT_L • 3-21 3.3.3.1.12 102_ GRANT _L • 3-21 3.3.3.1.13 PO,4CPU_WB_ONLY_L • 3-21 3.3.3.1.14 101_WB_ONLY _L • 3-22 3.3.3.1.15 102_WB_ONLY _L • 3-22 3.3.3.2 NDAL Arbitration liming • 3-22 3.3.3.3 NDAL Suppress and Its liming • 3-24 3.3.3.4 NDAL Arbitration Rules • 3-24

DIGITAL CONFIDENTIAL v

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3.3A NDAL Information Transfer 3-27 3.3.4.1 POkNDAL_H<63:0> • 3-27

3.3.4.1.1 Address Field • 3-27 3.3.4.1.2 Byte Enable Field • 3-29 3.3.4.1.2.1 110 space writes • 3-33 3.3.4.1.3 Length Field • 3-33 3.3.4.2 P%CMD _H<3:0> • 3-33 3.3.4.3 POkID_H<2:0> • 3-35 3.3.4.4 POkPARITY _H<2:0> • 3-35 3.3.4.5 P%ACK_L • 3-36

3.3.5 NDAL Transactions 3-38

3.3.5.1 Reads and Fills • 3-41

3.3.5.1.1 Dstream Read Requests (DREAD) • 3-41 3.3.5.12 Istream Read Requests (IREAD) • 3-41 3.3.5.1.3 Ownership Read Requests (OREAD) • 3-41

3.3.5.1.4 How memory handles reads to Owned blocks • 3-42 3.3.5.1.5 Read cycle description and timing • 3-42

3.3.5.1.6 Read Data Return cycles (RDRO, RDR1, RDR2, RDR3) • 3-44

3.3.5.1.7 Read data error cycles (ROE) • 3-44

3.3.5.1.8 Read data cycle description and timing • 3-45 3.3.5.1.9 Read Transaction Examples • 3-45

3.3.5.1.9.1 Ouadword Read and Fill • 3-45 3.3.5.1.9.2 Multiple Ouadword Reads • 3-47 3.3.52 Writes· H9

3.3.5.2.1 Normal Write Transactions (WRITE) • 3-49 3.3.5.22 Disown Write Transactions (WDISOWN) • 3-49

3.3.5.2.3 Write Data and Bad Write Data (WDATA,BADWDATA) • 3-49 3.3.5.2.4 Write transaction description and timing • 3-49

3.3.5.2.5 Write Transaction Examples • 3-50 3.3.5.2.5.1 Ouadword Writes • 3-50

3.3.5.2.5.2 Multiple Ouadword Writes • 3-52 3.3.5.3 NOPs· 3-53

3.3.6 Cache Coherency 3-54

3.3.7 Interrupts 3-55

3.3.8 Clear Write Buffer 3-55

3.3.9 VAX. archltecturally-deflned Interlocks 3-56

3.3.9.1 Ownership and Interlock transactions • 3-56

3.3.10 Errors 3-57

3.3.10.1 Transaction Timeout • 3-57

3.3.10.2 Non-existent memory and VO • 3-58 3.3.10.3 Error Handling • 3-58

3.3.10.4 Error Recovery • 3-63

3.3.11 NDAL Initialization 3-64

3.4 THE XMI-2 NVAX. SYSTEM 3-65

3A.1 Cache coherency In the XMl2 system 3-65

3.5 THE LOWEND NVAX SYSTEM - OMEGA 3-67

3.6 RESOLVED ISSUES 3-68

3.7 NVAX. CHIP INTERFACE SIGNAL NAME CROSS-REFERENCE 3-70

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Contents

CHAPTER 4 CHIP OVERVIEW 4-1

4.1 NVAX CPU CHIP BOX AND SECnON OVERVIEW 4-1

4.1.1 Thelbox 4-2

4.1.2 The Ebox and Mlcrosequencer 4-3

4.1.3 The Fbox 4-3

4.1.4 The Mbox 4-4

4.1.5 The Cbox 4-4

4.1.6 Major Internal Buses 4-4

CHAPTER 5 MACROINSTRUCTION AND MICROINSTRUCTION PIPELINES 5-1

5.1 INTRODUCTION 5-1

5.2 PIPELINE FUNDAMENTALS 5-1

5.2.1 The Concept of a Pipeline 5-1

5.2.2 Pipeline Flow 5-3

5.2.3 Stalls and exceptions in an Instruction Pipeline 5-5

5.3 NVAX CPU PIPELINE OVERVIEW 5-6

5.3.1 Normal Macroinstruction Execution 5-8

5.3.1.1 The Ibox • 5-8

5.3.1.2 The Microsequencer • 5-9 5.3.1.3 The Ebox • 5-9

5.3.1.4 The Fbox • 5-10 5.3.1.5 The Mbox • 5-10 5.3.1.6 The Cbox • 5-11

5.3.2 Stalls In the Pipeline 5-11

5.3.2.1 SO Stalls • 5-12 5.3.22 S1 Stalls • 5-12 5.3.2.3 S2 Stalls • 5-13 5.3.2.4 S3 Stalls • 5-14 5.3.2.5 S4 Stalls • 5-15

5.3.3 exception Handling 5-16

5.3,3.1 Interrupts • 5-17

5.3.32 Integer Arithmetic Exceptions • 5-17 5.3.3.3 Floating Point Arithmetic Exceptions • 5-17 5.3.3.4 Memory Management Exceptions • 5-18 5.3.3.5 Translation Buffer Miss • 5-19

5.3.3.6 Reserved Addressing Mode Faults • 5-19 5.3.3.7 Reserved Operand Faults • 5-20

5.3.3.8 Exceptions Occurring as the Consequence of an Instruction • 5-20

5.3.3.9 Trace Fault • 5-20

5.3.3.10 Conditional Branch Mispredict • 5-20 5.3.3.11 First Part Done Handling • 5-21

5.3.3.12 Cache and Memory Hardware Errors • 5-21

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CHAPTER 6 MICROINSTRUCTION FORMATS 6.1

6.2 6.3 6.4

EBOX MICROCODE

6.1.1 Data Path Control 6.1.2 Mlcrosequencer Control IBOX CSU MICROCODE

IBOX INSTRUCTION ROM AND CONTROL PLAS REVISION HISTORY

CHAPTER 7 THE IBOX 7.1

7.2

7.3

OVERVIEW

7.1.1 Introduction 7.1.2

7.1.3

Functional Overview The Pipeline

INSTRucnON STREAM PREFETCHING 7.2.1 The VIC

7.2.1.1 VIC Control • 7-7 7.2.1.2 VIC_Reads· 7-8 7.2.1.3 VIC Fills • 7-8 7.2.1.4 VIC Writes • 7-9 7.2.1.5 VIC Bypass • 7-9

7.2.1.6 VIC Hits Under Miss • 7-10 7.2.1.7 VIC Exceptions and Errors • 7-10 7.2.1 .8 PC Load Effects • 7-10

7.2.1.9 E%STOP _IBOX_H Effects • 7-11 7.2.1.10 Prefetch Stop Conditions • 7-12 7.2.1.11 Prefetch Start Conditions • 7-12

7.2.1 .12 Prioritized List of Prefetch Start/stop Conditions • 7-12 7.2.1.13 VIC Enable • 7-13

7.2.1.14 VIC Flushing • 7-13 7.2.1.15 Flushing IREFs • 7-13

7.2.1.16 VIC Control and Error Registers • 7-14 7.2.1.17 VIC Performance Monitoring Hardware • 7-16 7.2.2 The Prefetch Queue

7.2.2.1 PC load effects • 7-17 INSTRUCnON PARSING

7.3.1 VAX Instruction Format 7.3.2 The Instruction Burst Unit

7.3.2.1 7.3.2.2 7.3.2.3 7.3.2.4 7.3.2.5 7.3.2.6 7.3.2.7 7.3.2.8 7.3.2.9 7.3.2.10 7.3.2.11 7.3.2.12

Specifier Identification • 7-21 Operand Access Types • 7-23 DL stall • 7-24

Driving SPEC_CTRL • 7-24 PC and Delta_PC • 7-24

Branch Displacement Processing • 7-25 Ebox Assist Processing • 7-25

Reserved Addressing Modes • 7-26 Quadword Immediate Specifiers • 7-26 Index Mode Specifiers • 7-27

Loading a new opcode • 7-27 Reserved Opcodes • 7-28

6-1 6-1 6-1 6-3 6-4 6-5 6-8 7-1 7-1 7-1 7-2 7-4 7-5 7-5

7-17 7-17 7-19 7-19

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7.4

7.5

7.6

7.3.2.13 Instruction Parse Completion • 7-28

7.3.2.14 Operands with Access Type VR and VM • 7-28 7.3.2.15 I%IMEM_MEXC_H and I%IMEM_HERR_H • 7-28 7.3.2.16 IBU stop and restart conditions • 7-29

7.3.2.17 First Part Done (FPD) Set • 7-29 7.3.3 The Instruction Issue Unit

7.3.3.1 Issue Stall • 7-30

7.3.3.2 PC Queue and PC loads • 7-31 OPERAND SPECIFIER PROCESSING

7.4.1 Operand Queue Unit

7.4.1.1 Source Queue Interface • 7-34

7.4.1.1.1 Short Literal Specifiers (Modes 0 .. 3) • 7-36 7.4.1.1.2 RMODE Specifiers (Mode 5) • 7-36 7.4.1.1.3 Index Mode Specifiers (Mode 4) • 7-36 7.4.1.1.4 All Other Addressing Modes • 7-36 7.4.1.2 Destination Queue Interface • 7-37 7.4.1.2.1 RMODE Specifiers (Mode 5) • 7-38 7.4.1.2.2 Index Mode Specifiers (Mode 4) • 7-38 7.4.1.2.3 All Other Addressing Modes • 7-38 7.4.1.3 Queue Entry Allocation • 7-38 7.4.1.4 MD Allocation • 7-39

7.4.1.5 Specifier Bus Enable • 7-39

7.4.1.6 E%STOP _IBOX and Branch Mispredict • 7-39 7.4.2 Complex Specifier Unit

7.4.3

7.4.2.1 CSU Microcode Control • 7-40 7.4.2.2 CSU Pipeline • 7-41

7.4.2.2.1 S1 Pipeline Stage • 7-41 7.4.2.2.2 S2 Pipeline Stage • 7-45 7.4.2.2.3 S3 Pipeline Stage • 7-48 7.4.2.3 RlOG • 7-51

7.4.2.4 Branch Mispredict effects • 7-52 7.4.2.5 E%STOP _IBOX Effects • 7-52 7.4.2.6 RSVD~DDR_FAULT effects • 7-52 7.4.2.7 CSU Microcode Restrictions • 7-53 7.4.2.8 Ibox IPR Transactions • 7-53 7.4.2.8.1 IPR Reads • 7-53

7.4.2.8.2 IPR Writes • 7-54 Scoreboard Unit

7.4.3.1 E%STOP _IBOX and Branch Mispredict PC load Effects • 7-55

BRANCH PREDICTION

7.5.1 Branch Prediction Unit

7.5.1.1 The Branch Prediction Algorithm • 7-55 7.5.1.2 The Branch History Table • 7-56 7.5.1.3 Branch Prediction Sequence • 7-56 7.5.1.4 The Branch Queue • 7-57

7.5.1.5 Branch Mispredict • 7-58 7.5.1.6 Branch Stall • 7-58 7.5.1.7 PC loads • 7-58

7.5.1.8 Branch Prediction IPR Register • 7-59 PC LOAD EFFECTS

7.6.1 Mispredlct PC Loads

DIGITAL CONFIDENTIAL

Contents

7-30

7-32 7-32

7-40

7-54

7-55 7-55

7~1 7~2

Ix

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7.6.2 Ebox PC Loads 7-62

7.7 E%STOP _IBOX EFFECTS 7-63

7.8 INmALIZATlON 7-64

7.8.1 Mechanisms for lbox State Reset 7-64

7.9 ERRORS, EXCEPTIONS, AND FAULTS 7-64

7.9.1 Overview 7-64

7.9.2 Istream Memory Errors 7-64

7.9.3 Dstrum Memory Errors 7-65

7.9.4 Reserved Opcode Faults 7-65

7.9.5 Reserved Addressing Mode Faults 7-65

7.10 IBOX SIGNAL NAME CROSS-REFERENCE 7-67

7.11 TESTABILITY 7-68

7.11.1 Overview 7-69

7.11.2 Internal Scan Register and Data Reducer 7-69

7.11.3 Parallel Port 7-69

7.11.4 Architectural Features 7-70

7.12 PERFORMANCE MONITORING HARDWARE 7-70

7.12.1 Signals 7-70

CHAPTER 8 THE EBOX 8-1

8.1 CHAPTER OVERVIEW 8-1

8.2 INTRODUCTION 8-1

8.3 CHAPTER STRUCTURE 8-4

8.4 EBOX OVERVIEW 8-4

8.4.1 Mlcroword Fields 8-4

8.4.1.1 Microsequencer Control Fields • 8-6

8.4.2 The Register File 8-6

8.4.3 ALU and Shifter 8-6

8.4.3.1 Sources of ALU and Shifter Operands • 8-6 8.4.3.2 ALU Functions • 8-7

8.4.3.3 Shifter Functions • 8-7

8.4.3.4 Destinations of ALU and Shifter Results • 8-7

8.4.4 Ibox-Ebox Interface 8-7

8.4.5 Other Registers and States 8-9

8.4.6 Ebox Memory Access 8-9

8.4.7 CPU Control Functions 8-9

8.4.8 Ebox Pipeline 8-10

8.4.9 Pipeline Stalls 8-10

8.4.10 Mlcrotraps, Exceptions, and Interrupts 8-11

8.5 EBOX DETAILED FUNCTIONAL DESCRIPTION 8-13

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Contents

8.5.1 Register File 8-13

8.5.1.1 Register Groups • 8-13 8.5.1.2 Access Ports • 8-14

8.5.1.3 Register File Bypass Paths • 8-14 8.5.1.4 Write Collisions • 8-16

8.5.1.5 Valid, Fault, and Error Bits • 8-16

8.5.2 Constant Generation 8-17

8.5.3 The ALU 8-18

8.5.3.1 ALU Condition Codes • 8-19 8.5.32 SMUL Step Definition • 8-20 8.5.3.3 UDIV Step Definition • 8-20

8.5.4 The Shifter 8-21

8.5.4.1 Shifter Condition Codes • 8-22 8.5.4.2 Shifter Sign • 8-23

8.5.5 RMUX and E_BUS%WBUS_L 8-23

8.5.5.1 RMUX Produced Memory Request Signals • 8-24 8.5.5.2 RMUX Produced E_BUs%WBUS_L Related

Information • 8-24

8.5.6 VA Register 8-25

8.5.7 Q Register 8-25

8.5.8 Bypassing of Results 8-26

8.5.9 Result Destinations 8-27

8.5.10 Miscellaneous Ebox Registers and States 8-27

8.5.10.1 PSL • 8-27

8.5.10.1.1 Condition Code Alteration • 8-28 8.5.10.1.2 Trace and Trace Pending Bits • 8-29 8.5.10.2 SC • 8-29

8.5.10.3 INT.SYS • 8-30 8.5.10.4 MMGT.MODE • 8-30 8.5.10.5 State Flags • 8-30

8.5.10.5.1 E%MACHINE_CHECK_H • 8-31 8.5.10.5.2 State Rags and Pipeline Abort • 8-31

8.5.10.6 DL Part of the Instruction Context Register • 8-32 8.5.10.7 Mask Processing Unit • 8-32

8.5.11 Branch Condition Evaluator 8-34

8.5.12 Miscellaneous Ebox Operand Sources 8-35

8.5.12.1 S+PSW_EX • 8-36 8.5.12.2 Population Counter • 8-36 8.5.12.3 RN.MODE.OPCODE· 8-36 8.5.12.4 PMFCNT Register • 8-37

8.5.13 VAX Restart Bit 8-37

8.5.14 Ebox-Mlcrosequencer Interlace 8-38

8.5.14.1 Instruction Context Register • 8-38 8.5.14.2 Microtest Fields • 8-39

8.5.14.3 Miscellaneous Microsequencer Signals • 8-40 8.5.14.4 Miscellaneous Ebox-to-Microsequencer Signals • 8-41

8.5.15 Ebox-Ibox Interlace 8-42

8.5.15.1 Ibox Counters • 8-43 8.5.15.2 Source Queue • 8-43 8.5.15.3 Destination Queue • 8-44

8.5.15.4 Miscellaneous Queue Retire Information • 8-45 8.5.15.5 Branch Queue • 8-46

8.5.15.6 Operand and Branch Buses • 8-46

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xII

8.5.16

8.5.17

8.5.18 8.5.19

8.5.20

8.5.21 8.5.22

8.5.23 8.5.24 8.5.25

8.5.26

8.5.15.7 Retire Queue • 8-47 8.5.15.8 Field Queue • 8-48 8.5.15.9 Retiring Instructions • 8-49 8.5.15.10 First Part Done • 8-49

8.5.15.11 Ebox to Ibox Commands and IPR Accesses • 8-49 8.5.15.12 Loading The PC • ~50

8.5.15.13 Ebox to Ibox Rush Signals • ~O

8.5.15.14 Detecting lbox Incurred Faults and Errors • 8-51 Ebox-Fbox Interface

8.5.16.1 Fbox Opcode and Operand Delivery • ~2

8.5.16.2 Fbox Result Handling • 8-53 8.5.16.3 Fbox Store Stall • ~3

8.5.16.4 Fbox Destination Scoreboard. • 8-54 8.5.16.5 Fbox Fault and Error Management • ~6

8.5.16.6 Ebox to Fbox Commands • ~6

8.5.16.7 Summary of Fbox-Ebox Signals • ~7

8.5.16.8 Fbox Disabled Mode • 8-58 Ebox-Mbox Interface

8.5.17.1 10 Read Synchronization • 8-63 8.5.17.2 Mbox-Ebox signals • 8-84

8.5.17.3 Ibox IPR Access and LOAD PC • 8-66 Ebox Vector Support

Fault and Trap Management

8.5.19.1 Faults and Errors Detected in S4 • 8-68

8.5.19.1 .1 Coordinating Ebox and Fbox Faults and Errors • 8-68 8.5.19.1 .2 Breaking the S4 Stall • 8-09

8.5.19.2 Faults and Errors detected in S3 • 8-69

8.5.19.3 Integer Overflow and Branch Mispredict Traps • 8-69 8.5.19.4 Ebox Microtrap Handling • 8-70

8.5.19.5 Coincidence of Branch Mispredict Trap with other Traps • 8-70 8.5.19.6 Possible Microtrap Requests • ~71

8.5.19.7 Fbox Fault Reporting • ~71

Ebox Stalls

8.5.20.1 The STALL Microword • 8-74 8.5.20.2 Field Queue Stall • ~75

8.5.20.3 Ebox Stall Conditions • 8-75

8.5.20.4 Fbox and RMUX Related Stall Conditions • 8-76 Miscellaneous Operations

Ebox IPRs

8.5.22.1 IPR 7C (hex), Patchable Control Store Control Register • 8-80 8.5.22.2 IPR 70 (hex), Ebox Control Register • 8-81

Initialization Timing

Error Detection

8.5.25.1 S3 Stall limeout • 8-84

8.5.25.1 .1 Testing the S3 Stalllimeout Timer • 8-86 Testability

8.5.26.1 Parallel Port Test Features • 8-87 8.5.26.2 E%WBUS_H<31 :0> LFSR • 8-90

8-52

8-59

8-67 8-67

8-72

8-77 8-79

8-84 8-84 8-84

8-87

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Contents

8.5.27 Microcode Restrictions 8-91

8.5.27.1 Register Access Restriction • 8-91 8.5.27.2 FLUSH.PAQ Restriction • 8-91 8.5.27.3 Memory access restrictions • 8-91 8.5.27.4 Shifter Restrictions • 8-91

8.5.27.5 SHIFT.SIGN Restriction • 8-92 8.5.27.6 MMGT.MODE Restrictions • 8-92 8.5.27.7 MPU Restrictions • 8-92

8.5.27.8 Microbranch Condition Restrictions • 8-92 8.5.27.9 Ibox IPR read restriction • 8-92

8.5.27.10 RETIRE.lNSTRUCTION • 8-92 8.5.27.11 VAX Restart Bit Restriction • 8-92

8.5.27.12 Q Register Interaction With SMUL.STEP and UDIV.STEP • 8-92

8.5.27.13 UDIV/SMUL Restrictions • 8-93 8.5.27.14 F.DEST.CHECK Restrictions • 8-93 8.5.27.15 Fbox Operand Delivery Restriction • 8-93 8.5.27.16 RMUX control Restrictions • 8-93 8.5.27.17 Control Bits • 8-93

8.5.27.18 Microtrap Dispatch and RESET.CPU Restrictions • 8-93 8.5.27.18.1 Microtrap Flows • 8-93

8.5.27.18.2 MISC/RESET.CPU Restrictions • 8-94

8.5.27.18.3 Asynchronous Hardware Error Microtrap Restriction • 8-94 8.5.27.18.4 Rrst Part Done Dispatch Restriction • 8-94

8.5.27.19 PSL Use Restrictions • 8-94 8.5.27.20 S+PSW Restrictions • 8-96

8.5.27.21 RN.MODE.OPCODE Restrictions • 8-96

8.5.28 Signal Name Cross-Reference 8-97

8.5.29 Revision History 8-99

CHAPTER 9 THE MICROSEQUENCER 9-1

9.1 OVERVIEW 9-1

9.2 FUNCTIONAL DESCRIPTION 9-1

9.2.1 Introduction 9-1

9.2.2 Control Store 9-3

9.2.2.1 Patchable Control Store • 9-3

9.2.2.1.1 Loading the Patchable Control Store • 9-3 9.2.2.2 Microsequencer Control Field of Microcode • 9-8 9.2.2.2.1 Jump Format • 9-9

9.2.2.2.2 Branch Format • 9-10 9.2.2.3 M IB Latches • 9-1 0

9.2.3 Next Address Logic 9-11

9.2.3.1 CAL and CAL INPUT BUS • 9-11 9.2.3.1.1 Microtest Bus • 9-12

9.2.3.2 Microtrap Logic • 9-13 9.2.3.2.1 Microtraps • 9-13

9.2.3.2.2 Microtrap Request liming • 9-15 9.2.3.2.3 Prioritization of Microtraps • 9-15 9.2.3.2.4 Erroneous Microtrap Interruption • 9-16 9.2.3.2.5 Microtrap Detection Abort Effects • 9-17 9.2.3.3 Last Cycle Logic • 9-18

9.2.3.3.1 Interrupts • 9-19 9.2.3.3.2 Trace Fault • 9-1 9

DIGITAL CONFIDENTIAL xiii

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9.3 9.4 9.5

9.6 9.7

9.2.3.3.3 First Part Done • 9-19

9.2.3.3.3.1 Interaction with Reserved Instructions • 9-19 9.2.3.3.4 Instruction Queue • 9-20

9.2.3.3.4.1 Instruction Context Latches • 9-22 9.2.3.4 Microstack • 9-22

9.2.4 Stall Logic INITIALIZAnON

MICROCODE RESTRICTIONS TESTABIUTY

9.5.1 Test Address 9.5.2 MlB Scan Chain SIGNAL CROSS REFERENCE REVISION HISTORY

CHAPTER 10 THE INTERRUPT SECTION 10.1 OVERVIEW

10.2 INTERRUPT SUMMARY 10.2.1

10.2.2 10.2.3 10.2.4 10.2.5

External Interrupt Requests Received by Edge-SensHlve Logic External Interrupt Requests Received by Level-Sensltlve Logic Internal Interrupt Requests

Special Considerations for Interval Timer Interrupts Priority of Interrupt Requests

10.3 INTERRUPT SECTION STRUCTURE

10.3.1 Edge Detect and Synchronization Logic 10.3.1.1 Edge Detect Circuitry • 10-8 10.3.1.2 Interrupt Synchronization • 10-9 10.3.2 Interrupt State Register

10.3.3 Interrupt Generation Logic 10.4 EBOX MICROCODE INTERFACE 10.5 PROCESSOR REGISTER INTERFACE 10.6 INTERRUPT SECTION INTERFACES

10.6.1 Ebox Interface

10.6.1.1 Signals From Ebox • 10-14 H)"'6.1.2 Signals To Ebox • 1 0-14 10.6.2 M1crosequencer Interface

10.6.2.1 Signals from Microsequencer • 10-14 10.6.2.2 Signals To Microsequencer • 10-15 10.6.3 Cbox Interface

10.6.3.1 Signals From Cbox • 10-15 10.6.4 Ibox Interface

10.6.4.1 Signals From Ibox • 10-15 10.6.5 Mbox Interface

10.6.5.1 Signals From Mbox • 10-15 10.6.6 Pin Interface

10.6.6.1 Input Pins • 10-15 10.6.7 Signal Dictionary

9-24 9-24 9-25 9-25 9-25 9-26 9-30 9-33 10-1 10-1 10-1 10-2 10-2 10-4 10-5 10-6 10-8 10-8

10-9 10-10 10-12 10-13 10-14 10-14

10-14

10-15 10-15 10-15 10-15 10-15

xlv DIGITAL CONFIDENTIAL

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10.7 REVISION HISTORY CHAPTER 11 THE FBOX

11.1 11.2 11.3

11.4

11.5

11.6 11.7 11.8

OVERVIEW INTRODUCTION

FBOX FUNCTIONAL OVERVIEW 11.3.1

11.3.2 11.3.3 11.3.4 11.3.5 11.3.6

Fbox Interface Divider Stage 1 Stage 2 Stage 3 Stage 4 FBOX-EBOXINTERFACE

11.4.1 Opcode Transfers to the Fbox 11.4.2 Operand Transfers to the Fbox

11.4.3 SummarY of Fbox Input Stage Stall Rules 11.4.4 Fbox Result Transfers to the Ebox 11.4.5 Fbox Pipeline Stalls

11.4.6 Fbox Reset and Flush

11.4.7 Summary of Fbox-Ebox Signals 11.4.8 Fbox Instruction Set

DIVIDER

11.5.1 Introduction 11.5.2 Overview

INTERFACE SIGNAL TIMING DIAGRAMS DIVIDER OPERATION

DIVIDER IMPLEMENTATION

11.8.1 Divider Fraction Data Path

11 .8.1.1 Divisor Register - DVR • 11-20 11 .8.1 .2 Divider Array • 11-20

11.8.1.2.1 DCSA and DSEL • 11-20 11.8.1.2.2 LAT1· 11-21

11.8.1.2.3 R2D and DCSAF· 11-21 11 .8.1.2.4 DFB and SHF • 11-21 11.8.1.2.5 CPA· 11-22

11.8.1.3 Ouotient Recoding and Quotient Registers • 11-23 11.8.1.3.1 OS21 and OREC • 11-24

11 .8.1.3.2 OM and OS registers • 11-24 11.8.1.3.3 OSEL and TSF· 11-25 11.8.2 Divider Control

11 .8.2.1 Divider Control Blocks • 11-26 11 .8.2.1 .1 Control Sequencer • 11-26

11.8.2.1.2 Opcode Information Latches • 11-27 11 .8.2.1 .3 Divider Behavior during ABORT • 11-27 11 .8.2.1 .4 Data path Control Drivers • 11-27 11 .8.2.2 Summary of Divider Stage Outputs • 11-27 11 .8.2.3 Data Valid Logic • 11-28

Contents

10-17 11-1 11-1 11-1 11-2 11-3 11-4 11-4 11-4 11-4 11-4 11-4 11-5 11-6 11-7 11-8 11-10 11-11 11-11 11-12 11-15 11-15 11-16 11-17 11-17 11-19 11-19

11-25

xv

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11.8.3 Exponent and Sign Data Path 11-28

11.9 STAGE 1 11-28

11.10 SECnON IMPLEMENTATION DESCRIPTION 11-29

11.10.1 Fraction Datapath 11-29

11.10.2 Integer Overflow - IOVF 11-31

11.10.3 Input Selector - ISEL 11-31

11.10.4 Adder 11-31

11.10.5 Recoder Selector - RSEL 11-32

11.10.6 SRECODER 11-32

11.10.7 Multiplier 'TWo's Complement Register - MTCR<18:0> 11-32

11.10.8 Recoder 11-32

11.10.9 PHI_ 4 LATCHES 11-32

11.10.10 Recoder Register - MRECR[0:6]<5:0> 11-33

11.10.11 Multiplier Initial Partial Product Selector and Register - MlPPR 11-33 11.10.12 Multiplier Row 1 Selector and Register - MRW1 R 11-33 11.10.13 Multiplier Row 2 Selector and Register - MRW2R 11-33

11.10.14 Selector and Register - FD1 R 11-33

11.10.15 Selector and Register - FD2R 11-33

11.11 EXPONENT DATAPATH 11-35

11.11.1 Stage 1 Exponent Processor Block diagram 11-35

11.11.2 Exponent Adders 11-36

11.11.3 Constants 11-36

11.11.4 Zero Detection 11-37

11.11.5 Exponent Adder 1 11-37

11.11.7 Exponent Difference Detection 11-38

11.11.8 Output Selector 11-38

11.12 SIGN DATAPATH 11-39

11.13 STAGE 1 CONTROL 11-39

11.13.1 Divide Instruction 11-39

11.14 FRACTION DATAPATH OPERATION SUMMARY 11-40

11.15 FRACTION DATAPATH EXCEPTION SUMMARY 11-40

11.16 EXPONENT DATAPATH OPERATION SUMMARY 11-42

11.17 EXPONENT DATAPATH EXCEP110N SUMMARY 11-43

11.17.1 Passthru Signals 11-43

11.18 STAGE 2 11-44

11.18.2 MUL Instruction Flows 11-44

11.19 STAGE 2 IMPLEMENTATION DESCRIPTION 11-47

11.19.2 MSEL - Multiplier Selector 11-49

11.19.3 MROW1 - Multiplier Row 1 11-49

11.19.4 MROW2 - Multiplier Row 2 11-50

11.19.5 MARRAY - Multiplier Array 11-50

xvi DIGITAL CONFIDENTIAL

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Contents

11.19.6 MILSBSR<S:O> - Multiplier Integer LSB Sum Register 11-50 11.19.7 MILSBCR<4:0> - Multiplier Integer LSB Carry Register 11-51

11.19.8 RSHIFT - Right Shifter 11-51

11.19.9 RSHFTOR<AO:B58> - Right Shifter Output Register 11-51

11.19.10 SDEC - Shift Decoders 11-51

11.19.11 SDECOR<57:0> - Shift Decoder Output Register 11-51

11.19.12 DETL - Detection Logic 11-52

11.19.13 DETLOR<BO:B57> - Detection Logic Output Register 11-52

11.19.14 L 1 DETL - Leading 1 Detection Logic 11-52

11.19.15 LSSEL - Left Shift Selector 11-52

11.19.16 LSENC - Left Shift Encoder 11-53

11.19.17 LSHR<57:0> - Left Shifter Control Register 11-53

11.19.18 FD1 SEL - Fraction Data 1 Selector 11-53

11.19.19 FD1 R<AO:B58> - Stage 2 Fraction Data 1 Register 11-53 11.19.20 FD2R<AO:B58> - Stage 2 Fraction Data 2 Register 11-53

11.19.21 Exponent Datapath 11-54

11.19.22 Zero Detection 11-54

11.19.24 Floating Overflow and Underflow Detection 11-55

11.19.25 Output Selector 11-55

11.19.26 ED2R<5:0> - Exponent Data 2 Register 11-55

11.19.27 Sign Datapath 11-56

11.19.28 Control 11-57

11.19.28.1 Datapath Control Signals Output from Control Block • 11-58

11.19.29 Stage 2 Fraction Datapath Operation Summary 11-60

11.19.30 Passthru Signals 11-62

11.20 STAGE 3 11-63

11.20.2 Stage 4 Bypass 11-63

11.20.2.1 Stage 4 Bypass Request • 11-64 11.20.2.2 Stage 4 Bypass Abort • 11-64

11.20.2.3 Stage 3 Response to FBOX Purge • 11-64

11.20.3 Section Implementation Description 11-64

11.20.3.1 Block Diagrams • 11-65

11.20.4.1 Normalizer Input Selection • 11-69 11.20.4.2 Left Shifter • 11-69

11.20.4.3 Adder Input Selection • 11-70 11.20.4.4 Adder • 11-70

11.20.4.5 Mini-Round Incrementers • 11--72 11.20.4.6 Output Selector • 11-72

11.20.4.7 Fraction Datapath Operation Summary (Normal Operating Mode): • 11-73

11.20.5 Exponent Datapath 11-74

11.20.5.1 Constants • 11-74 -11.20.5.2 Zero Detection • 11-74 11.20.5.3 Exponent Adder 1 • 11-75 11.20.5.4 Output Selector • 11-75

11.20.5.5 Exponent Datapath Operation Summary (Normal Operating Mode): • 11-77

11.20.6 Sign Datapath 11-77

DIGITAL CONFIDENTIAL xvii

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11.20.7

11.21 STAGE 4

Control 11.20.7.1 11.20.7.2 11.20.7.3 11.20.7.4 11.20.7.5 11.20.7.6 11.20.7.7 11.20.7.8 11.20.7.9 11.20.7.10 11.20.7.11

11.22 FRACTION DATAPATH

Miscellaneous Control Signals • 11-78 Oata_ Valid • 11-78

Fault Bits and NEW_FOP • 11-78 Signs_NoCEql, Fb_Neg4 • 11-79 Integer Overflow Logic • 11-79 Cin_BSS • 11-80

SeL Other • 11-80

Left Shifter Input Selection Signals • 11-80 Osel1_Zero • 11-81

0se11_Ed1r • 11-81 MULL Adder • 11-81

11.22.1 Fraction Implementation Descrl ptlon 11.22.2 Fraction Operation

11.23 EXPONENT DATAPATH

11.23.1 Exponent Block Description 11.23.2 Exponent Operation

11.23.3 Floating Overflow and Underflow Detection 11.23.4 Output Selector

11.24 CONTROL

11.24.1 Control Block Description 11.24.2 Control Block Implementation 11.25 MISCELLANEOUS AND SIGN LOGIC

11.25.1 Miscellaneous Sign Logic Implementation 11.25.2 Sign and Negative Result Logic

11.25.3 Integer Overflow 11.25.4 Zero Result 11.25.5 Reserved Operand 11.25.6 Floating Divide by Zero 11.26 FBOX TESTABIUTY

11-77

11-$1 11-$2 11-$3 11-84 11-86 11-$7 11-$7 11-$7 11-$8 11-90 11-90 11-90 11-91 11-91 11-92 11-93 11-95 11-96 11-96 11-97

11.26.1 FBOX_ Test Control Signals 11-97

11.26.2 FBOX_ Test Mode Description 11-97

11.26.2.1 FBOX Section Operation During FBOX_ Test Mode • 11-97

11.26.3 Revision History 11-99

CHAPTER 12 THE MBOX 12-1

12-1 12-2 12-6 12-8 12-9

xvIII

12.1 INTRODUCTION 12.2 MBOX STRUCTURE

12.2.1 IREF _LATCH 12.2.2 SPEC_QUEUE 12.2.3 EM_LATCH 12.2.4

12.2.5 12.2.6 12.2.7

VAP_LATCH MME_LATCH RTY _OMISS_LATCH CBOX_LATCH

12-11 12-12 12-14 12-16

(19)

Contents

12.2.8 PA_QUEUE 12-17

12.2.9 TB 12-18

12.2.10 MME_DATAPATH 12-18

12.2.11 ARBITRATION LOGIC 12-18

12.2.12 S6_PIPELATCH 12-18

12.2.13 DMISS_LATCH and IMISS_LATCH 12-19

12.2.14 MD _BUS_ROTATOR 12-20

12.2.15 Pcache 12-21

12.3 REFERENCE PROCESSING 12-23

12.3.1 REFERENCE DEFINITIONS 12-23

12.3.2 SIMPLE MBOX PIPELINE FLOW 12-24

12.3.3 REFERENCE ORDER RESTRICTIONS 12-25

12.3.3.1 No D-stream hits under O-stream misses • 12-26 12.3.3.2 No I-stream hits under I-stream misses • 12-26 12.3.3.3 Maintain the order of writes • 12-27

12.3.3.4 Maintain the order of Cbox references • 12-27

12.3.3.5 Preserve the order of Ibox reads relative to any pending Ebox writes to the same quadword address • 12-27

12.3.3.6 110 Space Reads from the Ibox must only be executed when the Ebox is executing the corresponding instruction • 12-27 12.3.3.7 Reads to the same Pcache block as a pending read/fill

operation must be inhibited • 12~8

12.3.3.8 Writes to the same Pcache block as a pending readltill operation must be inhibited until the readlfill operation completes • 12-28

12.3.4 REFERENCE ARBITRATION 12-28

12.3.4.1 Arbitration Priority • 12~8

12.3.4.2 Arbitration Algorithm • 12-29

12.3.5 READS 12-30

12.3.5.1 Generic Read-hit and Read-miss/Cache_fili Sequences • 12-30

12.3.5.1.1 Returning Read Data • 12-31 12.3.5.1.1.1 Pcache Data Bypass • 12-31 12.3.5.2 I-stream Read Processing • 12-31 12.3.5.2.1 I-stream Read Hits • 12-31 12.3.5.2.2 I-stream Read Misses • 12-32 12.3.5.2.3 1/0 Space I-stream Reads • 12--32 12.3.5.3 D-stream Read Processing • 12--32 12.3.5.3.1 Reads under Rlls • 12--33 12.3.5.4 110 Space Reads • 12-33

12.3.6 WRITES 12-34

12.3.6.1 Destination Specifier Writes • 12-35 12.3.6.2 Explicit Writes • 12-36

12.3.6.3 Writes to 110 Space • 12--36 12.3.6.4 Byte Mask Generation • 12-36

12.3.7 IPR PROCESSING 12-37

12.3.7.1 MBOX IPRs • 12-37

12.3.7.2 Hardware MBOX IPR Format • 12-46 12.3.7.3 IPR Reads • 12-47

12.3.7.3.1 Mbox IPR Reads • 12-48 12.3.7.3.2 Non-Mbox IPR Reads • 12-48 12.3.7.4 IPR WRITES • 12-48

12.3.7.4.1 Mbox IPR Writes • 12-48

DIGITAL CONFIDENTIAL xix

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12.4

xx

12.3.8 12.3.9 12.3.10 12.3.11

12.3.12

12.3.13 12.3.14 12.3.15 12.3.16 12.3.17

12.3.18

12.3.19

12.3.20 12.3.21

12.3.7.4.2 Non-Mbox IPR Writes • 12-49 LOAD_PC

INVALIDATES

CACHE FILL COMMANDS MME CHECK COMMANDS 12.3.11.1 MME_CHK· 12-50 12.3.11.2 PROBE· 12-50 TB Fills

12.3.12.1 TB Tag Rlls • 12-51 12.3.12.2 TB PTE Rlls • 12-52 TBIS

TBIP TBIA

STOP_SPEC_Q

UNALIGNED REFERENCES

12.3.17.1 Unaligned Reads • 12-56 12.3.17.2 Unaligned Writes • 12-56

12.3.17.3 Byte Mask Generation for Unaligned Writes • 12-57 12.3.17.4 Unaligned Destination Specifier Writes • 12-58 12.3.17.5 Implication of Ebox unaligned references on

M%EM_LAT_FUU._H • 12-58 ABORTING REFERENCES

12.3.18.1 Conditions for Aborting References • 12-59

12.3.18.1.1 Aborting to Maintain Reference Order Restrictions • 12-59 12.3.18.1.2 Aborting due to lack of hardware resources • 12-62 12.3.18.1.3 Aborting due to memory management operation • 12-63 12.3.18.1.4 Aborting due to an external flush condition • 12-63 MBOX PIPELINE DEADLOCK AVOIDANCE SCENARIOS 12.3.19.1 Unaligned Reference Deadlock Condition • 12-04

12.3.19.2 READ_LOCKlWRITE_UNLOCK Deadlock Condition • 12-64 THESPEC_Q_SYNC_CTR

FLUSHING REFERENCES FROM THE MBOX PIPE 12.3.21.1 Ibox Rushes • 12-66

12.3.21.2 Ebox Rushes • 12-67

12.3.21 .2.1 Rushing due to E%EM_ABORT _L • 12-67 12.3.21 .2.2 Rushing due to E%FLUSH_MBOX_H • 12-67 12.3.21.2.3 Ebox Rushing of the PA_ QUEUE • 12-68 THE PCACHE

12.4.1 PCCTL

12.4.2 Pcache HltlMiss Determination

12.4.2.1 HitlMiss Determination by Tag Comparison • 12-72 12.4.2.2 Conditions which force Pcache Miss • 12-72 12.4.2.3 Conditions which force Pcache Hit • 12-73 12.4.3 Pcache Read Operation

12.4.4 Peaehe Write Operation

12.4.5 Pcache Replacement Algorithm 12.4.6 Pcache Fill Operation

12.4.7 Pcache Invalidate Operation 12.4.8 PcachelPRAecess

12.4.9 Peache IPR Summary

12.4.10 Pcache States Resulting In UNPREDICTABLE operation 12.4.11 Pcache Redundancy Logie

12-49 12-49 12-50 12-50

12-51

12-54 12-54 12-55 12-55 12-55

12-58

12-63

12-65 12-66

12-70 12-71 12-72

12-73 12-74 12-74 12-74 12-75 12-75 12-76 12-77 12-71