with Wire Bending with Wire Bending

Redundant Via Insertion Redundant Via Insertion

with Wire Bending with Wire Bending

Kuang

Kuang--Yao Lee, Yao Lee, ShingShing--Tung Lin and TingTung Lin and Ting--Chi WangChi Wang

Department of Computer Science Department of Computer Science

National

National TsingTsing HuaHua UniversityUniversity Hsinchu

Hsinchu, Taiwan, Taiwan

Outline Outline

Preliminaries Preliminaries

Problem definition Problem definition

Minimum

Minimum--weight maximum independent weight maximum independent set formulation

set formulation

00--1 integer linear program based approach1 integer linear program based approach Experimental results

Experimental results Conclusion

Conclusion

Redundant via Redundant via

Enable a single via failure to be tolerated Enable a single via failure to be tolerated

Improve the chip yield and reliability Improve the chip yield and reliability

NN

EE WW

Single Single

via

Redundant Via

Redundant

Double ViaVia

Feasible double via Feasible double via

Feasible Infeasible

v₁

d₁ d₂ v₁

v₂

d₃

d₁ d₂ v₂

Wire bending Wire bending

Create more feasible double

Create more feasible double viasvias Improve the insertion rate

Improve the insertion rate

Insertion rate = 50% Insertion rate = 100%

Wire bending (cont

Wire bending (cont ’ ’ d) d)

The wires are allowed to be bent The wires are allowed to be bent

A bending window of pre

A bending window of pre--defined size is givendefined size is given

p

p’ p’

p

p p

p’ p’

Bending window

Bending window

Legal

Illegal

Double via insertion with wire bending Double via insertion with wire bending

(DVI/WB) (DVI/WB)

Input Input

–– A routed design and a set of viaA routed design and a set of via--related design rulesrelated design rules

GoalGoal

1.1. To replace as many single To replace as many single viasvias with double with double viasvias as as possible

possible

2.2. Minimize the Minimize the wirelengthwirelength increase due to wire increase due to wire bending

bending

Constraints Constraints

–– Each single via either remains unchanged or is Each single via either remains unchanged or is replaced by a double via

replaced by a double via

–– After via replacement and wire bending, no design After via replacement and wire bending, no design rule is violated

rule is violated

Enhanced conflict graph Enhanced conflict graph

An undirected vertex

An undirected vertex--weighted graph weighted graph

constructed from a detailed routing solution constructed from a detailed routing solution

Vertex Vertex

–– a feasible double viaa feasible double via

EdgeEdge

–– cannot be inserted simultaneouslycannot be inserted simultaneously

d₃

d d₂

d₁ d₂

d₃

Enhanced conflict graph Enhanced conflict graph

Each vertex is associated with a weight Each vertex is associated with a weight

–– The amount of The amount of wirelengthwirelength increase caused by increase caused by inserting the corresponding double via

inserting the corresponding double via

p’

p

m₂

m₃ m₄

p p’

Bending window

Weight = m₁+m₂+m₃+m₄

m₁

Theorem Theorem

The DVI/WB problem can be formulated The DVI/WB problem can be formulated

as that of finding a minimum

as that of finding a minimum--weight weight maximum independent set (

maximum independent set (mWMISmWMIS) from ) from the enhanced conflict graph

the enhanced conflict graph

Graph construction Graph construction

2

1 3

N1

S1

E1

N2

S2

W2

W3

S3

E3

W3

[Lee et al., ICCAD’06]

– Sweep-line-like approach

– Cannot consider wire bending

Graph construction Graph construction

1

2

3

4 4

1 3

2 5

0 0

0 0

5 0

Graph construction Graph construction

6

6 K 1

2

3 0

0

0

5 0

KK

6 Bending window

Graph construction Graph construction

1

2

3

4 5

0 0

0 0

5

0 6

8

7 6 K

7 0

8 0

4 1

3

2

0 0 - - 1 ILP formulation 1 ILP formulation

∈

∑

∑

−

⋅

8 1

8 1

|) SV

| (

i

i i i

i

W R

R C

Maximize

1 1

8 7

6 5

4 3

2 1

≤ +

+ +

≤ +

+ +

R R

R R

R R

R R

1 1

6 4

5 2

≤ +

≤ +

R R

R R

Subject to

1

2

3

4 0

0

0 0

5

0

6 K

7 0

8 0

Double-cut constraint

Wi

> max

# of single vias Weight of vertex i

Conflict

External

Speed

Speed - - up up – – Pre Pre - - selection selection

Adapted from [Lee et al, ISPD

Adapted from [Lee et al, ISPD’’08]08]

–– No external edgeNo external edge

–– Having the minimum weight among the Having the minimum weight among the vertices coming from the same single via vertices coming from the same single via

1

2

3

4 5

0 W₂

0 W₄

5 W₅ 6

8

7

6 W₆ 7 W₇ 8 W₈ 4

1 3

2

Speed

Speed - - up up – –

Connected components Connected components

[Lee et al, ISPD

[Lee et al, ISPD’’08]08]

–– Divide into smaller 0Divide into smaller 0--1 ILP problems1 ILP problems

Overall approach Overall approach

1. Pre-selection 1. Pre

1. Pre--selectionselection

5

10 0

0

5 0

5 5

0 9

0

5

Overall approach Overall approach

1. Pre-selection 1. Pre

1. Pre--selectionselection

0

5 0

5 5

0 9

0

5

2.Connected Components 2.2.Connected Connected

Components Components

2020

Overall approach Overall approach

1. Pre-selection 1. Pre

1. Pre--selectionselection

0

5 0

5 5

0 9

0

5

2.Connected Components 2.2.Connected Connected

Components Components

3. Solve 0-1 ILP 3.3. Solve 0Solve 0--1 ILP1 ILP

Maximize ∑ ∑

≤

≤

≤

≤

−

⋅

5 1 5

1

2 10

i

i i i

i W R

R

Subject to

Λ

Maximize ∑ ∑

≤

≤

≤

≤

−

⋅

4 1 4

1

2 6

i

i i i

i W R

R

Subject to

Λ

Overall approach (cont

Overall approach (cont ’ ’ d) d)

5

10 0

0

5 0

5 5

0 9

0

5

Experiment

Experiment setup setup

Linux based machine with 2.4GHz processor Linux based machine with 2.4GHz processor

and 2GB memory and 2GB memory

Adopted

Adopted lp_solvelp_solve as our 0as our 0--1 ILP solver1 ILP solver

55 357386

357386 9999

44720 44720 C5C5

55 151912

151912 415415

17692 17692 C4C4

55 127059

127059 8585

18157 18157 C3C3

55 41157

41157 211211

52525252 C2C2

55 24594

24594 2020

43094309 C1C1

#M-#M-LayersLayers

#Vias#Vias

#I/Os

#I/Os

#Nets

#Nets Circuit

Circuit

Experimental results Experimental results – –

Effectiveness of wire bending Effectiveness of wire bending

T(s)T(s)

|E||E|

|V||V|

#A#A--viasvias T(sT(s))

|E||E|

|V||V|

#A-#A-viasvias

1.361.36 2.092.09

1.331.33 1.061.06

11 11

11 11

Normalized Normalized

731 1025320

804268 296323

442 444754

574142 276032

C5C5

184 371024

302904 119795

131 159691

220538 112076

C4C4

157 357643

284072 104356

120 179307

215647 99142

C3C3

41 114497

90541 33174

32 54376

67312 31464

C2C2

27 64083

53504 20664

22 36714

43246 19796

C1C1

with wire bending with wire bending w/o wire bending

w/o wire bending Circuit

Circuit

Experimental results Experimental results – –

# of inserted double

# of inserted double vias vias

T(s)T(s)

#WB#WB

#DVI#DVI T(s)T(s)

#DVI#DVI

1.181.18 --

1.061.06 11

11

Normalized Normalized

13.62 13.62 20256

20256 295383

295383 5.14

5.14 275437

275437 C5C5

5.19 5.19 77987798

119256 119256 3.87

3.87 111657

111657 C4C4

4.87 4.87 51465146

103934 103934 3.81

3.81 98888

98888 C3C3

3.54 3.54 17201720

33101 33101 3.30

3.30 31411

31411 C2C2

3.37 3.37 835835

20567 20567 3.23

3.23 19754

19754 C1C1

01ILP

01ILP––DVI/WBDVI/WB 01ILP

01ILP––DVI*DVI*

Circuit Circuit

*[Lee et al., ISPD’08]

Experimental results Experimental results – –

Wirelength

Wirelength increase increase

1.221.22

13.62 13.62 5.19 5.19 4.87 4.87 3.54 3.54 3.37 3.37 T(s)T(s)

11

9.02 9.02 4.41 4.41 4.42 4.42 3.43 3.43 3.30 3.30 T(s)T(s)

01ILP

01ILP––DVI/WBDVI/WB Rate(%) Rate(%) WL(WL(μμm)m)

Rate(%) Rate(%) WL(WL(μμm)m)

-- 0.280.28

-- 11

Normalized Normalized

0.100.10 2.57E+04

2.57E+04 0.360.36

9.27E+04 9.27E+04 C5C5

0.100.10 9.79E+03

9.79E+03 0.320.32

3.11E+04 3.11E+04 C4C4

0.100.10 6.30E+03

6.30E+03 0.390.39

2.47E+04 2.47E+04 C3C3

0.100.10 2.12E+03

2.12E+03 0.390.39

8.21E+03 8.21E+03 C2C2

0.100.10 9.96E+02

9.96E+02 0.320.32

3.22E+03 3.22E+03 C1C1

ECG + 01ILP

ECG + 01ILP––DVI*DVI*

Circuit Circuit

Conclusions Conclusions

We studied the DVI/WB problem and We studied the DVI/WB problem and

formulated it as a

formulated it as a mWMISmWMIS on the on the enhanced conflict graph

enhanced conflict graph

We proposed an efficient 0

We proposed an efficient 0--1 ILP based 1 ILP based approach to solve the

approach to solve the mWMISmWMIS problemproblem The experimental results were shown to The experimental results were shown to

support our approach support our approach

Wire bending Wire bending

p

p’ p’

p

p p

p’ o p’

Bending window

o

Bending window

Legal

Illegal