Principles of Operation

--- - - ---- _{- - - ---} ---

----

- - - ,-

Publication Number GA22-7000-10

IBM System/370

Principles of Operation

File Number S370-01

Eleventh Edition (September 1987)

This major revision obsoletes and replaces GA22-7000-8, GA22- 7000-9, and Technical Newsletters GN22-0644 and GN22-0683.

Significant changes or additions to the text and illustrations are indicated by a vertical line to the left of the change.

Changes are made occasionally to the using this publication in connection equipment, refer to the latest IBM Processors Bibliography, GC20-000I7 applicable and current.

information herein; before with the operation of IBM System/370, 30xx, and 4300 for the editions that are IBM may have patents or pending patent applications covering subject matter described herein. Furnishing this publication does not constitute or imply a grant of any license under any patents, patent applications, trademarks, copyrights, or other rights of IBM or of any third party, or any right to refer to IBM in any advertising or other promotional or marketing activities.

IBM assumes no responsibility for any infringement of patents or other rights that may result from the use of this publication or from the manufacture, use, lease, or sale of apparatus described herein.

licenses under IBM's utility patents are available on reasonable and nondiscriminatory terms and conditions. Inquiries relative to licensing should be directed, in writing, to: IBM Corpora- tion, Director of Contracts and licensing, Armonk, NY, USA 10504.

References in this publication to IBM products, programs, or services do not imply that IBM intends to make these available in all countries in which IBM operates.

Publications are not stocked at the address given below.

Requests for IBM publications should be made to your IBM repre- sentative or to the IBM branch office serving your locality.

A form for reader's comments is provided at the back of this publication. If the form has been removed, comments may be addressed to: IBM Corporation, Central Systems Architecture, Department E57, PO Box 390, Poughkeepsie, NY, USA 12602. IBM may use or distribute whatever information you supply in any way it believes appropriate without incurring any obligation to you.

ec) Copyright International Business Machines Corporation 1970,

This pUblication provides, for reference purposes, a detailed definition of the machine functions performed by System/370.

The publication applies only to systems operating in the System/370 mode. The IBM 370-XA Principles of Operation, SA22-7085, should be consulted regarding the functions of the architecture which apply to systems operating in the 370-XA mode, and the IBM 4300 Processors Prin- ciples of Operation for ECPS:VSE Mode, GA22-7070, should be consulted regarding the functions of the architecture which apply only to systems operating in the VSE mode.

The publication describes each function at the level of detail needed to prepare an assembler-language program that relies on that function. It does not, however, describe the notation and conventions that must be employed in preparing such a program, for which the user must instead refer to the appropri- ate assembler-language publication.

The information in this publication is provided principally for use by assembler-language programmers, although anyone concerned with the functional details of System/370 will find it useful.

This publication is written as a refer- ence and should not be considered an introduction or a textbook. It assumes the user has a basic knowledge of data- processing systems. IBM publications relating to System/370 are listed and described in the IBM System/370, 30xx, and 4300 Processors Bibliography, GC20-0001.

All facilities discussed in this publi- cation are not necessarily available on every model. Furthermore, in some instances the definitions have been structured to allow for some degree of extendibility, and therefore certain capabilities may be described or implied that are not offered on any model.

Examples of such capabilities are the number of channel-mask bits in the control register, the size of the CPU address, and the number of CPUs sharing main storage. The allowance for this type of extendibility should not be construed as implying any intention by IBM to provide such capabilities. For information about the characteristics and availability of facilities on a specific model, see the functional char- acteristics publication for that model.

~ Largely because this publication is

~ arranged for reference, certain words

; PREFACE

and phrases appear, of necessity, earli- er in the publication than the principal discussions explaining them. The reader who encounters a problem because of this arrangement should refer to the index, which indicates the location of the key description.

The information presented in this publi- cation is grouped in 13 chapters and several appendixes:

Chapter 1, Introduction, highlights some of the major facilities of System/370.

Chapter~, Organization, describes the major groupings within the system -- the central processing unit (CPU), storage, and input/output -- with some attention given to the composition and character- istics of those groupings.

Chapter

d,

Storage, explains the infor- mation formats, the addressing of stor- age, and the facilities for storage protection. It also deals with dynamic address translation (OAT), which, coupled with special programming support, makes the use of a virtual storage possible in System/370. Dynamic address translation eliminates the need to assign a program to a fixed lo~ation

in real storage and thus reduces the addressing constraints on system and problem programs.

Chapter ^~, Control, describes the facil- ities for the switching of system status, for special externally initiated operations, for debugging, and for timing. It deals specifically with CPU states, control modes, the program- status word (PSW), control registers, program-event recording, timing facili- ties, resets, store status, and initial program loading.

Chapter 2, Program Execution, explains the role of instructions in program execution, looks in detail at instruc- tion formats, and describes briefly the use of the program-status word (PSW), of branching, and of interruptions. It contains the principal description of the dual-address-space (DAS) facility.

It also details the aspects of program execution on one CPU as observed by other CPUs and by channels.

Chapter ^~, Interruptions, details the mechanism that permits the CPU to change its state as a result of conditions external to the system, within the system, or within the CPU itself. Six classes of interruptions are identified and described: machine-check interrup- tions, program interruptions, super- visor-call interruptions, external

iii

interruptions, input/output interrup- tions, and restart interruptions.

Chapter 7, General Instructions, contains detailed descriptions of logical and binary-integer data formats and of all unprivileged instructions except the decimal and floating-point instructions.

Chapter ^~, Decimal Instructions, describes in detail decimal data formats and the decimal instructions. The deci- mal instructions are a part of the commercial instruction set.

Chapter 1, Floating-Point Instructions, contains detailed descriptions of floating-point data formats and the instructions provided by the floating- point facility and by the extended- precision floating-point facility.

Chapter 1!, Control Instructions, contains detailed descriptions of all of the semiprivileged and privileged instructions except for the I/O instructions.

Chapter 11, describes the correcting, malfunctions.

Machine-Check Handling, mechanism for detecting, and reporting machine Chapter lZ, Operator Facilities, describes the basic manual functions and controls available for operating and controlling the system.

Chapter 11, Input/Output Operations, explains the programmed control of I/O devices by CPUs and by channels. It includes detailed descriptions of the I/O instructions, channel-command words, and other I/O-control formats.

The Appendixes include:

• Information about number represen- tation

• Instruction-use examples

• Lists of the instructions arranged in several sequences

• A summary of the condition-code settings

• A list of the System/370 facilities

• A table of the powers of 2

• Tabular information helpful in dealing with hexadecimal numbers

• An EBCDIC chart

• A discussion of changes compatibility between and System/370

affecting System/360

•

A discussion of changes affecting compatibility within System/370

SIZE NOTATION

In this publication, the letters K and M denote the multipliers 2¹⁰ and 220 ,

respectively. Although the letters are borrowed from the decimal system and stand for kilo (10³⁾ and mega (10^{6 ),} they do not have the decimal meaning but instead represent the power of 2 closest to the corresponding power of 10. Their meaning in this pUblication is as follows:

Symbol Value

K (kilo) 1,024

=

²¹⁰

M (mega) 1,048,576

=

²²⁰

The following are some examples of the use of K and M:

2,048 is expressed as 2K.

4,096 is expressed as 4K.

65,536 is expressed as 64K (not 65K).

224 is expressed as 16M.

When the words "thousand" and "million"

are used, no special power-of-2 meaning is assigned to them.

BYTES, CHARACTERS, AND CODES

Although the System/360 architecture was originally designed to support the Extended Binary-Coded-Decimal Inter- change Code (EBCDIC), the instructions and data formats of the architecture are for the most part independent of the external code which is to be processed by the machine. For most instructions, all 256 possible combinations of bit patterns for a particular byte can be processed, independent of the character which the bit pattern is intended to represent. For instructions which use the zoned format, and for those few instructions which are dependent on a particular external code, the instruc- tion TRANSLATE may be used to convert data from one code to another code.

Thus, a machine operating in the System/370 mode can process EBCDIC, ASCII, or any other code which can be represented in eight or fewer bits per character.

In this publication, unless otherwise specified, the value given for a byte is the value obtained by considering the

4

bits of the byte to represent a binary, code. Thus, when a byte is said to

contain a zero, the value 00000000 bina- ry, or 00 hex, is meant, and not the value for an EBCDIC character "0," which would be FO hex.

OTHER PUBLICATIONS

The channel-to-channel adapter is described in the pUblication IBM Channel-to-Channel Adapter, SA22-7091-.-- The I/O interface is

pUblication IBM described in System/360 the

and

System/370 I/O Interface Channel to Control Unit Original Equipment Manufac- turers' Information, GA22-6974.

Mathematical assists are described in the publication IBM System/370 Mathemat- ical Assists, SA22-7094, which describes the i nstructi ons ARCTANGENT, ^COM~10N LOGARITHM, COSINE, EXPONENTIAL, MULTIPLY AND ADD, NATURAL LOGARITHM, RAISE TO POWER, SINE, and SQUARE ROOT.

Vector operations are described in the publication IBM System/370 Vector Oper- ations, SA22-7125.

y

.This page is intentionally left blank.

CHAPTER 1. INTRODUCTION . • . . General-Purpose Design . • . . . Compatibility . . . . . . .

Compatibility among System/370

~'odels . . . • . . Compatibility between System/360

and System/370 . . System Program . • . . . . Availability . . . • . . CHAPTER 2. ORGANIZATION

Main Storage . . CPU . . . • . . . .

PSW . . . . • .

General Registers . . . . • . Floating-Point Registers

Control Registers Vector Facility

I/O . . . . . . .

Channel Sets . . . . Channels . . . . I/O Devices and Control Units Operator Facilities

CHAPTER 3. STORAGE

Storage Addressing . . . • • . Storage Addressing with

Extended Address Fields Information Formats

Integral Boundaries . . . Byte-Oriented-Operand Facility Address Types . • . •

Absolute Address Real Address Virtual Address

Primary Virtual Address Secondary Virtual Address

Logical Address . . • . Instruction Address . . . Effective Address

Storage Key . . . • Storage-Key 4K-Byte-Block

Facility . . . . Storage Keys with Storage-Key

4K-Byte-Block facility Not Installed . . . • • Storage Keys with Storage-Key

4K-Byte-Block Facility

Installed . . . • . • . . • Storage-Key-Exception Control Storage-Key-Instruction

Extensions . . . . Protection . . . .

Key-Controlled Protection

Segment Protection . . • • • • Low-Address Protection . . • • Reference Recording

Change Recording Prefixing • . . • Address Spaces

ASH Translation . . . . • . . • ASN-Translation Controls

ASN-Translation Tables ASN-first-Table Entries ASN-Second-Table Entries ASN-Translation Process

ASN-First-Table Lookup ASN-Second-Table Lookup

1-1 1-2 1-3 1-3 1-3 1-4 1-4 2-1 2-3 2-3 2-3 2-4 2-4 2-4 2-4 2-4 2-6 2-6 2-6 2-6 3-1 3-2 3-3 3-3 3-3 3-5 3-5 3-5 3-5 3-5 3-5 3-6 3-6 3-6 3-6 3-6 3-7 3-7 3-7 3-7 3-7 3-7 3-8 3-9 3-9 3-10 3-10 3-11 3-12 3-13 3-13 3-14 3-14 3-14 3-15 3-16 3-16

CONTENTS

Recognition of Exceptions during ASN Translation ASN Authorization . . •

ASH-Authorization Controls Control Register 4

ASH-Second-Table Entry Authority-Table Entries ASH-Authorization Process Authority-Table Lookup Recognition of Exceptions

during ASH Authorization Dynamic Address Translation

Translation Control Translation Modes Control Register 0 Control Register 1 Control Register 7

Translation Tables . . Segment-Table Entries Page-Table Entries Summary of

Dynamic-Address-Translation Formats . . . . Translation Process

Effective Segment-Table

Designation . . . . . • Inspection of Control Register o • • • • • • • • • • • • • Segment-Table Lookup • . . • Page-Table Lookup . . . . • Formation of the Real Address Recognition of Exceptions

during Translation • . • • Translation-Lookaside Buffer

Use of the

Translation-Lookaside Buffer Modification of Translation

Tables • . • . . Address Summary . . .

Addresses Translated Handling of Addresses Assigned Storage Locations CHAPTER 4. CONTROL . Stopped, Operating, Load, and

Check-Stop States Stopped State Operating State Load State

Check-Stop state Program-Status Word

EC and BC Modes • • • • • . . Program-Status-Word Format in EC

Mo de • • • • • • • • • Program-Status-Word Format in BC

Mode • . . •

Control Registers • • . • DAS Tracing • . • . . Protection for DAS Tracing Other Actions Associated with

DAS Tracing . . . . Serialization for DAS Tracing Trace-Table Designation

Trace-Table-Entry Header Interlocks • • • . • • . Trace Entry . • • • • • Program-Event Recording •

Control-Register Allocation

3-17 3-17 3-17 3-17 3-17 3-18 3-18 3-19 3-20 3-20 3-22 3-22 3-23 3-24 3-24 3-25 3-25 3-26 3-26 3-27 3-27 3-30 3-30 3-31 3-31 3-31 3-31 3-32 3-36 3-38 3-38 3-39 3-41 4-1 4-2 4-2 4-2 4-3 4-3 4-3 4-4 4-6 4-8 4-8 4-11 4-13 4-13 4-13 4-13 4-13 4-14 4-14 4-15 4-15 vil

Operation

· · · · ^{· ·} ·

^4-16 Execution of Interruptible

Identification of Cause 4-17 Instructions

· · ^{· · ·}

^5-9

Priority of Indication 4-17 Exceptions to Nullification and

storage-Area Designation 4-18 Suppression

· · · · · · · · ·

^5-11

PER Events

· · · · ·

^4-19 Storage Change and Restoration Successful Branching

· · ·

^4-19 for DAT-Associated Access

Instruction Fetching

· · · ·

^4-19 Exceptions

· · · · ^{· · ·} ·

^5-11

Storage Alteration

· · ·

^4-19 Modification of DAT-Table

General-Register Alteration 4-20 Entries

· ^{· ·} · · · · · · ·

^5-12

Indication of PER Events Trial Execution for Editing

Concurrently with Other Instructions and TRANSLATE 5-12 Interruption Conditions 4-20 Interlocked Update for

Direct Control

· · · · ·

^4-23 Nullification and Suppression 5-12 Read-Write-Direct Facility 4-23 Dual-Address-Space Control 5-13 External-Signal Facility 4-23 Summary

. _· · ^· · · · ^·

^5-13

Timing Time-of-Day Clock

. . _· · · ^{· ·} · · ^·

^4-23 4-23 DAS Functions Using Two Address Spaces

· · · · · ·

^5-14 5-14 Format

· · · · · ^· ·

^4-24 Changing to Other Spaces 5-14 states

· · · ^· ·

^4-24 Moving Information

· · ·

^5-15

Changes in Clock State

·

^{t-25 Transferring Program Control 5-15 Setting and Inspecting the Handling Storage Keys and the

Clock

· · · ^{· ·} · ^· ·

^{4-25 PSW Key}

· · · · · · · ^·

^5-16

TOD-Clock Synchronization 4-26 Program-Problem Analysis 5-17 Clock Comparator

· · · ^·

^4-27 DAS Authorization ^~lechan isms 5-17 CPU Timer Interval Timer

· · · · · · · · ^· · · · ·

^{4-28 4-29} Mode Requirements Extraction-Authority Control

· · ·

^5-17 5-17 Externally Initiated Functions _Resets

_.

4-30 PSW-Key Mask

· · · · · ·

^5-18

· · · ·

^4-30 Secondary-Space Control 5-18

CPU Reset 4-33 Subsystem-Linkage Control 5-18

Initial CPU Reset 4-34 ASN-Translation Control 5-18

Subsystem Reset 4-34 Authorization Index 5-18

Program Reset

· ·

^4-34 PC-Number Translation 5-21

Initial Program Reset 4-34 PC-Number Translation Control 5-21 Clear Reset

· · · ·

^4-34 PC-Number Translation Tables 5-21 Power-On Reset

· · · ·

^4-35 Linkage-Table Entries 5-21 Initial Program Loading 4-35 Entry-Table Entries

· · · ·

^5-22

Store Status

· · · ·

^4-37 PC-Number-Translation Process 5-22 Multiprocessing Shared Main Storage CPU-Address Identification

· · · · · · · · ^·

^{4-37 4-38} 4-38 Linkage-Table Lookup Entry-Table Lookup Recognition of Exceptions

· · · · · ^· · ·

^{5-23 5-24}

CPU Signaling and Response 4-38 during PC-Number Translation 5-24 Signal-Processor Orders

· ^{· ·}

^4-38 Sequence of Storage References 5-24 Conditions Determining Response 4-40 Conceptual Sequence 5-24

Conditions Precluding Overlapped Operation of

Interpretation of the Order Instruction Execution 5-24 Code

· · · · · ^{· · ·} ·

^4-40 Divisible Instruction

Status Bits 4-41 Execution

· · ^{· · ·} · · ^· ·

^5-25

Channel-Set Switching 4-43 Interlocks for Virtual-Storage

References

· · · ^·

^5-25

CHAPTER 5. PROGRAM EXECUTION 5-1 Instruction Fetching 5-26 Instructions

· · · ^{· · · · ·}

^5-2 DAT-Table Fetches 5-27 Operands

· · · · · · · · ^·

^5-2 Storage-Key Accesses 5-28

Instruction Format 5-3 Storage-Operand References 5-28

Register Operands

· · · ^{· ·}

^5-4 Storage-Operand Fetch

Immediate Operands 5-4 References

· · · · · · · ·

^5-29

Storage Operands

· · · ·

^5-4 Storage-Operand store

Address Generation Sequential Instruction-Address

· · · · · · ·

^5-5 Storage-Operand Update References

· · · ·

^5-29

Generation

· · · · · · ·

^5-5 References

· · ^{· ·} · ^·

^5-29

Operand-Address Generation 5-5 Storage-Operand Consistency 5-30 Branch-Address Generation 5-6 Single-Access References 5-30 Instruction Execution and Multiple-Access References 5-31 Sequencing

· · · · · · · ·

^5-6 Block-Concurrent References 5-31 Decision Making

· · · · ·

^5-6 Consistency Specification 5-31

Loop Control 5-6 Relation between Operand

Subroutine Linkage

· · ^· ·

^{5-6 Accesses}

· · · · · ^{· · ·}

^5-32

Interruptions

· · · · ·

^5-8 Other Storage References 5-33 Types of Instruction End; ng Completion Suppression 5-8 5-9 5-9 Serialization CPU Serialization Channel-Program Serialization

· · · · · · · ·

^{5-33 5-33} 5-34

Nullification

· · · ·

^5-9

Termination

· · ·

^{5-9 CHAPTER 6 .} INTERRUPTIONS 6-1

I

Interruptible Instructions 5-9 Interruption Action 6-2 \

Point of Interruption 5-9 Interruption Code 6-5

Enabling and Disabling

· ^· · ·

^{6-6 CHAPTER 7 •} GENERAL INSTRUCTIONS 7-1 Handling of Floating Interruption Conditions

· · · · · · · · ·

^6-7 Data Format Binary-Integer Representation

· · · ^{· ·} · ^{· ·}

^7-2 7-2 Instruction-Length Code _{Zero ILC} 6-7 Binary Arithmetic

· · · · ·

^7-3

· · · · · · · · ^· ·

^6-7 Signed Binary Arithmetic 7-3

ILC on Instruction-Fetching Addition and Subtraction 7-3 Exceptions

· · · · ·

^6-8 Fixed-Point Overflow

·

^7-3

Exceptions Associated with the Unsigned Binary Arithmetic 7-3 PSW

. . . · · · · · ^{· · ·} ·

^6-9 Signed and Logical Comparison ^7-4 Early Exception Recognition 6-9 Instructions

· · ·

^7-4

Late Exception Recognition ^6-9 ADD

· · · · ·

^7-7

External Interruption

· · · · ·

^6-10 ADD HALFWORD ^7-7 Clock Comparator

· · · ·

^6-11 ADD LOGICAL

· · · · · ·

^7-8

CPU Timer Emergency Signal 6-11 6-11 AND BRANCH AND LINK

· ^{· · ·} ·

^7-8 7-9

External Call

· · · ·

^6-11 BRANCH AND SAVE 7-9

External Signal

· · · · ·

^6-12 BRANCH ON CONDITION 7-10 Interrupt Key

· · · ^·

^6-12 BRANCH ON COUNT

· ·

^7-11

Interval Timer

· · · · ·

^6-12 BRANCH ON INDEX HIGH

· · ·

^7-11

~1al funct ion Alert 6-12 BRANCH ON INDEX LOW OR EQUAL 7-11 Service Signal

· · ^· · · ·

^{6-13 COMPARE}

· ^{· ·}

^7-12

TOD-Clock Sync Check 6-13 COMPARE AND SWAP 7-12

I/O Interruption

· ^{· ·}

^6-13 COMPARE DOUBLE AND SWAP 7-12 Machine-Check Interruption Program Interruption Exception-Extension Code

· · · · · · ·

6-14 ^{6-14 6-15} COMPARE LOGICAL CHARACTERS UNDER CO~'PARE ^CO~1PARE HALFWORD ^LOGICAL

· · · ^· · ·

^{7-14 7-14}

Program-Interruption Conditions Addressing Exception

· · ·

6-15 ^{6-15 CO~1PARE} MASK LOGICAL LONG

· · · · · · · · · · · ^·

^7-15 7-15 AFX-Translation Exception 6-18 CONVERT TO BINARY

· · · · · ^·

^7-16

ASN-Translation-Specification _Exception CONVERT TO DECIMAL

· · · · · ·

^7-17

· · · ·

^·

·

^{6-18 DIVIDE}

· · · ·

^7-17

ASX-Translation Exception 6-18 EXCLUSIVE OR

· · ·

^7-18

Data Exception

· · · · · · ·

^{6-18 EXECUTE}

· · ^{· · ·}

^7-19

Decimal-Divide Exception 6-19 INSERT CHARACTER

· · · · ^·

^7-20

Dec i ma l-Overf lot'" Exception 6-19 INSERT CHARACTERS UNDER MASK ^7-20 Execute Exception Exponent-Overflow Exception 6-19 6-19 LOAD LOAD ADDRESS

· · · · ·

^{7-20 7-21}

Exponent-Underflow Exception 6-19 LOAD AND TEST

· · · ^{· · ·} · ^·

^7-21

EX-Translation Exception

·

^6-20 LOAD Cor'1P L Ef'1ENT 7-21

Fixed-Point-Divide Exception 6-20 LOAD HALFWORD 7-22

Fixed-Point-Overflow Exception 6-20 LOAD ~1UL TIPLE

· · · · · · ·

^7-22

Floating-Point-Divide LOAD NEGATIVE ^7-22

Exception

· · · · · ·

^6-20 LOAD POSITIVE

· · · · · · · ·

^7-22

LX-Translation Exception 6-20 MONITOR CALL 7-23

t10n ito r Event Operation Exception Page-Translation Exception PC-Translation-Specification

· · · · ·

^{6-21 6-21} 6-22 ^MOVE MOVE INVERSE t'10VE LONG MOVE NUttER I CS

· · · · · · · · · · · · · · ^{· · ·} · · · · · · · ^{· ·} ·

^{7-23 7-24 7-24} 7-27

Exception

· ^{· ·}

^{6-22 ~1OVE} WITH OFFSET

· · · ·

^7-27

PER Event

· ^{· · · · ·}

^6-22 MOVE ZONES 7-28

Primary-Authority Exception 6-23 MULTIPLY

· · · · ·

^7-28

Privileged-Operation Exception 6-23 MULTIPLY HALFWORD 7-29 Protection Exception

· · · ·

^{6-23 OR}

. · · ^{· · ·} · ^·

^7-29

Secondary-Authority Exception Segment-Translation Exception 6-24 6-24 PACK SET PROGRAM MASK

· ^· · · · · · · · ·

^{7-30 7-31}

Significance Exception 6-25 SHIFT LEFT DOUBLE

· · · · · ·

^7-31

Space-Switch Event

· · · · ·

^6-25 SHIFT LEFT DOUBLE LOGICAL 7-32 Special-Operation Exception 6-25 SHIFT LEFT SINGLE ^7-32 Specification Exception 6-26 SHIFT LEFT SINGLE LOGICAL 7-33

Translation-Specification SHIFT RIGHT DOUBLE ^7-33

Exception

· · · · · · · · ·

^6-27 SHIFT RIGHT DOUBLE LOGICAL 7-33 Unnormalized-Operand Exception 6-27 SHIFT RIGHT SINGLE 7-34 Vector-Operation Exception 6-28 SHIFT RIGHT SINGLE LOGICAL 7-34 Collective Program-Interruption _Names

. . · · · ^{· · · ·} · · ·

^6-28 STORE STORE CHARACTER

· · · ·

^7-34 7-34 Recognition of Access Exceptions 6-28 STORE CHARACTERS UNDER MASK 7-35 f>1ult;ple Program-Interruption Conditions

· ^{· · ·} · ·

^6-30 STORE CLOCK STORE HALFWORD

· · · · ^{· · ·}

^7-35 7-36 Access Exceptions 6-33 STORE ~'Ul TIPlE

· · · · ·

^7-36

ASH-Translation Exceptions 6-35 SUBTRACT

· ·

^7-36

Trace Exceptions

· · · ·

^6-35 SUBTRACT HALFWORD

· · ·

^7-37

~ Restart Interruption 6-35 SUBTRACT LOGICAL 7-37

Supervisor-Call Interruption 6-36 SUPERVISOR CALL ^7-38

,

Priority of Interruptions 6-36

;x

TEST AND SET .. .. .. .. 7-38 READ DIRECT

. .

..

·

^..

.

^..

.

^10-36

TEST UNDER MASK

. _·

^..

.

^7-38 RESET REFERENCE BIT .. ^,

.

.. .. 10-36

TRANSLATE 7-39 RESET REFERENCE BIT EXTENDED 10-37

TRANSLATE AND TEST 7-40 SET ADDRESS SPACE CONTROL 10-38

UNPACK ..

.

.. ..

.

7-40 SET CLOCK SET CLOCK COMPARATOR .. .. .. ..

·

^.. .. .. .. .. ^10-39 10-39

CHAPTER 8 .. DECIMAL INSTRUCTIONS 8-1 SET CPU TIMER 10-40

Decimal-Number Formats Zoned Format .. .. .. .. .. .. .. ..

·

..

·

^{.. .. .. 8-1 8-1} SET PREFIX SET PSW KEY FROM ADDRESS .. .. .. ..

·

^{.. 10-40} 10-41

Packed Format 8-1 SET SECm-WARY ASN 10-41

Decimal Codes .. .. .. .. ..

· ·

^{.. 8-2} SET STORAGE KEY 10-45

Decimal Operations ..

.

.. .. .. .. .. 8-2 SET STORAGE KEY EXTENDED 10-45

Decimal-Arithmetic Instructions 8-2 SET SYSTEM MASK .. .. ..

.

10-46

Editing Instructions ..

·

^{.. 8-3} SIGNAL PROCESSOR 10-46

Execution of Decimal Instructions 8-3 STORE CLOCK CO~iPARATOR 10-47

Other Instructions for Decimal STORE CONTROL .. .. .. .. 10-48

Operands ..

.

^{.. ..}

.

^8-3 STORE CPU ADDRESS .. .. .. .. .. 10-48

Instructions .. .. .. .. 8-3 STORE CPU ID 10-48

ADD DECIMAL 8-5 STORE CPU T I~lER 10-49

COl"lPARE DECIMAL ..

.

.. .. 8-5 STORE PREFIX .. .. .. .. .. .. 10-49

DIVIDE DECIMAL 8-5 STORE THEN AND SYSTEM MASK 10-50

EDIT .. .. ..

.

.. 8-6 STORE THEN OR SYSTEi" MASK 10-50

EDIT AND MARK .. .. .. .. 8-9 TEST BLOCK .. .. 10-50

MULTIPLY DECIMAL .. .. 8-10 TEST PROTECTION .. .. .. 10-52

SHIFT AND ROUND DECIMAL 8-10 WRITE DIRECT 10-54

SUBTRACT DEC Ir'1A L 8-11

ZERO AND ADD .. .. .. .. .. .. .. .. 8-12 CHAPTER 11 .. MACHINE-CHECK

HANDLING .. .. .. .. .. .. .. .. .. .. .. 11-1

CHAPTER 9. FLOATING-POINT ~lach 1 ne-Check Detection .. .. .. .. 11-2

INSTRUCTIONS 9-1 Correction of Machine Malfunctions 11-2

Floating-Point Number Error Checking and Correction 11-2

Representation .. .. 9-1 CPU Retry .. .. .. .. 11-3

Normalization .. .. .. .. .. .. 9-2 Effects of CPU Retry 11-3

Floating-Point-Data Format 9-2 Checkpoint Synchronization 11-3

Instructions 9-4 Handling of Machine Checks

ADD NOR r·j A LIZ E D .. .. .. 9-6 during Checkpoint

ADD UNNOR~lA L IZED 9-7 Synchronization .. 11-3

cor-jp ^PI R E .. .. .. .. .. 9-8 Checkpoint-Synchronization

DIVIDE .. .. .. .. .. .. .. .. 9-9 Operations .. .. .. .. .. 11-4

HALVE 9-10 Checkpoint-Synchronization

LOAD .. .. .. .. 9-10 Action 11-4

LOAD AND TEST .. .. .. .. .. 9-11 Unit Deletion .. .. .. 11-4

LOAD COMPLEMENT 9-11 Handling of Machine Checks 11-5

LOAD NEGATIVE .. .. 9-11 Validation .. .. .. 11-5

LOAD POSITIVE 9-12 Invalid eBC 1 n Storage .. 11-6

LOAD ROUNDED ..

·

^{.. .. 9-12} Programmed Validation of

i'tuL TIPL Y 9-13 Storage .. .. .. .. .. .. 11-6

STORE .. .. .. .. .. .. 9-14 Invalid eBC in Storage Keys 11-7

SUBTRACT NORr1AlIZED 9-14 Invalid CBC in Registers 11-9

SUBTRACT UNNORMALIZED .. .. .. 9-15 Check-Stop State .. 11-10

System Check Stop .. 11-11

CHAPTER 10 .. CONTROL INSTRUCTIONS 10-1 Machine-Check Interruption 11-11

CONNECT CHANNEL SET 10-4 Exigent Conditions .. .. .. .. .. 11-11

DIAGNOSE .. .. .. .. .. .. .. .. .. 10-5 Repressible Conditions 11-12

DISCONNECT CHANNEL SET .. .. .. .. 10-6 Interruption Action 11-12

EXTRACT PRIMARY ASN .. .. .. .. .. 10-6 Point of Interruption .. .. .. 11-14

EXTRACT SECONDARY ASN .. .. 10-7 Machine-Check-Interruption Code 11-15

INSERT ADDRESS SPACE CONTROL 10-7 Subclass .. .. .. .. .. .. 11-16

INSERT PSl'J KEY .. .. .. .. .. .. 10-8 System Damage 11-16

INSERT STORAGE KEY .. .. .. ..

·

^{.. 10-8} Instruction-Processing Damage 11-17

INSERT STORAGE KEY EXTENDED 10-9 S~/stem Recovery 11-17

INSERT VIRTUAL STORAGE KEY 10-10 Interval-Timer Damage 11-17

INVALIDATE PAGE TABLE ENTRY 10-11 Timing-Facility Damage 11-17

LOAD ADDRESS SPACE PARAMETERS 10-12 External Damage 11-18

LOAD CONTROL 10-20 Vector-Facility Failure 11-18

LOl\D PSW .. .. .. .. 10-20 Degradation

.

.. ..

.

.. .. .. 11-18

LOAD REAL ADDRESS 10-21 Warning .. .. .. .. 11-18

r'1QV E TO PRH'iARY 10-22 Service-Processor Damage 11-18

MOVE TO SECONDARY 10-22 Subclass Modifiers 11-18

MOVE WITH KEY 10-24 Vector-Facility Source 11-19

PROGRAM CALL

.

.. 10-25 Backed Up .. .. .. .. .. 11-19

PROGRAM TRANSFER 10-31 Delayed ..

.

^.. .. 11-19

f PURGE TLB .. .. .. .. .. 10-36 Delayed Access Exception 11-19

\

Synchronous

Machine-Cheek-Interruption Conditions

Processing Backup • . • • Processing Damage • . . . Storage Errors • • . • •

Storage Error Uncorrected Storage Error Corrected • Storage-Key Error Uncorrected Storage Degradation

Indirect Storage Error

Machine-Check Interruption-Code Validity Bits . . . • . . • PSW-EMWP Validity . . PSW Mask and Key Validity PSW Program-Mask and

Condition-Code Validity PSW-Instruction-Address

Validity . . . • Failing-Storage-Address

Validity . . . • . . Region-Code Validity . . . External-Damage-Code Validity Floating-Point-Register

Validity . . . . General-Register Validity Control-Register Validity logout Validity . . . . • Storage Logical Validity CPU-Timer Validity . . . • Clock-Comparator Validity Machine-Check Extended-logout

length . • . . . . Machine-Check Extended

Interruption Information Register-Save Areas

External-Damage Code . . . . Failing-Storage Address

Region Code . . . Handling of Machine-Check

Conditions . . . . • Floating Interruption

Conditions • . . . Floating

Machine-Cheek-Interruption Conditions . . . •

Machine-Check Masking . . • • Check-Stop Control • • • • Recovery Subclass Mask

Degradation Subclass Mask External-Damage Subclass Mask Warning Subclass Mask

Machine-Check logout

Logout Controls . . . Synchronous Machine-Check

Extended-Logout Control • Input/Output Extended-Logout Control . . . . . • Asynchronous Machine-Check

Extended-Logout Control Asynchronous Fixed-Logout

Control . . . . . . . Machine-Check Extended-logout

Address . • . • . . . • Summary of Machine-Check Masking

and logout . . • • . . . . CHAPTER 12. OPERATOR FACILITIES Manual Operation . . . Basic Operator Facilities

Address-Compare Controls Alter-and-Display Controls Check-Stop Indicator

IML Controls . • • . . .

11-19 11-19 11-20 11-20 11-20 11-20 11-21 11-21 11-21 11-21 11-22 11-22 11-22 11-22 11-22 11-22 11-22 11-22 11-23 11-23 11-23 11-23 11-23 11-23 11-23 11-24 11-24 11-24 11-26 11-26 11-27 11-27 11-27 11-27 11-28 11-28 11-28 11-28 11-28 11-28 11-29 11-29 11-29 11-29 11-29 11-29 11-30 12-1 12-1 12-1 12-1 12-2 12-2 12-2

Interrupt Key

Interval-Timer Control load Indicator

load-Clear Key

load-Normal Key . • load-Unit-Address Controls Manual Indicator

Power Controls Rate Control Restart Key Start Key

Stop Key • • . Store-Status Key • • System-Reset-Clear Key System-Reset-Normal Key Test Indicator . • . • TOD-Clock Control

Wait Indicator • . • • • . Multiprocessing Configurations CHAPTER 13. INPUT/OUTPUT

OPERATIONS . • • . • • • • • • Attachment of Input/Output Devices

InputlOutput Devices

Control Units . . • . Channels • . • • . •

Modes of Operation Types of Channels

I/O-System Operation . • Compatibility of Operation Control of Input/Output Devices

Input/Output Device Addressing States of the Input/Output

12-2 12-3 12-3 12-3 12-3 12-3 12-3 12-3 12-4 12-4 12-4 12-4 12-5 12-5 12-5 12-5 12-5 12-6 12-6 13-1 13-2 13-2 13-3 13-3 13-4 13-4 13-5 13-7 13-8 13-8 System . • • . • • • . . • . 13-9 Resetting of the Input/Output

System . . . . . • . . I/O-System Reset . . • • • I/O Selective Reset

Effect of Reset on a Working

13-12 13-12 13-12 Device . . . 13-12 Reset Upon Malfunction 13-12

Condition Code 13-12

Instruction Formats 13-15 Instructions . . . . 13-15

CLEAR CHANNEL 13-16

CLEAR I/O 13-17

HALT DEVICE 13-19

HALT 1/0 • • • • 13-23 RESUME I/O . . . 13-26 START I/O . . . . . . . 13-27 START I/O FAST RELEASE 13-27

STORE CHANNEL ID 13-32

TEST CHANNEL . • . . • • 13-33 TEST I/O . . . • . • • • . 13-34 Input/Output-Instruction-Exception

Handling • . . . • . 13-36 Execution of Input/Output

Operations . • . . Blocking of Data . Channel-Address Word Channel-Command Word

Command Code • • • Designation of Storage Area Chaining • . • •

Data Chaining • . • • Command Chaining • • . • .

Skipping . . • • .

Program-Controlled Interruption Channel Indirect Data

Addressing . • • •

Addressing Using the 24-Bit

IDAW. . • . •

Addressing Using the 31-Bit I DAW • . • • • • • •

13-37 13-37 13-37 13-38 13-39 13-39 13-40 13-42 13-43 13-43 13-44 13-45 13-45 13-46

Suspension of Channel-Program Execution

Commands Write

Read . . • . • Read Backward Control

Sense

Sense ID • . • . Transfer in Channel Command Retry • Conclusion of Input/Output Operations . . . .

Types of Conclusion . Conclusion at Operation

Initiation . . . • • Immediate Operations . . • Conclusion of Data Transfer Termination by HALT I/O or

HALT DEVICE . . . • Termination by CLEAR I/O . Termination by CLEAR CHANNEL Termination Due to Equipment

Malfunction . . . Input/Output Interruptions

Interruption Conditions Channel-Available

Interruption . • • . Priority of Interruptions

Interruption Action Channel-Status Word Unit status

Attention

Status ~1odifier

Control-Unit End Busy

Channel End DQvice End

Unit Check . . Unit Exception Channel Status . .

Program-Controlled Interruption Incorrect Length Program Check Protection Check

Channel-Data Check . . . . Channel-Control Check

Interface-Control Check Chaining Check . . . . Contents of Channel-Status Word

Information Provided by Channel-Status Word Subchannel Key

Suspended Indication Logout Pending . Deferred Condition Code

CCL~ Address

Count . . • . . Status . . • . . Channel Logout

I/O-Communication Area

APPENDIX A. NUMBER REPRESENTATION AND INSTRUCTION-USE EXAMPLES Number Representation

Binary Integers . . . Signed Binary Integers Unsigned Binary Integers Decimal Integers

Floating-Point Numbers Conversion Example • Instruction-Use Examples

('<lachine Format

13-46 13-48 13-49 13-49 13-50 13-50 13-51 13-52 13-53 13-53 13-54 13-54 13-55 13-55 13-56 13-57 13-59 13-59 13-59 13-60 13-60 13-61 13-62 13-62 13-62 13-63 13-64 13-64 13-64 13-65 13-67 13-67 13-68 13-69 13-70 13-70 13-70 13-70 13-71 13-71 13-72 13-72 13-72 13-72 13-73 13-73 13-74 13-74 13-74 13-75 13-77 13-78 13-80 13-80 A-I A-2 A-2 A-2 A-4 A-5 A-5 A-7 A-7 A-7

Assembler-Language Format General Instructions • • • •

ADD HALFWORD (AH) • • • • AND (N, NC, NI, NR)

NI Example . •

Linkage Instructions (BAL, BALR, BAS, BASR)

Other BALR and BASR Examples BRANCH ON CONDITION (BC, BCR) BRANCH ON COUNT (BCT, BCTR) BRANCH ON INDEX HIGH (BXH)

BXH Example 1 BXH Example 2

BRANCH ON INDEX LOW OR EQUAL (BXlE)

BXlE Example 1 BXlE Example 2

COMPARE HAlFWORD (CH) . • COMPARE LOGICAL (Cl, CLC, ClI,

ClR)

CLC Example CLI Example

ClR Example .

COMPARE lOGICAL CHARACTERS UNDER MASK (ClM) . . . .

COMPARE LOGICAL lONG (CLCl) CONVERT TO BINARY (CVB) CONVERT TO DECIMAL (CVD)

DIVIDE (D, DR) • . . . EXCLUSIVE OR (X, XC, XI, XR)

XC Example XI Example EXECUTE (EX) •

INSERT CHARACTERS UNDER MASK ( I Cf"1 ) . . . • . . .

lOAD (l, lR) . . . . • . lOAD ADDRESS (lA) . . . . LOAD HAlFWORD (lH) . . • . . .

~1OVE (MVC, MVI) 1'1VC Exampl e ,.1VI Example . MOVE INVERSE (MVCIN)

MOVE LONG (MVCl) . • . . MOVE NUMERICS (MVN)

MOVE WITH OFFSET (MVO) MOVE ZONES (MVZ)

~1U L TIP L Y (M, MR)

MULTIPLY HAlFWORD (MH)

OR (0, OC, 01, OR) . . . . 01 Example . . .

PACK (PACK) . . . . • . SHIFT lEFT DOUBLE (SlDA) SHIFT LEFT SINGLE (SLA) STORE CHARACTERS UNDER MASK

(STCM) . . . STORE MULTIPLE (STM) TEST UNDER MASK (TM) TRANSLATE (TR) . . . . TRANSLATE AND TEST (TRT)

UNPACK (UNPK) . . • . • • Decimal Instructions . . • .

ADD DECIMAL (AP) . . . • . • . COMPARE DECIMAL (CP) . . . • • DIVIDE DECIMAL (DP)

EDIT (ED) . . . . • . EDIT AND MARK (EDMK)

MULTIPLY DECIMAL (MP) . . SHIFT AND ROUND DECIMAL (SRP)

Decimal Left Shift . . . • • Decimal Right Shift . . . . Decimal Right Shift and Round Multiplying by a Variable

Power of 10 . . . . • . ZERO AND ADD (ZAP) • . . .

A-7 A-8 A-8 A-8 A-8 A-I0 A-8 A-I0 A-I0 A-I!

A-II A-II A-12 A-12 A-12 A-12 A-13 A-13 A-13 A-14 A-14 A-14 A-16 A-16 A-16 A-17 A-17 A-I8 A-IB A-19 A-20 A-20 A-20 A-21 A-2I A-21 A-22 A-22 A-23 A-23 A-24 A-24 A-24 A-25 A-25 A-25 A-26 A-26 A-26 A-27 A-27 A-28 A-28 A-30 A-30 A-30 A-31 A-31 A-31 A-33 A-34 A-34 A-34 A-35 A-35 A-35 ~ A-36 ~

Floating-Point Instructions ADD NORMALIZED (AD, ADR, AE, ADD UNNORMALIZED (AU, AUR, AW, AER, AXR)

· · · · · · · · · ·

A-36 ^A-36 Floating Point Halt Device ^1/0 Limited Channel Logout Extended Logout

· · · ^{· · · · · · ·} · · · · · · · · ^{· ·} · ^·

^{0-4 0-4 0-4} 0-4

AWR)

. _· · · · · ^· · · ·

^A-36 Move Inverse

· · · · ^{· ·}

^0-4

COt-WARE (CD, CDR, CE, CER) A-37 Multiprocessing

· · · ·

^0-4

DIVIDE (DO, DDR, DE, DER) A-37 PSW-Key Handling 0-4

HALVE (HDR, HER)

· · · · · · ·

^A-38 Recovery Extensions 0-4 MULTIPLY (MD, MDR, ME, MER, MXD, Segment Protection 0-4 MXDR, MXR)

· · · · ^{· ·} · · ·

^A-38 Service Signal

· · · · · ·

^D-4

Floating-Point-Number Conversion Fixed Point to Floating Point A-38 A-39 Start-lID-Fast Queuing Storage-Key-Instruction

· · · ·

^D-4

Floating Point to Fixed Point A-39 Extensions

· · · · ^· ·

^0-5

Multiprogramming and Storage-Key 4K-Byte Block 0-5

Multiprocessing Examples Example of a Program Failure Conditional Swapping Using OR Immediate Instructions (CS, COS) Setting a Single Bit Updating Counters

· · · · · · · · · · · ^{· ·} ·

^{A-40 A-40} A-40 ^{A-41 A-41} APPENDIX E. Suspend and Resume Test Block Translation Vector 31-Bit IDAWs TABLE OF POWERS OF 2

· · · · · · · · · · · ^· · · · · · · ^· · · · · · ·

^{0-5 D-5 D-5 D-5 0-5} E-l

Bypassing POST and WAIT A-42

BYPASS POST Routine

· · · ·

^A-42 APPENDIX F. HEXADECIMAL TABLES F-l BYPASS WAIT Routine A-42

LOCK/UNLOCK

· · · · ·

^A-42 APPENDIX G. EBCDIC CHART G-l LOCK/UNLOCK with LIFO Queuing

for Contentions

· · ^· · · ·

^A-43 APPENDIX H. CHANGES AFFECTING LOCK/UNLOCK wi th FIFO Queuing COt'1PATIBILITY BETWEEN SYSTEM/360

for Contentions

· · · · ·

^A-44 AND SYSTEM/370

· · · ·

^H-l

Free-Pool Manipulation

· · · ·

^A-46 Removal of USASCII-8 Mode H-l Operation Codes of lID

APPENDIX B. LISTS OF INSTRUCTIONS B-1 Instructions H-l

Halt 1/0

· · · ·

^H-l

APPENDIX C. CONDITION-CODE Start 1/0 H-l

SETTINGS

· · · · · · · · · ·

^C-l _Logout Test Channel

_{. · ·} · · · · · ^·

^H-2

· · · · · ·

^H-2

APPENDIX D. FACILITIES

· · · ·

^D-1 Command Retry

· · ·

^B-2

Commercial Instruction Set D-l Channel Prefetching H-2

Other Facilities Channel Indirect Data Addressing Branch and Save

· · · · · · · · ·

^{D-1 D-2} D-2 APPENDIX I . Validity of Data CHANGES AFFECTING

· · · · ·

^H-2

Channel-Set Switching

· · · ^·

^D-2 COMPATIBILITY WITHIN S YS T Ef'1I3 70 I-I Clear 1/0

· · ^· · · · · · · ·

^D-2 READ DIRECT and WRITE DIRECT I-I Command Retry

· · · ·

^0-2 Store Accesses

· · · · ·

^1-1

Conditional Swapping

· · · ·

^0-2 Fetch Accesses

· · · ·

^I-I

CPU Timer and Clock Comparator D-2 Operand-Access Consistency 1-2 Direct Control

· · · · ^{· · · ·}

^0-2 Change Bit

· · · ^{· ·} · · · ·

^1-2

Dua l-AddJ~ess Space (DAS) 0-2 Subchannel Interruption-Pending

Extended

· · · ^{· ·} · · · · · ·

^{D-3 State}

. · · · · · · ^· · · · ·

^1-2

Extended-Precision Floating Point 0-3 START 1/0 and START 1/0 FAST

Extended Real Addressing External Signals

· · ·

D-3 ^0-3 RELEASE

· · · · · ^{· ·} · ^·

^1-2

Fast Release

· · ^· · ·

^{0-3 INDEX}

· · · ·

^X-I

CHAPTER ~ INTRODUCTION

General-Purpose Design •...•••••••••••••••••••••••••••••••• 1-2 Compa t i b iii ty .••.•••.••.•.••••••••.•••••.•••••••••••••.••• 1- 3 Compatibility among System/370 Models ..•..•••••••..••••. 1-3 Compatibility between System/360 and System/370 •.•.•...• 1-3 System Program ••..•..••..•.••••..•.•••••.•.••••••.••..•••• 1-4 Availability ••••••••.••..•.•••••••••••••.••.•••••••••••••• 1-4

This publication describes the IBM System/370 architecture.

The architecture of a system defines its attributes as seen by the programmer, that is, the conceptual structure and functional behavior of the machine, as distinct from the organization of the data flow, the logical design, the phys- ical design, and the performance of any particular implementation. Several dissimilar machine implementations may conform to a single architecture. When the execution of programs on different machine implementations produces the results that are defined by a single architecture, the implementations are considered to be compatible.

System/370 is a product of the experi- ence gained in developing and using several generations of compatible general-purpose systems, starting with System/360 as a base. System/370 incor- porates a number of significant facilities, which are described below.

• Dynamic address translation (OAT) is a facility that eliminates~e

need to assign a program to fixed locations in real storage and thus reduces the addressing constraints on both control programs and prob- lem programs, providing greater freedom in program design. Dynamic address translation permits a more efficient and effective utilization of main storage. When one of the operating systems for virtual stor- age is used, dynamic address translation allows the use of up to 16,777,216 bytes of virtual storage. Two page sizes (2K and 4K bytes) and two segment sizes (64K and 1M bytes) are provided, although some models offer only the 64K-byte-segment size and some models offer only the 4K-byte-page size. Extensions to this facility include the com~on-segment bit, the use of which increases the effec- tive size of the translation- lookaside buffer and thus improves CPU performance, and the instruc- tion INVALIDATE PAGE TABLE ENTRY, which improves CPU performance in a demand-paging environment.

•

•

•

•

Protection facilities include a storage key which is standard on all models. On some models this is extended by low-address protection, the use of which increases the protection of storage locations at effective addresses 0 through 511, which are vital to the control program. Segment protection, which is available on some models, provides a segment-protection bit in the segment-table entry. When the bit is one, an attempt to store in the segment causes a protection exception to be recognized.

Extended real addressing, which is an extension to dynamic address translation, provides the CPU with the capability of addressing up to 64M bytes of real storage. This is accomplished by the use of bits 13 and 14 of the page-table entry, which serve as the high-order bits of the page-frame real address when 4K-byte pages are specified. The larger address size applies to the real address provided by dynamic address translation and to the address provided by the LOAD REAL ADDRESS instruction.

Channel indirect data addressing, a companion facility to dynamic address translation, provides assistance in translating data addresses for I/O operations. It permits a single channel-command word to control the transmission of data that spans noncontiguous areas of main storage. In the basic form the indirect-data-address word contains a 24-bit address. This becomes a 31-bit address when the 31-bit-IDAW facility is installed.

Multiprocessing provides for the interconnection of CPUs to enhance system availability and share data and resources. It includes facili- ties for shared main storage, for programmed and special machine signaling between CPUs, and for the programmed reassignment of the first 4K bytes of real storage for each CPU.

Chapter 1. Introduction 1-1

•

•

•

•

•

•

Channel-set switching permits the collection of channels in a channel set to be connected to any CPU in a multiprocessing configuration.

Timing facilities include a TOO clock, a clock comparator, and a CPU timer, along with an interval timer that is also available in System/360. The TOO clock provides a measure of elapsed time suitable for the indication of date and time; it has a cycle of approxi- mately 143 years and a resolution such that the incrementing rate is comparable to the instruction- execution rate of the model. The clock comparator provides for an interruption when the TOD clock reaches a program-specified value.

The CPU timer is a high-resolution timer that initiates an inter- ruption upon being decremented past zero.

Extended-precision floating point includes addition, subtraction, and multiplication of floating-point numbers with a fraction of 28 hexa- decimal digits. Also included are instructions for rounding from extended to long and from long to short formats.

Program-event recording provides program interruptions on a selec- tive basis as an aid in program debugging.

The dual-address-space (DAS) facil-

~ provides for the support of semiprivileged programs, which are executed in the problem state but which, when allowed by authori- zation controls, are also permitted to use additional capabilities previously available only through the assistance of supervisor-state programs. The capabilities include (1) a PSW-key mask that controls the PSW keys which can be set by the program, (2) a second address space, called the secondary address space, together with an address- space-control bit in the PSW that permits the program to switch between the primary and secondary address spaces, and (3) a table- based linkage mechanism which permits a program with one authori- ty to call a program with greater authority.

Start-I/O-fast gueuing permits a subchannel to accept an SIOF func- tion even when certain I/O-busy conditions are encountered. If accepted, the SIOF function is held pending until the required facili- ties are available. An SIOF function is initiated when a START I/O FAST RELEASE instruction is executed and other necessary condi- tions exist. Start-I/O-fast

•

queuing may be provided for one or more subchannels of a channel.

The suspend-and-resume facility provides a means for programmed control of the progress of channel-program execution. A flag bit is provided in the channel- command word (CCW) which indicates that channel-program execution is to be suspended by the channel prior to executing the CCW. A new bit is added to the channel-status word which indicates that a channel program has been suspended. A control bit is provided in the channel-address word (CAW) which indicates that the suspend function is permitted for the channel program. An instruction, RESUME I/O, causes a suspended channel program to be resumed. The suspend-and-resume facility may be provided for one or more subchan- nels of a multiplexer channel.

GENERAL-PURPOSE DESIGN

System/370 is a general-purpose system that can readily be tailored for a varl- ety of applications. A commercial instruction set provides the basic proc- essing capabilities of the system. If the floating-point facility is installed with the commercial instruction set, a universal instruction set is obtained.

Adding other facilities, such as the extended-precision floating-point facil- ity or the conditional-swapping facility, extends the processing capa- bilities of the system still further.

System/370 has the capability of addressing a main storage of up to 64M bytes. The System/370 dynamic-address- translation facility, used with appro- priate programming support, can provide each user with an address space of 16M bytes independent of the amount of main storage. The dual-address-space facili- ty extends this by providing each user with multiple address spaces. This facility and this support permit a System/370 model with limited main stor- age to be used for a much wider set of applications, and they make many appli- cations with requirements for extensive storage practical and convenient.

Another major aspect of the general- purpose design of System/370 is the capability provided to attach a wide variety of I/O devices through a selec- tor channel and two types of multiplex- ing channels. System/370 has a byte- multiplexer channel for the attachment of unbuffered devices and of a large number of communications devices. Addi- tionally, it offers a block-multiplexer channel, which is particularly well-

suited for the attachment of buffered devices and high-speed cyclic devices.

An individual System/370 installation is obtained by selecting the system compo- nents best suited to the applications from a wide variety of alternatives in internal performance, functional ability, and input/output.

COMPATIBILITY

COMPATIBILITY AMONG SYSTEM/370 MODELS Although systems operating in the System/370 mode may differ in implemen- tation and physical capabilities, logically they are upward and downward compatible. Compatibility provides for simplicity in education, availability of system backup, and ease in system growth. Specifically, any program writ- ten for the System/370 mode gives identical results on any system operat- ing in that mode, provided that the program:

1. Is not time-dependent.

2. Does not depend on system facili- ties (such as storage capacity, I/O equipment, or optional facilities) being present when the facilities are not included in the configura- tion.

3. Does not depend on system facili- ties being absent when the facili- ties are included in the configuration. For example, the program must not depend on inter- ruptions caused by the use of operation codes or command codes that are not installed in some models. Also, it must not use or depend on fields associated with uninstalled facilities. For exam- ple, data should not be placed in an area used by another model for logout. Similarly, the program must not use or depend on unas- signed fields in machine formats (control registers, instruction formats, etc.) that are not explic- itly made available for program use.

4. Does not depend on results or func- tions that are defined to be unpre- dictable or model-dependent. This includes the requirement that the program should not depend on the assignment of I/O addresses and CPU addresses.

5. Does not depend on results or func- tions that are defined in the functional-characteristics publica-

tion for a particular model to be deviations from the architecture.

6. Takes into account those changes made to the original System/370 architectural definition that affect compatibility among System/370 models. These changes are described in Appendix I.

COMPATIBILITY BETWEEN SYSTEM/360 AND SYSTEM/370

System/370 is forward-compatible from System/360. A program written for the System/360 operates on the System/370, provided that the program:

1. Complies with the limitations described in the section "Compat- ibility among System/370 Models."

2. Does not use PSW bit 12 as an ASCII bit (a special case of the second rule in the section "Compatibility among System/370 Models").

3. Does not use or depend on storage locations assigned specifically for System/370, such as the interruption-code areas, the machine-check save areas, and the extended-logout area (a special case of the third rule in the section "Compatibility among System/370 Models").

4. Takes into account other changes made to the System/360 architec- tural definition that affect compatibility between System/360 and System/370. These changes are described in Appendix H.

Programming Note

This pUblication assigns meanings to various operation codes, to bit posi- tions in instructions, channel-command words, registers, and table entries, and to fixed locations in the low 512 bytes of storage. Unless specifically noted, the remaining operation codes, bit posi- tions, and low-storage locations are reserved for future assignment to new facilities and other extensions of the architecture. (In addition to fixed locations in the low 512 bytes, logical location 795 is assigned to a specific function.)

To ensure that existing programs operate if and when such new facilities are installed, programs should not depend on an indication of an exception as a result of invalid values that are currently defined as being checked. If a value must be placed in unassigned Chapter 1. Introduction 1-3