• Aucun résultat trouvé

Compiler-based Countermeasure Against Fault Attacks

N/A
N/A
Protected

Academic year: 2021

Partager "Compiler-based Countermeasure Against Fault Attacks"

Copied!
2
0
0

Texte intégral

(1)

HAL Id: emse-01232664

https://hal-emse.ccsd.cnrs.fr/emse-01232664

Submitted on 23 Nov 2015

HAL is a multi-disciplinary open access

archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.

L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Compiler-based Countermeasure Against Fault Attacks

Thierno Barry, Damien Couroussé, Bruno Robisson

To cite this version:

Thierno Barry, Damien Couroussé, Bruno Robisson. Compiler-based Countermeasure Against Fault Attacks. Workshop on Cryptographic Hardware and Embedded Systems, Sep 2015, Saint-Malo, France. �emse-01232664�

(2)

&

Compiler-based Countermeasure Against Fault Attacks

C

ONTEXT

The goal is to implement the instruction duplication technique as a countermeasure against Fault

Attacks on an ARM 32-bit Microcontroller[1,2]. Operating inside a compiler allowed us to reduce the

security overhead thanks to the flexibility and code transformations opportunities offered by compilers

Instruction

Selection

Clang

@__to_secure__(“fault”)

int

foo

(

int

a,

int

b){

. . .

return

a * b + a;

}

Generation of 3-address instructions:

add

r0, r1, r2

str

r5, [r3, #4]

add

r0, r1, r2

add

r0, r1, r2

str

r5, [r3, #4]

str

r5, [r3, #4]

str

r5, [r3, #4]

add

r0, r1, r2

str

r5, [r3, #4]

add

r0, r1, r2

Before scheduling

After scheduling

Duplication

Scheduling

Before duplication

W

ORKFLOW

The user identifies the portions of the program to protect

Source

Code

LLVM

bytecode

Binary

Code

Instructions cannot be duplicated at the middle-end due to the SSA form

entry:

%mul =

mul

%a,

%b

%add =

add

%mul,

%a

ret

%add

entry:

%mul =

mul

%a,

%b

%mul2 =

mul

%a,

%b

%add =

add

%mul,

%a

%add2 =

add

%mul,

%a

Unused and will be

removed by the Dead

Code Elimination pass

We only select instructions that are suitable for duplication

+

*

a

a

b

m

u

l

tiply and

a

ccumulate:

mla

a, a, b

is matched

we separately match: a

mul

followed by

add

By default

1

2

Instead of generating

add

vreg1, vreg2

We generate

add

vreg3, vreg1, vreg2

When the liveness intervals (L) of registers are disjoint:

{

L(

vreg3

)

}

{

L(

vreg1

) . L(

vreg2

)

}

= ∅

add

r0, r0, r1

add

r0, r1, r2

We introduce a constraint:

$𝑑𝑠𝑡 ≠ $𝑠𝑟𝑐

Registers are allocated in favor of duplication

The register allocator tends to reduce register pressure: Reusing the allocated registers as soon as possible

By default

Instead

Instructions are duplicated before scheduling

Attempted

duplication

LLVM bytecode

C source code

The user has a full control over parts of the code to protect

add

vreg3, vreg1, vreg2

Register

Allocation

Instruction

Scheduling

Code

Emission

Comparison with assembly approach

F

UTURE

WORK

&

R

EFERENCES

Using code annotation for more flexibility when defining the code

regions to protect

Automatic identification of the most vulnerable parts of the program

compiler-based implementation of the masking countermeasure

[1] Barenghi et al. Countermeasures against fault attacks on software implemented AES

[2] Moro et al. Electromagnetic Fault Injection : Towards a Fault Model on a 32-bit Microcontroller

F

UTURE

W

ORK

R

EFERENCES

L

EGEND

Duplicable

Not duplicable

Instruction

Transformation

Duplication

Assembly

approach

add

r0, r0, r2

mov

rx, r0

add

r0, rx, r2

mov

rx, r0

mov

rx, r0

add

r0, rx, r2

add

r0, rx, r2

Our

approach

add

r0, r1, r2

add

r0, r1, r2

add

r0, r1, r2

X 4

X 2

Mid

dle

-en

d

Fr

on

t-end

Back

-end

Thierno Barry* Damien Couroussé* Bruno Robisson**

*Univ. Grenoble Alpes, F-38000 Grenoble, France

CEA, LIST, Minatec Campus, F-38054 Grenoble, France

**CEA-Tech DPACA, Gardanne, France

[email protected]

sources

destination

llc

AES 8-bit NIST on ARM Cortex-M3

Unprotected Protected Overhead

Références

Documents relatifs

In order to show the effect of coupling between the heat transfer with phase change and the water steam flow in the ground, we simulate the heat diffusion in a water saturated soil

Both practical and theoretical, this thesis proposes to study the physical attacks also called side-channel attacks like Simple Power Anal- ysis, Dierential Power

Rather than relying on the C language to provide domain-specific features and enforce domain-specific properties, we propose an alternate approach to internal DSL development based

In this paper, we propose gadget weighted tagging (GWT), a flexible framework to detect and prevent CRAs. In GWT, we classify all possible gadgets into three major types on the basis

We showed that the columns parity check detects every single byte fault 6 propagation, even on AES-192 and AES-256 if the proposed correction (extra parity equations) is applied.. As

Unit´e de recherche INRIA Rennes, Irisa, Campus universitaire de Beaulieu, 35042 RENNES Cedex Unit´e de recherche INRIA Rhˆone-Alpes, 655, avenue de l’Europe, 38330 MONTBONNOT ST

The technique was used to solve the code equivalence problem for Reed-Muller codes [MS07], Polar codes [BCD + 16, Dra17], QC-LDPC codes [OTD08], a variant of the McEliece scheme

The lightweight validating compiler from Lustre to C consists of five main components: A mod- ular compiler from Lustre to C, a test suite generator for Lustre programs, a