MK4027(J/N)-4
o
Improved performance with "gated CAS", "RAS only" refresh and page mode capabilityo
All inputs are low capacitance and TTL compatibleo
Input latches for addresses, chip select and data ino
Three-state TTL compatible outputo
Output data latched and valid into next cycle o MKS version screened to Mll-STD-883System oriented features include direct interfacing capability with TTL, only 6 very low capacitance address lines to drive, on-chip address and data registers which eliminates the need for interface registers, input logic levels selected to optimize noise immunity, and two chip select methods to allow the user to determine the appropriate speed/power characteristics of his memory system. The MK 4027 also incorporates several flexible operating modes. In addition to the usual react and write cycles, read-modify write, page-mode, and ~-only refresh cycles are available with the MK 4027. Page-mode timing is very useful in systems requiring Direct Memory Access (DMA) operation.
IV-13 COLUMN ADDRESS STROBE CHIP SELECT
DATA IN DATA OUT
ROW ADDRESS STROBE READ/WRITE INPUT
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative.to VBB ... -0.5V to +20V
Voltage on VOO, VCC relative to VSS ... -1.0V to +15V *Stresses greater. than those listed under
"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional opera-tion of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VBB-VSS (VOO-VSS
>
0) ... OV Operating temperature, T A (Ambient) ... O°C to + 70°C Storage temperature (Ambient)(Ceramic) ... -65°C to + 150°C Storage temperature (Ambient)(Plastic) ... -55°C to + 125°C Short Circuit Output Current ... 50mA Power dissipation . . . .. 1 Watt RECOMMENDED DC OPERATING CONDITIONS 4(Ooc .;; T A .;; 70°C) 1 DC ELECTRICAL CHARACTERISTICS 4
TYP MAX UNITS NOTES
1001 Average VOO Power Supply Current 1002 Standby VOO Power Supply Current 1003 Average VOO Power Supply Current
during "AAS only" cycles ICC VCC Power Supply Current IBB Average VBB Power Supply Current II(l) Input leakage Current (any input) ,IO(l) Output leakage Current
VOH Output logic 1 Voltage @ lOUT =
3. Output voltage will swing from VSS to Vec when enabled,with no output load. For purposes of maintaining data in standby mode,
~a1~ r~t~~:~~d~~~e!~r:~Se ~i~h~(:n~~f)e~~~nC~f~~:~~~~ f~~~~tions or
guaranteed in this mode.
4. Several cycles are required after power-up before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose.
5. Current is proportional to cycle rate.IOOl (max) is measured at the cycle rate specified by tAC (min). See figure 1 for 1001 limits at other cycle rates.
6. ICC depends on output loading. During readout of high level data Vec is connected through a low impedance (135S! typ) to Data Out. At all other times Ice consists of leakage currents only.
TYP MAX UNITS NOTES at a logic 1. Transient ttabTlization is required prior to measure-ment of th is parameter.
10. Effective capacitance is calculated from the equation;
c = 00 with 1'1 V = 3 volts.
I'1v
11. A.C. measurements assume tT = 5ns.
12. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature range (0° ~ TA ~ 70°C) is assured.
IV-14
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(4,11, 17) (00 C.;;; TA';;; 70° C)1 (VDD
=
12.0V± 10%, VCC=
5.0V ± 10%, VSS=
OV, -5.7V';;; VBB ';;;-4.5V)PARAMETER
tRC Random read or write cycle time tRWC Read write cycle time tRMW Read modify write cycle time tpc Page mode cycle time
tRAC Access time from row address strobe tCAC Access time from column address strobe tOFF Output buffer turn-off delay
tRP Row address strobe precharge time tRAS Row address strobe pulse width tRSH Row address strobe hold time tCAS Column address strobe pulse width tCSH Column address strobe hold time tRCD Row to column strobe delay tASR Row address set-up time tRAH Row address hold time tASC Column address set-up time tCAH Column address hold time
tAR Column address hold time referenced to RAS tcsc Chip select set-up time
tCH Chip select hold time
tCHR Chip select hold time referenced to RAS
IT
Transition time (rise and fall) tRCS Read command set-up time tRCH Read command hold time tWCH Write command hold timetWCR Write command hold time referenced to RAS twp Write command pulse width
tRWL Write command to row strobe lead time tCWL Write command to column strobe lead time tDS Data in set-up time
tDH Data in hold time
tDHR Data in hold time referenced to RAS tCRP Column to row strobe precharge time tcp Column precharge time
tRFSH Refresh period
twcs Write command set-up time tCWD CAS to WRITE delay time is controlled exclusively by tCAC'
MK4027-4 measuring timing of input signals. Also, transition times are measured between VIHC or VIH and
VIL-18. These parameters are referenced to CAS leading edge in random write cycles and to W"R'i"T'E leading edge in delayed write or read-modify-write cycles.
19. twcs, tCYVD, and tRWD are restrictive operating parameters in . a read/write or read/modify/write cycle only. If twcs ~twcs (mm), the cycle is an early write cycle and Data Out wilr cOntain the data written into the selected cell. If tCWD ~tCWD (min) and tRWD ~ tRWD (min), the cycle is a read-write cycle and Data Out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of Data Out (at access time) is indeterminate.
IV-15
---~ .~-~-.--->~----. "~~
...
~..
II
AC ELECTRICAL CHARACTERISTICS
(DoC ,;;;;TA';;;; 70t) (VDD = 12.0V ± 10%; VSS = OV;-5.7V';;;;VBB,;;;;-4.5V)
PARAMETER TYP
C 11 Input Capacitance (AO·A5), DIN, CS 4 C 12 Input Capacitance RAS, CAS, WR ITE 8
Co Output Capacitance (DOUT) 5
MAXIMUM 1001
vs.
CYCLE RATE FOR DEVICE OPERATION AT EXTENDED FREQUENCIESFigure 1
50mA
«
40mAE.
f-w Z
a: a:
30mA U ::l
>-..J a.
a.
::l en C; 20rnA
E
r--
-I -
-/
lOrnA
o o
1000
CYCLE TIME tCYC (ns) 380 500 400
v~~ ~~
fvv~
:P
~~'?"
»"
-$> ,~
~~
~ -<.-{~~*'l
i./
i.-~
"""
1.0 2.0
MAX 5 10 7
300
3.0 CYCLE RATE (MHz) = 103 /tCYC (ns)
UNITS pF pF pF
250
4.0
SUPPLEMENT -To be used in conjunction with MK4027(J/N)-1/2/3 data sheet.
IV-16
NOTES 10
10 8,10
FEATURES
o
Recognized industry standard 16-pin config-uration from MOSTEKo
150ns access time, 320ns cycle (M K 4116-2) 200ns access time, 375ns cycle (MK 4116-3)o
± 10% tolerance on all power supplies (+12V, ±5V)o
Low power: 462mW active, 20mW standby (max)o
Output data controlled byCAS
and unlatched at end of cycle to allow two dimensional chip selec-tion and extended page boundaryo
Common I/O capability using "early write"operation advanced circuit techniques designed to provide wide operating margins, both internally and to the system user, while achieving performance levels in speed and power previously seen only in MOSTEK's high performance MK 4027 (4K RAM).
The technology used to fabricate the M K 4116 is MOSTEK's double-poly, N-channel silicon gate, POL Y II
e
process. This process, coupled with the use of a single transistor dynamic storage cell, pro-vides the maximum possible circuit density and reliability, while maintaining high performance FUNCTIONAL DIAGRAMAvailable per MIL-STO-883 B. Mostek is qualified per