PAGE MODE WRITE CYCLE

32,768x1-BIT DYNAMIC RAM

1 4 - - - -

I RAS - - - e j

ADDRESSES

IV-57

-DESCRIPTION (continued)

System oriented features include ± 10% tolerance on all power supplies, direct interfacing capability with high performance logic f?mi!ies su~h as Sc:h(:>tt.ky several flexible timing/operating modes. In addition to the usual read, write, and read-modify-write cycles, the MK 4332 is capable ...QLdelayed write cycles, page-mode operation and RAS-only-DUresh.

Pr~p.fr control of the clock inputs(RAS, CAS and W I E) allows common I/O capability, two dimen-sional chip selection, and extended page boundaries (when operating in page mode).

ADDRESSING latches by externally applying two negative going TTL-level clocks. The first clock, the Row Address con-trolled by different delayed internal .clocks. The two clock chains are linked together logically in such a way that the address multiplexing operation is done outside of the critical path timing seq~e for read data access. The later events in the CAS clock se-quence are inhibited until the occurence of a delayed sigSI derived from the RAS clock chain. This "gated CA " feature allows the CAS clock to be externally activated as soon as the Row Address Hold Time specification (tRAH) has been satisfied and the ad-dress inputs have been changed from Row adad-dress to Column address information.

Note that

CAS

can be activated at any time after made its negative -transition. In this "delayed write cycle" the data input set-up and hold times are throughout the portion of the memory cycle in which

CAS

is active (low). Data read from the selected cell will be available at the output within the specified access time.

DATA OUTPUT CONTROL

The normal condition of the Data Output (DOUT) of theMK 4332 is the high impedance (open-circuit) state. That is to say, anytime CAS is at a hiQh level,

ships' of the two devices. Both deVices cannot be acti-vated at the same time as a data output conflict can occur.

If the memory cycle in progress is a read, read-modify write or a delayed write cycle, then the data out~ut placement of WRlTE command during a write cycle, and the pulse width of the Column Address Strobe during read operations. Note also that even thouQh data is not latched at the output, data can remain valid from access time until the beginning of a sub-sequent cycle without paying any penalty in overall memory cycle time (stretching the cycle).

This type of output operation results in some very significant system implications.

Common I/O Operation - If all write operations are

with QQYenalty in cycle time. This also makes the RAS/CAS clock timing relationship very flexible.

Two Methods of Chip Selectioll - Since 00UT

Extended Page Boundary - Page-mode operation allows for successive memory cycles at multiple column locations of the same row address. By de-coding

CAS

as a page cycle select signal, the page boundary can be extended beyond the 128 colu mn locations in a single chip. (See page-mode operation).

OUTPUT INTERFACE CHARACTERISTICS The three state data output buffer presents the data successive memory operations at mUltiple column locations of the same row address with increased speed without an increase in power. This is done by strobing the row address into the chip and maintain-ing the RAS signal at a logic 0 throughout all success-ive memory cycles in which the row address is com-mon. This "page-mode" of operation will not dissi-pate the~er associated with the negative going as a page cycle select signal. Only those devices which receive both RAS and CAS signals will execute a read order to completely refresh all 32,768 memory cells.

Although any normal memory cycle will perform the refresh operation, this function is most easily accomplished with "RAS-only" cycles. RAS-only re-fresh resu Is in a substantial reduction in operating address strobe edge. Consequently, the dynamic power is primarily a function of operating frequency rather than active duty cycle (refer to the MK 4116

Although no particular power supply noise r~stri~ti<?n exists other than the supply voltages remain within the specified tolerance limits, adequate decoupling should be provided to suppress high frequency noise resu Iting from the transient cu rrent of the device. This insures optimum system performance and reliability. Bulk capacitance reql,Jirements are minimal since the MK 4332 draws very little steady state (DC) current.

In system applications requiring lower power dissi-pation ,the operating frequency (cycle rate) of the operating frequency, for example 1 microsecond cycle, results in a reduced maximum 1001 require-ment of under 20mA with an ambient temperature range from 0° to 70° C.

NOTE: Additional power supply tolerance has been included on the VSB supply to allow direct interface capability with both -5V systems -5.2V ECl svstems.

Fig. 5 Typical Current Waveforms for the MK 4116

11.-50 NANOSECONDS I DIVISION

RAS ONLY CYCLE

Although

RAS

and/or

CAS

can be decoded and used as a chip select sifJnal for the MK 4116,overall system power is minimized if the Row Address Strobe (RAS) is used for this purpose. All unselected de-vices (those which do not receive a RAS) will remain in a 1011lL.1!.0wer (standby) mode regardless of the state of CAS.

POWER UP

The MK 4332 requires no particular power supply sequencing so long as the Absolute Maximum Rating Conditions are observed. However, in order to insurE compliance with the Absolute Maximum Ratings, MOSTEK recommends sequencing of power supplies

such that VBB is applied first and removed last.

VBB should never be more positive than VSS when power is applied to VDD.

Under system failure conditions in which one or more supplies exceed the specified limits significant addi-tional margin a!tainst ca1i!llrophicJ!eyice failure may

be achievea by -forcing RAS and CAS to the inactive state (high level).

After power is applied to the device, the MK 4332 requires several cycles before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose. Each MK 4116 device must receive the 8 initialization cycles.

IV-60

TYPICAL CHARACTERISTICS OF THE MK 4116

TYPICAL ACCESS TIME (NORMALIZED) VI. VOO

TJ = 50"C

--...

t-- --...

r--10 11 12 13 14

VOO SUPPLY VOLTAGE (VOLTS)

TYPICAL ACCESS TIME (NORMALIZED) vs. Vaa

~ TJ""50"C Vaa SUPPLY VOLTAGE (VOLTS)

TYPICAL ACCESS TIME (NORMALIZED) vs VCC

1.2

TYPICAL ACCESS TIME (NORMALIZED) liS JUNCTION TEMPERATURE

/

Voo SUPPLY VOLTAGE (VOLTS)

TYPICAL 1002 vs VOO

VOO SUPPLY VOLTAGE (VOLTS)

TYPICAL 1003 VS. VOD

Veo SUPPLY VOLTAGE (VOLTS)

TYPICAL 1004 vs VOO

-VOD SUPPLY VOL rAGE (VOLTS)

IV-61

TYPICAL 1001 vs JUNCTION TEMPERATURE 35

TJ. JUNCTION TEMPERATURE ("C)

TYPICAL 1002 vsJUNCTION TEMPERATURE 1. 4

TJ. JUNCTION TEMPERATURE ("c)

TYPICAL 1003 liS JUNCTION TEMPERATURE

o ~oo ^=13.2V

TJ,JUNCTION TEMPERATURE (OC)

TYPICAL 1004 Vi. JUNCTION TEMPERATURE 20

TJ.JUNCTION TEMPERATIjRE IOC)

II

3.0

TYPICAL AOORESSANO DATA INPUT LEVELS vs. VOO 3.0

VOO SUPPLY VOLTAGE (VOLTS)

TYPICAL CLOCK INPUT lEVELS VI Vaa 3. 0 Vea SUPPLY VOLTAGE (VOLTS)

TYPICAL ADDRE.~ AND DATA INPUT lEVELS vs Vea Vea SUPPLY VOLTAGE (VOLTS)

IV-62

T J. JUNCTION TEMPERATURE (oC)

TYPICAL ADDRESS AND DATA INPUT lEVELS vs. TJ

TJ. JUNCTION TEMPERATURE (Gel

MOSTEI{.

MEMORY COMPONENTS

65,536 x 1-.Bit Dynamic RAM MK4564{P INI J)-15/20/25

FEATURES

D Recognized industry standard 16-pin configuration from Mostek

D Single +5V (± 10%) supply operation

D On chip substrate bias generator for optimum performance

D Low power: 300 mW active, max 22 mW standby, max

D 150 ns access time, 260 ns cycle time (MK4564-15) 200 ns access time, 345 ns cycle time (MK4564-20) 250 ns access time, 425 ns cycle time (MK4564-25)

DESCRIPTION

The MK4564 is the new generation dynamic RAM.

Organized 65,536 words by 1 bit, it is the successor to the industry standard MK4116. The MK4564 utilizes Mostek's Scaled POLY 5 process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. The use of dynamic circuitry throughout, including the 512 sense amplifiers, assures that power dissipation is minimized without any sacrifice in speed or internal and external operating margins. Refresh characteristics have been chosen to maximize yield (low cost to user) while maintaining compatibility between dynamic RAM generations.

PIN FUNCTIONS

"a-

A 7 Address Inputs RAS(RE) Row Address Strobe CAS(CE) Column Address WRITE(W) Read!

Strobe Write Input

D'N(D) Data In Vee Power (5V)

DOUT(Q) Data Out _Vss GND

N!C Not Connected

Available soon in MIL-STD-883 Class B (MKB).

D Extended DOUT hold using CAS control (Hidden Refresh) D Common 1/0 capability using "early write"

D Read, Write, Read-Write, Read-Modify-Write and Page-Mode capability

D All inputs TIL compatible, low capacitance, and protected against static charge

D Scaled POLY 5™ technology D 128 refresh cycles (2 msec)

Pin 9 is not needed for refresh D MKB version screened to MIL-STD-883

Multiplexed address inputs (a feature dating back to the industry standard MK4096, 1973) permit the MK4564 to be packaged in a standard 16-pin DIP with only 15 pins required for basic functionality. The MK4564 is designed to be compatible with the JEDEC standards for the 64K x 1 dynamic RAM.

Theoutputofthe MK4564 can be held valid upto 10 J1.sec by holding CAS active low: This is quite useful since refresh cycles can be performed while holding data valid from a previous cycle. This feature is referred to as Hidden Refresh.

The 64K RAM from Mostek is the culmination of several years of circuit and process development, proven in predecessor products.

PIN OUT

DUAL-IN-LiNE PACKAGE

16 vss

DINID} 2 15 CAS (eel

WRil'EjW) 3 140oUT(Qj

RAs lIfE) 4 13 As

Ao 5 12 A]

A, 6 11 A4

A, 7 10 As

Vee 8 9 A,

IV-63

1'1

ABSOLUTE MAXIMUM RATINGS*

Voltage on Vcc supply relative to VSS ., ...•...••....•... -1.0 Vto +7.0 V Operating Temperature, TA (Ambient)" ...•...••...•..••.. O°C to +70C Storage Temperature (Ceramic)' .•..••.... , .•...•...•...••... -65°C to +150°C Storage Temperature (Plastic) ..•...•.... ' .•...•...••... -55°C to +125°C 'Power Dillsipation .•... ',' .•...•...•..•...•...•...•... 1 Watt Short Circuit Output Current ...• ;' ..•...••...•..•...•.••.•.•...•... 50 mA

*Stres~es greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (O°C ::::; T A::::; 70°C)

SYM PARAMETER MIN

VCC Supply Voltage 4.5

V1H Input High (Logic 1) Voltage, 2.4 All Inputs

V1L Input Low (Logic 0) -2.0

Voltage, All Inputs

DC ELECTRICAL CHARACTERISTICS (O°C ::::;TA ::::; 70°C) (Vcc = 5.0 V

±

10%)

SYM PARAMETER

ICC1 OPERATING CURRENT

Average power supply operating current (RAS, CAS cycling; tRC = tRC min.) ICC2 STANDBY CURRENT

Power 'supply standby current (RAS ,= V1H' DOUT = High Impedance)

ICC3 RAS ONLY REFRESH CURRENT

Average power supply current, refresh mode (RAS cycling, CAS = "IH; tRC = tRC min.) 'CC4 PAGE MODE CURRENT

Average power supply current, page mode operation

(RAS

= V1L' tRAS '= tRAS max., ~ cycling; tpc = tpc min.)

'I(L) INPUT LEAKAGE ^\

Input leakage current, any input

(0 V::::; V1N ::::; Vcc), all other pins not under test=OV

'O(L) OUTPUT LEAKAGE

Output leakage current (DOUT is disabled,

o

V::::; VOUT ::::; Vce!

OUTPUT LEVELS

VOH Output High (Logic 1) voltage (lOUT = -5 mAl VOL Output Low (Logic 0) voltage (lOUT = 4.2 mAl

IV-64

TVP MAX UNITS NOTES

5.0 5.5 V 1

-

Vcc+1 V 1

-

^.8 ^V 1,18

MIN MAX UNITS NOTES

54,0 mA 2

4 mA

45 mA 2

35 mA 2

-10 10 p.A.

2.4 V

0.4 V

NOTES:

1. All voltages referenced to Vss

2.ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

3. An initial pause of 500 JiS is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. Note that RAS may be cycled during the initial pause

4. AC characteristics assume tT = 5 ns.

5. V1H min. and VIL max. are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL'

6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (DoC::; TA :::; 70°C) is assured.

7. Load = 2 TIL loads and 50 pF.

8. Assumes that tRCD :::; tRCO (max). If tRCO is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCO exceeds the value shown.

9. Assumes that tRCO 2 tRCD (max).

10. tOFF max defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL.

11. Operation within the tRCO (max) limit insures that tRAC (max) can be met.

tRCO (max) is specified as a reference point only; if tRCO is greater than the

specified tRCO (max) limit, then access time is controlled exclusively by

tCAe-12. Either tRRH or tRCH must be satisfied for a read cycle

13. These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in delayed write or read-modify-write cycles.

14. twcs, tCWD' and tRWD are restrictive operating parameters in READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs :> twcs (min) the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If teWD:2 tewD (min) and tRWD:2 tRWD (min)the cycle is a READ/WRITE and the data output will contain data read from the selected cell. If neither of the above conditions are met the condition of the data out (at access time and until CAS goes back to VIH) is indeterminate.

15. In addition to meeting the transition rate specification, all input signals must transmit between VIH and VIL (or between VIL and VIH) in a monotonic manner

16. Effective capacitance calculated from the equation C::: I.£.! with f::. V:: 3 volts and power supply at nominal level f::. V

17. CAs = VIH to disable DOUT

18. Includes the DC level and all instantaneous signal excursions.

19. WRITE::: don't care. Data out depends on the state of CAS. If CAS = VIH, data output is high impedance. If CAS = VIL, the data output will contain data from the last valid read cycle.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (3A.5,15)(0°C:::; TA :::; 70°C), VCC ⁼5.0 V ± 10%

SYMBOL MK4564-15 MK4564-20 MK4564-25

STD ALT PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTES

tREHWX tRRH Read command hold time

referenced to RAS 20 25 30 ns 12

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (3,4,5,15) (0° :c:; T A:C:; 70°C), V cc

=

^{5.0 V}

±

^10%

SYMBOL MK4564-15 MK4564-20 MK4564-25

STD ALT PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTES

tWHCEL t RCS Read command set-up time tCEHWX tRCH Read command hold time

referenced to CAS tCELWX tWCH Write command hold time tRELWX tWCR Write command hold time

referenced to RAS

tWLWH twp Write command pulse width tWLREH tRWL Write command to RAS lead time tWLCEH tCWL Write command to CAS lead time t DVCEL t DS Data-in set-up time

tCELDX tDH Data-in hold time tRELDX tDHR Data-in hold time referenced to RAS tCEHCEL tcp CAS precharge time

(PC) (for page-mode cycle only) tRVRV tREF Refresh Period

tWLCEL twcs WRITE command set-up time tCELWL tCWD CAS to WRITE delay tRELWL tRWD RAS to WRITE delay tCEHCEL t CPN CAS precharge time

AC ELECTRICAL CHARACTERISTICS (Oo:c:; TA:C:; 70°C), VCC

=

^5.0V

±

^10%

SYM PARAMETER

C_il Input Capacitance

(Ao -

^A7), DIN CI2 Input Capacitance RAS, CAS, WRITE Co Output Capacitance (D_OUl)

0 45

115 35 45 45 0 45

115

-10 55 120

IV-66

0 0 ns

0 0 ns 12

55 70 ns

150 185 ns

45 55 ns

55 65 ns

0 0 ns 13

55 70 ns 13

150 190 ns

75 85 ns

2 2 2 ms

-10 -10 ns 14

80 100 ns 14

165 205 ns 14

35 45 ns

MAX UNITS NOTES

5 pF 16

10 pF 16

7 pF 16,17

READ CYCLE

RAS

V_{1H _}

V'L-CAS

^V'H_

V'L-ADDRESSES V_{1H _}

II

V'l-WRITE

V_{1H _}

V'l-tOFF

DOUT VOH _

OPEN VOl _

WRITE CYCLE (EARLY WRITE)

RAS

V_{1H _} V_1L

-CAS

V'H-V1l

-ADDRESSES V'H_

V'l-WRITE V_1L

-D'N V'H_

V1L

-tOHR

Dour

VOH-OPEN

VOl-IV-67

READ-WRITE/READ-MODIFY-WRITE CYCLE

RAS

V_{1H _} ADDRESSES V

-VVifITE

V'H_ ~~7r.~~~7r.~r---~---~i

V IL - ~'""'"''f''~~'"''

VOH

-VOl_---~---O

V'H _ "'"7r.>7777>'77:7r.~7n'77:>77~'77:>77~7n7r.>7777>"7'"?;"77'."'" .r-~:-:-:-;~'lI.. "''7n7r.777'7n7r.777","7'"?;'7;

V'l-~~~~~~~~~~~~~GU,",~GU,"",",~~ ~~~~~ ~~~~~~,"",",~LL

"RAS-ONL Y" REFRESH CYCLE

t Re

tRAS

{ ^L

_ t RAH tRP

I I

tASR ~

ADDRESSES

IV-58

Dans le document 1982/1983 (Page 110-122)

PAGE MODE WRITE CYCLE

32,768x1-BIT DYNAMIC RAM