This bit is ‘V when the pattern generated fran the input data 0
to in bsfEer does not match with the CRC pattern generated
from Zn register output data. This bit is ‘O
•while NC! is
OFF.
. .(Ii) *ZBIC
•(*XBF Bus In Check)
. . .This bit is set wbeá illegal ErR Buffer Input data pattern is detected. This bit is not reset until NC! is turned OFF.
This bit is ‘0’ while NC! is OFF.
. .A
4
—68
RD DATA CR side
DV side
B=C • . . Invalid for BWD,
B=D . . . Invalid except in 6250
FWD mode Figure 4.17
Table 4.21
Input Byte Operation Mbde
CRCA CRCB CRC CRCC CRCD
6250 XBF Input XBF Output Data, Pad, Data, A.ux, CRC
data data ux. CRC Aux. CRC
CRC Byte,
(Write-’Write (Write*Write 1 Byte (BRD only) 03RD not
Data, Data, feasthie)
Read Read Read-Read
Data) Data)
1600 Data
800 Data, CRC Data
WT DATA
RD DATA
*MCRCC
B
4 69
(16) FMERR (Format Error): hF
DC CK
:c
iSC :RC(a) *SRDC (Not Start Read Check)
This bit is turned ON, if the PREA signal (Start of Data Field Detection Signal) is not set within the specified delay time after P110K. This signal remains at ‘0’ till MCY is OFF. This bit is ‘1’ while MCY is OFF. This bit, ‘1’, means that Start Read Check error has not been detected in the Read Operation.
Tab le 4,22 SRDC Set condit ion
Mode Condition
WRS When PREA=O upon specified delay of 120 ± 8 bit cells after P140K set.
6250
RDS When PREA=0 upon specified delay of 168 ± 8 bit cells after PHOK set.
WRS When PREA0 upon specified delay of 52 ± 4 bit cells after PHOK set.
1600
RSD When PREA=O upon specified delay of 63 ± 4 bit cells after PHOK Set.
This bit is not available in 800 BPI mode.
(b) *EDCK (Not End Data Check)
This bit is turned ON if DIBG signal cannot be detected within the specified time after 1POSA (see Table 4.23 for a specified time delay after preamble). Once set to ‘0’ it is not reset (‘1’) till I,1CY is OFF. It is ‘1’ while MCY is OFF. This bit,
‘I’ may be assumed that End Data Check Error has not occurred in the Read Operation.
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Table 4.23 EDC Condition
Hode Condition
WRS When DIBCO upon delay of 88 ± 8 bit cells after EPOSA1,
6250
RDS When DIBC=0 upon delay of 248 ± 8 bit cells after EPOSA.=1.
WRS When DIBC0 upon delay of 20 ± 4 bit cells after EPOSA=I.
1600
ROS When DIBCzO upon delay of 36 ± 4 bit cells after EP0SA1.
Not available in 800 BPI mode.
(c) *SL1PC (Not Slip Check)
This bit is set to ‘0’ upon detection of data write (800 BP1) or DNOIS signal (6250/1600 BPI) while the above mentioned WWD signal (section (14), d) is ‘1,. Once set to ‘0’, the status of this signal remains unchanged till MCY is turned OFF. This bit is ‘1’ while MCY is ‘1’.
This bit ‘I‘ , may be assumed that no s lip check error has occured in Write Operation. This bit is ‘1’ when MCY or STPHK is ‘0’.
(d) *NO1SC (Not Noise Check)
This bit is set to ‘0’ when data byte (800 BPI) or DBOB signal (6250/1600 BPI) is detected within the specified delay time after starting Write Operation (WOK Rise). Once set to ‘0’
the status of this signal remains unchanged till MCY is turned OFF. This bit is ‘1’ when MCY is OFF. This bit is ‘1’ when MCY or STPHK signal is ‘0’ .
(e) *WTf3OC (Not Write Data Bus-Out Check)
This bit is set to ‘0’ when a parity error is detected in the Write Bus Data to be entered to the Write Circuit. This bit i_s not set to ‘0’ when the above mentioned WTCTL register ALIWT bit is set to ‘0’.
4 71
This bit remains in ‘0’ status while MCY is OFF. This bit is set to ‘1‘ by HCLR s ignal. When this bit is ‘1‘ it may be assumed that no parity error has occurred in Write Circuit during Write Operation.
(1) *WTVRC (Not Write VRC)
This bit is set to ‘0’ when a parity error is detected in the modulated Write Data . Once set to ‘0’ the status of this byte remains unchanged till KCY is turned OFF. When this bit is ‘1’ it may be assumed that no parity error has occurred in modulated data in Write Operation.
(8) *OVRN (Not Over Run)
This bit is set to ‘0’ when overrun is detected in Read/Write Operation. Once set to ‘0’ the status of this bit remains unchanged till KCY is turned OFF, This bit is ‘0’ when MCY is OFF. When this bit is ‘1‘ , it may be assumed that overrun error has not been detected in Read/Write Operation.
- OVRN Set Condition —
1. When DXF1=1 (Read Operation)
. If XFR Buffer is Full (BFUL=1) 2. DXFO1 (Write Operation)
. If XFR Buffer became empty (CMP=1) before receiptor
“transfer STOP” from the chann€I. interface during Write Operation.
. If the data left in the XFR buffer was less than 6 bytes before the “transfer STOP” was issued by the channel interface in 6250 mode Write operation.
(h) *CMP (Not Compare)
This bit is set to ‘0’ if the XFR buffer Read-In count and Read Out count do not match. This bit indicates the presence or absence of data in XFR buffer. There is no data in FR buffer if this bit is ‘0’ and there is data in the buffer if this bit is ‘I’ This bit is ‘0’ when MCY is OFF.
(17) TSNS (Time Sense): 50
[NSO 4:52 SS3 S:S4 S:S5 4:56
4 —. 12
Each of these bits is ‘0’ when the peak pulse of the tracks rising and falling and falling edgepulse of Read Data, corresponding to these bits has been coming with required period and with specified cycles. *TSNSO7 are all ‘l’s while MCY is OFF. Peak pulse niay only be generated if ROK1.
(18) POUIT (Pointer): 51
TO Tl T2 ‘T3 T4 T5 T6 T7
DET • . . Detect Error Track
This is an error track pointer used in Read write operation in 6250/1600 BPI mode. All the bits are ‘1’ while MCY is OFF.
DETO’8 are set by dead track (skew, persistant track, drop out) valid pointer or ECC group buffer pointer.
(19) BLFMT (Block Format): 52
O2CR ET8 s:S8 :BG N:Is :OB TM
(a) *1O2CR (No 1 or 2 track correction)
This bit is set to ‘0’ if I or 2 track error correction has been executed in 6250/1600 BPI read operation. Once set to
to,
this bit remains in this status ti]]. MCY is OFF. This bit is ‘1’ while MCY is OFF.When SCAN bit is ‘1’, this bit represents a scan out signal of LSI chips related to read operation.
(b) *DET8 (No Detect Error Track 8) Refer to section (18), *DETO7.
(c) *TSNS8 (No Time Sense 8)
Refer to section (17). TSNSO’7.
(d) *DIBG (Not Detect 1GB)
This bit is ‘1, when TSNO8 represents IBG pattern.
4 — 13
(e) *DNO1S (Not Detect Noise)
This bit is ‘0’ when TSNSO”8 represents NOIS pattern.
(f) *DBOB (Not Detect BOB)
This bit is ‘0’ when TSWSO8 repuesents BOB patLern.
(g) *DARA (Not Detect MA)
This bit is ‘0’ when TSNSO’8 represents ARA pattern.
(Ii) *L)TM (Not Detect TM)
This bit is ‘0’ when TSNSO8 represents TM patten. It is also ‘0’ when TM byte is detected in 800 BPI mode,
DIBGO+I+24-3+4+5+6+7+8 DNOIS : A+B
A (O.5.8)÷(2.6.7)+(1.3.4) B (O÷5i-8).(2÷6÷7).(1÷3f4) DBOB A.B
DTM cL÷3÷4{o.5.82.6.n
+PE.R DS[(O.5.8)+(2.6.7)]
+GCR.RDS[(2 .6.7)(O÷5f8)÷(O.5 .8)(24-6-1-1)]}
DMA (O÷8+5){(1.3.4)(2.6.7)
÷RDS[(l.3.4)(2÷6+7)÷(li-3÷4)(2.6.7)]}
O’8 TSNSO’’8
(20) RDERR (Read Error): 53
(*) S:WE *D:CK *D:OE PNMLT *PO:AE t*:t.
(a) *vRC: (No VRC Error)
This bit; is set to ‘0’ when a Read Data Parity Error is detected and cannot be recovered by the pointer or ECC. Once this bit is set to ‘0’ it remains in this status till. MCY is turned OFF. This bit is ‘I’ while NCY is OFF. This bit, ‘0’, indicates an incorrectable VRC error. Error is not corrected if the above IHCOR bit has been set.
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