PHOK signal
*HIG bit
Figure 4.15 *HIG bit control in 6250 BPI mode
(g) ISPILE (Issue Phase Error)
This bit is used to generate a phase error. A phase error is (PilE) generated in the track corresponding to the MASK bit O-9 which have been turned ON. (For further details refer to Chapter 9).
This bit is reset by HCLR signal.
(h) SKWMG (Skew Marginal)
The skew check condition is set to marginal as soon as this bit is turned ON. This bit
may
be used only in 1600 mode.This bit is reset by HCLR signal.
(13) MODE (Mode Select): 4C
0 1 2 3 4 5 6 7
*HIG bit i
__________
MCY BWD WKS ZRD 6250 1600 CMCY CBR
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(a)
MCY (Machine cy1e)The MCY signal is turned ON to enable Read, Write, Device Control Circuits. In this stage these circuits may be controlled from microprogram while MCY signal is Ot.
This bit is reset by HCLR signal, (b) BWD (Backward)
This bit is turned ‘ON’ (set to 1) to set the MTC Read circuit to Backward Mode. This bit is read by HCLR signal.
(c) WRS (Write Status)
This bit is turned ON (set Lo ‘1’) to set the MTC R/W circuit to Write Mode,
The following check conditions may be affected by this bit:
1*115 (Noise Block) check condition.
Postamble Read End (EPOSA) condition. STRCK (Start Read Check) condition. HTM (tape mark detection, skew mark, error correction and other control conditions. Read status is set when this bit is ‘0’. This bit is reset by HCLR signal.
(d) NRD (NRZ Read)
This bit is set to execute 800 BP1, Read/write opetation When this bit. is on the modulation circuit will generate a peak pulse as the data rises if the BWD bit is ‘1’ and a peak pulse as the input data falls if the BWD bit is ‘0’. Both the pulses are generated as peak pulses.
This bit is reset by HCLR signal.
(e) 6250 (6250 mode)
This bit is set to ‘1’ to execute 6250 BPI Read/Write operation. This bit is reset by HCLR signal.
(f) 1600 (1600 mode)
This bit is set to ‘1’ to execute read/write operation in 1600 BPI mode.
This bit is reset by the HCLR signal.
(g) CMCY (Complete MCY)
This bit is not used. This bit is reset by HCLR signal.
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(Ii) CBR (Channel Buffer Read)
This bit is
set
to ‘1’ to execute a channel buffer Read operation. As soon as this bit is set to ‘1’, the data transmit control section repeatedly transfers the channel buffer data, This bit is reset by HCLR signal.(14) RDSNS (Read Format Sense): 4D
IS K K FA SA SA
(a) HNLS (Noise Block Detected)
If a noise pattern is detected (DNois1) for a duration described in Table 4.17 this bit is set to ‘1’. This bit remains unchanged till ROK is turned OFF. ROK is OFF.
Table 4.17 HNIS set condition
Mode Condition
WRS 46 ± 2 Bit cell period, continuous PNOIS 6250
RDS 22 ± 2 Bit cell period, continuous PNOIS WRD 23 i 2 Bit cell period, continuous PNOIS 1600
RDS li ± 1 Bit cell period, continuous POINS
This bit is not set in 800 BPI mode,
(b) HBLK (Block Detected)
If a block pattern (DB0B’1’) is detected for a duration in excess of the specified bit cell period, this bit is set to
e t • This bit remains unchanged till it is reset when ROK is turned OFF. This bit is in Reset status while ROK is OFF.
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Table 4.18 HBLK set condition
Mode Condition
WRS 25 ± 1 Bit cell period, continuous DBOB 6250
RDS 25 ± 1 Bit cell period, continuous DBOB WRS 12.5 ± 05 Bit cell period, continuous DBOB 1600
RDS 12.5 ± 0.5 Bit cell period, continuous DBOB
This bit is not set in 800 BPI mode.
(c) 11TH (Tape Mark Block Detected)
If a tape mark block pattern (DTM=’l’) is detected continuously in excess of the specified bit cell period, this bit is set to ‘1‘ . This bit remains unchanged till reset when ROK i.s OFF. This bit is reset while ROK is OFF.
Table 4.19 HTM setting condition
Mode Condition
WRS 304 ± 8 Bit cell period, continuous DTM 6250
RDS 42 ± 2 Bit cell period, continuous DTM WRS 84 ± 4 Bit cell period, continuous DTM 1600
RDS 21 ± 1 Bit cell period, continuous DTM
This bit is not set in 800 BP1 mode.
(d) WIND (Window)
In Write operation, this signal becomes ‘1’ during a specified period after specified delay time has elapsed from starting Write operation. The leading of the block recorded in the corresponding write operation should be detected while this signal is ‘1’. The data bytes (800) or DBOB detected between
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the period from starting the Write Operation till rise of this signal. Will set NOISC signal (described later) to ‘I’.
The SLIPC (described later) will be set to ‘I’ if Wind Signal i_s set to ‘0’ without detecting a data byte (800) or DNOIS signal. Figure 4.15 shows set and reset timing of WIND signal.
-WOK rising edge WOKR
7%
R/W gap period Figure 4.16 WIND signal
(e) P1(0K (Phase OK)
This signal is set while HBLK signal rises when STPHK has been set. This signal is reset when the EPOSA signal rises (described later) or STP[LK is reset. While this signal. is ON, Write data error cheek and correction are available.
(f) PRKA (Preamble Detected)
This signal is set to ‘I’ upon detection of the first data byte in the 6250, 1600 BPI Read Circuit. The status of this signal remains unchanged till P110K is reset. This bit is in reset status while PHOK is ‘0’.
(g) POSA (Postamble Detected)
This signal is set to ‘1’ upon detection of the last data byte (Head of Postamble) in 6250, 1600 T3P1 Read Circuit. This bit remains unchanged till. PHOK is reset. This bit remains in reset status while P110K is ‘0’.
(h) EPOSA (End of Postamble)
This bit is set to ‘1’ after the specified length of postatable i_s confirmed in 6250, 1600 BPI Read/Write operation. This bit is reset (‘0’) when DIBG signal rises, This bit is in reset status while MCY is OFF
WIND 2O%
100%
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Table 4.20 EPOSA set condition
Mode Condition
WRS After POSA1 and after a delay of 34 ± 2 bit cells.
6250
RDS After POS&=1 and after a delay of 6 t 2 hit cells.
CRCST (CRC Status): 4E
.
0 1 2 3 4 5 6 7
(15)
Hi;;c cz
=CR RCC(a) *MCRC (Unmatch CRC)
This bit is when the CRC pattern generated as a result of operating on the Read Data (including CRC byte) is
not
normal (bits other than 2, I of CRC register are ON). This hit is employed in Read, Write, and Back Read operations in 6250, 800 mode, This bit is ON (‘1’) when I’ICY is OFF,(b) *MCRCZ (Unmatch CRC zero)
This bit is ‘I when the CRC pattern generated as a result of operating on Read data (including CRC pattern) is not all
‘0’s. This bit is employed in Read, Write and Back Read Operations in 800 mode. This bit is ‘0’ when MCY is OFF.
(c) *EPCR (EP/CR)
This bit is ‘EL’ if the pattern obtained by reversing the pattern (except bits 2, 4) generated by operating on the Read data (including CRC byte) does not match with the error pattern register. It is used for detecting errors along with the *MCRCZ signal in 800 mode. This bit is set to ‘1’ while MCY is OFF.
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(d) *BD (CRCThCRCD)
This bit is employed in Read, Write operations (excluding Back Read)
in
6250 mode. This bit is turned ON C‘1‘) when the Aux—CRC byte (CRCD) does not match with the CRCB pattern (CRC generated from transfer Buffer output). This bit is ‘1’ while MCY is OFF.(e) *BC (CRCB4CRCC)
This bit. is employed in 1600, 800 mode write operation. This bit is turned ON when the Write Data CRC pattern (obtained from CRCB - XFR buffer output) does not match with the After Read data (excluding CRC byte) CRC pattern. This bit is set to ‘0’ while I4CY is OFF.
( f ) *HCRCC (Unmatch CRCC)
This bit is ‘1’ when the CRC patLetn obtained from Read Data (excluding CRC byte) is not normal. This bit. is employed in Back Read processing in 6250 mode. This bit is ‘1’ while MCY
is off.
(g) *AB (CRCA4CRCB)
This bit; is ‘1’ when the pattern generated from the input data to XFR buffer does not match with the CRC pattern generated from XFR register output data This bit is ‘0’ while MCY is OFF.
(h) *XBIC (*XBF Bus In Check)
This bit is set when illegal XFR Buffer Input data pattern is detected. This bit is not reset until MCY is turned OFF.
This bit is ‘0’ while MCY is OFF.
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RD DATA
CR side
Figure 4.17
Table 4.21
Dv side
Input Byte Operation Mode
CRCA CRCB CRC CRCC CRCD
6250 XI3F Input XBF Output Data, Pad, Data, Aux, CRC
data data Aux. CRC Aux. CRC
CRC Byte,
(Write+Write (Write’Write 1 Byte (BRD only) 03RD not
Data, Data, feasible)
Read Read ReadRead
Data) Data)
16 00 Data
800 Data, CRC Data
WT DATA
RD DATA
*MCRCC
B=C . .. Invalid for BWD,
B=D . . . Invalid except in 6250 FWD mode
4 -“. 69
(16) FMERR (Format Error): 4F
DC CK IPC ISC
:oc
VRC RN MP(a) *SRDC (Not Start Read Check)
This bit is turned ON, if the PREA signal (Start of Data Field Detection Signal) is not set within the specified delay time after PHOK. This signal remains at ‘0’ till MCY is OFF. This bit is ‘1’ while MCY is OFF. This bit, ‘1’, means that Stad Read Check error has not been detected in the Read Operation.
Table 4.22 SRDC Set condition
Mode Condition
WRS When PREA=O upon specified delay of 120 ± 8 bit cells after P140K
set.
6250
RDS When PREAO upon specified delay of 168 ± 8 bit cells after PHOK
set.
WRS When PREA=O upon specified delay of 52 ± 4 bit cells after PHOK
set.
1600
RSD When PREA0 upon specified delay of 63 ±
I’ bit cells after P110K Set.
This bit is not available in 800 BPI mode.
(b) *EDCK (Not End Data Check)
This bit is turned ON if t)IBG signal cannot be detected within the specified time after TPOSA (see Table 4.23 for a specified time delay after preamble). Once set to ‘0’ it is not reset (‘1’) till MGY is OFF. It
is
‘V while MCY is OFF. This hit,‘1’ may be assumed that End Data Check Error has not occurred in the Read Operation.
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Table 4.23 EDC Condition
Mode Condition
WRS When DIBCO upon delay of 88 ± 8 bit cells after EPOSA:1.
6250
RDS When DIBC=0 upon delay of 248 ± 8 bit cells after EPOSA=1.
WRS When DIBC0 upon delay of 20 ± 4 bit cells after EPOSA=1.
1600
ROS When DIBC0 upon delay of 36 ± 4 bit cells after EPOSA=1.
Not available in 800 BPI mode.
(c) *St4IpC (Not Slip Check)
This bit is set to ‘0’ upon detection of data write (800 BP1) or: DtJ0IS signal (6250/1600 BPI) while the above mentioned WltTD signal (section (14), d) is ‘1’. Once set to ‘0’, the status of this signal remains unchanged till MCY is turned OFF. This bit is ‘1’ while MCY is ‘1’.
This bit, ‘I‘ , may be assumed that no slip check error has occured in Write Operation. This bit is ‘1’ when MCY or STPHK is ‘0’.
(d) *NOISC (Not Noise Check)
This bit is set to ‘0’ when data byte (800 BPI) or DBOB signal (6250/1600 BPI) is detected within the specified delay time after starting Write Operation (WOK Rise). Once set to ‘0’
the status of this s igna I remains unchanged t ii 1. MCY is turned OFF. This bit is ‘1’ when MCY is OFF. This bit is ‘1’ when KCY or STPHK signal is ‘0’.
(e) *WTBOC (Not Write Data Bus-Out Check)
This bit is set to ‘0’ when a parity error is detected in the Write Bus Data to be entered to the Write Circuit, This bit is not set to ‘0’ when the above mentioned WTCTL register ALIW’1
1 bit is set to ‘0’.
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