Bits LAM, K.SVI, LSTV, RQIAF and RQIBF are ‘0’ when this bit is •1’. Set this bit to ‘0’ to clear DCI bit. This bit
is also reset by the SKIT signal.
(30) CURl (Channel Bus-tn): 3D
0 1 2 3 4 5
.6 7
L .CBfl CB12
.CB13 CBI4 CBX5 ai
CA) (*B) (SDI)
This is a register to send fts-tn signals for the channel
.I/O address (with LADI bit)
,status byte (with tSfl bit)
,sense data (with N.m bit), etc. sy be stored in this register. This register is cleared by SKIT signal
.CBIO-2 are assigned to Scan Clock A, Scan Clock B and the Scan Data when the SCAN bit is set to
t1ta .
V
4 84
(31) 1FCTL (InterFace Control): 5E
(a) R.RSTA (Reset RSTA) /OVRN2 (over run 2)
SetLing this bit to 1, th above mentioned signals SERA, SYRA are reset (‘0’). They should be reset upon completion of selective reset or system reset operation The OVRN2 signal
i_s
turned ON if overrun is detected in data transferin offset
interlock mode (refer to section 472)(b) S.BCT (Set Byte Counter)/*XTAG (No Transfer Tag)
Setting this bit. to ‘1 , content of the CHBI register is preset in the upper 8 bits of the 12 bit byte counter. Now
‘1, is entered in the lower 4 bits. Tf SHBC is ‘0’, the Cl-Ill bit. correspond to 24LS8. If SI-LBC is ‘1’ (described later), the CUll bit corresponds to 20 LSB. in the case the byte counter becomes an 8 bit counter and is capable of counting upto 255 bytes.
This function may be employed only if NTC is in off line status. *XTAG 1’ indicates that in—-tag and out-tag signal for data transfer to and from the channel have not been generated. Those signals are SVI signal (service in), DTI (data in) signal and SVO (service out), DTO (data out) signals respectively.
(c) SFIBC/DXFE (Short Byte Counter/Data Transfer End)
Sl-LBC is employed to iuake the byte counter act as 8 bit counter.
DXFE signal is provided to indicate any data transfer with format circuit has finished. This signal is set to ‘1’ by
,
sioi”
(CMO=I), DISCONNECT from Cl-I linked to the MTC or by the carry from the above byte counter (in case of MTC off line).DXFE is ‘0’ when NCY is turned OFF.
(d) S.UCT/DXRQ (Start. Up Count/Data XFR Request)
Setting this bit to ‘l, the Position Check FTP counter starts counting FTP in UP count mode.
DXRQ is a data tcansfer request signal from the formatter circuit. Now DXRQ1 indicates that SFR buffer is not full (when DTFO=1) or data is still left in SFR buffer (when DTF1d).
‘1 - 85
If both DTFO and DTFI are ‘O , DXRQ is ‘0’ It. may also be
•0• if IHDRQ bit is ‘1’.
(e) SDCT/B1BSY (Start Down Count/Bus In Busy)
Setting this bit t.o 1, the Position Cheek FTP counter start counting FTP in Down Count Mode.
BIBSY
is
‘I’ if the data stored in CR131 register does not move to XFR buffer data from up to the XFR buffer is stored (Via CI-IBI Register). MP should confirm that BIBSYO before settingthe
next data in CHBI register.(f) CTSTP/*ABRPC (Counter Stop/No A,B Register Parity Check)
The Position Check FTP counter is stopped when CTSTP is set to
‘l’. *ABRPC is set to ‘0’ if a parity check has detected in A.
and B registers during data transfer from MTC to the channel.
Once set to ‘0’ it remains in this status till. MCY is turned OFF This bit, ‘1’, indicate that parity error was not detected in A or B registers during data transfer from MTC to Cu.
(8) R.RCT/*BOPC (Reset Reposition Counter/No Bus Out Parity Check) R.RCT is set to ‘1’ to clear position check FTP counter to all
‘0’s. *BOPC is ‘0’ if a Bus Out parity error has detected in data trans fer from the channe 1.
Once set to ‘0‘ , *BOPC remains in this status unti I MCY is turned OFF. While MCY is OFF, this bit is ‘0’ if there is a parity error in the Bus-Out data and is 1 if no parity error
is found in the Bus Out data.
While MCY is ON, *BOPC ‘0’ indicates that no. Bus Out Parity error has detected during data transfer, While MCY is OFF, it indicates that there is no parity error in the present Bus Out data.
(h) R.CRY/C.RCT (Reset Carry/Carry of Reposition Counter)
R.CRY is set to ‘I’ to reset overflow of the position check FTP counter.
C.RCT
i.s
changed to ‘1’ upon detection of carry in the above mentioned counter. It remains in this state till MCY is turned OFF or R.CRY is set. C.RCT is therefore ‘0’ while MCY is OFF.I’ _ 86
(32) XFCTL (Transfer Control): 5?
0 1 2 3 4 5 6 7
DXFI DXFO MPFD SCAN EBOPI CMROI4 ROM2 ROM1
(a) DXFJ. (Data Transfer In)
Set this bit to ‘I’ for data
transfer
from MTC toa channel.
This sets the
data
transfer circuit to enable in the required direction. This bit. is reset by SERT signal,(1) DKFO (Data Transfer Out)
Set this bit. to ‘1’ to enable data transfer from the channel to MTC. This sets the data transfer circuit to enable in the required direction. This bit is reset by SERT signal.
(c) IPRD (Microprogram Read)
Set this bit to ‘1’ to store MP data to XFR buffer. This bit is reset by SERT signal.
(d) SCAN (Scan Mode)
Setting this bit to ‘1’, all the LSI FF5 in the formatter circuit are in serial scan mode. Scan operation is countrolled by C8IO”2 bits described earlier. SCAN function i_s used with diagnose operations. This bit is reset by SERT signal.
(e) FBOP1 (Enable OP1 - OFF)
Setting this bit to ‘1’, the OPI signal is immediately reset when ‘Se lect Out‘ from the channe I linked with MTC is released.
If this bit is ‘0‘ , the OPI s ignal wil 1 remain unchanged even if the above ‘Select Out’ is released.
(
f) CMROM (Command ROM So lect)When this bit is ‘I‘ , converted command code (CMO’3) is represented in bits 4’7 of the above mentioned TOADA resister (58).
Moreover CHTJO register (5A), hits CBOO 7, is represented position
check
counter output RCTO- 7. This bit is reset by SERT signal.‘I — 87