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512 Graphics DotsNOTE:
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; Graphics BoundaryL-
; Alpha BoundaryFigure 3-14. Display Specifications
Video Board Overview
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390 Scan Lines
The video board contains the digital logic used to display alpha and graphics information on the screen. Alpha information is addressed from a plane separate from graphics information. To do this, it performs the following functions:
1. Stores the information to be displayed in alpha and graphics RAM.
2. Produces an alpha dot stream.
Hardware Subsystems
3. Produces a graphics dot stream.
4. Mixes the two dot streams and sends the resulting control signals to the sweep:
NFB not full bright NUB not half bright.
5.
Provides deflection control signals used by the sweep;NVSYNC vertical sync HSYNC horizontal sync.
Figure 3-15 shows the major components of the video board and the flow of data and control information between them. The following list provides a brief description of each of these components.
1. Processor Request and Wait Generation:
Decodes 8088 access to the alpha or graphics RAM producing signals used by the RAM controllers. Also inserts necp-ssary processor wait states.
2. Graphics RAM interface:
Interfaces the 8088 and the Graphics Display Controller Chip (GDC-3091) to the graphics RAM.
3. Graphics RAM:
32K x 8 block of dynamic RAM which is used to store graphics information. Because the graphics is a bit map display the information is stored in that format. A portion of the RAM is also used by the alpha video firmware to store variables.
4.
Graphics Display Controller Chip:Custom gate array graphics controller which retrieves data from the graphics RAM and forms the graphics dot stream. Also provides graphics RAM timing signals.
5.
Alpha RAM controller:Interfaces 8088 to the alpha RAM and to the
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9007 video controller. Also interfaces the SHC 9007 to the alpha RAM.6. Alpha RAM:
12K x 8 block of static RAM which stores the alpha information to be displayed.
7. SHC 9007 Alpha Video Controller:
VLSI video controller which retrieves data from the alpha RAM and provides display signals needed to generate the alpha dot stream.
8. Character ROM:
16K x 8 ROM which contains template for each alpha character. The ROM contains eight character sets. Each set contains 128 characters.
9. Alpha character display hardware:
This hardware uses information from alpha RAM and the character ROM along with signals from the SHC 9007 and generates the alpha dot character stream.
This stream does not include any enhan~ement information.
10. Enhancement decoding logic:
This hardware decodes the enhancement information. It produces signals used by the mixing hardware.
11. Dot stream mixing hardware:
Mixes the alpha and graphics dot streams with the enhancement information to obtain the signals NFB and NHB which are sent to the sweep.
12. Clock generation:
Produces various clock signals which are used by the other sections of the board.
The following discussion outlines the events which must take place to obtain the video dot stream and other signals sent to the sweep. It also highlights the key points of implementation.
To obtain an alpha dot stream the following happens:
1. The 8088 writes control information to the SHC 9007 to initialize the controller. This establishes the VSYNC and HSYNC signals sent to the sweep as well as the other control signals produced by the SHC 9007.
2. The 8088 writes the characters and enhancements to be displayed to the alpha RAM along with information needed by the SHC 9007 to retrieve the characters.
3. SHC 9007 retrieves data from the alpha RAM and latches it into discrete TTL latches.
4.
This data is used to address the character ROM and generate the enhancements associated with the character.5. The dot stream generated from the character ROM infonnation and the enhancement information is combined to form the alpha dot stream.
NOTES: 1. Accesses to the SHC 9007 and the alpha RAM by the 8088 are synchronized to the SHC 9007 character clock. Also accesses by the SHC 9007 to the alpha RAM are synchronized to the character clock.
2. 8088 and SHC 9007 alpha RAM accesses are time multiplexed within the character clock. In other words, part of the character clock is alloted to 8088 accesses and part is alloted to the SHC 9007.
Hardware Subsystems
To obtain the graphics display:
1. The 8088 writes information to be displayed into graphics RAM.
2. The Graphics Display Controller Chip retrieves the information and forms the graphics dot stream.
NOTES: 1. The signal which initializes the Graphics Display Controller Chip is derived from signals generated by the SHC 9007. This means that the SHC 9007 must be initialized before the graphics display is enabled or the graphics RAM is accessed.
2. Accesses to the graphics RAM by the 8088 and the Graphics display controller are syncronized to the graphics dot clock. The accesses are also time multiplexed wi thin each graphics cycle, where one graphics cycle is 16 graphics dot clocks in length.
To obtain the sweep signals:
1. The alpha and graphics dot streams are combined using combinatorial logic.
This logic produces the NFB and NBB signals which are sent to the sweep.
2. The NHSYNC and NVSYNC signals are produced by the SHC 9007 and are buffered before being sent to the sweep.
Notes on clock generation:
1. The 8 MHz system clock is used by the request and wait generation circuitry to aid in sychronizig the 8088 RAM accesses to the video clocks.
2. All clocks on the video board are derived from a 25.7715 MHz crystal.
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Hardware Subsystems