Value Representation

This architecture defines numeric and nonnumeric values representable within each of the two supported formats. The numeric values are approximations to the real numbers and include the normalized numbers, denormalized numbers, and zero values. The nonnumeric values repre-sentable are the infinities and the Not a Numbers (NaNs). The infinities are adjoined to the real numbers, but are not numbers themselves, and the standard rules of arithmetic do not hold when they are used in an operation. They are related to the real numbers by order alone. It is possi-ble, however, to define restricted operations among numbers and infini-ties as defined below. The relative location on the real number line for each of the defined entities is shown in Figure 29.

-INF

• I

^-NOR

I

^-DEN

^1-0 I

^+O

I

^+DEN

I

^+NOR

I

Figure 29. Approximation to real numbers

+INF

The NaNs are not related to the numeric values or infinities by order or value but are encodings used to convey diagnostic information such as the representation of uninitialized variables.

The following is a description of the different floating-point values defined in the architecture:

Binary floating-point numbers

Machine representable values used as approximations to real numbers.

Three categories of numbers are supported: normalized numbers, denor-malized numbers, and zero values.

Normalized numbers (±NOR)

These are values that have a biased exponent value in the range:

1 to 254 in single format 1 to 2046 in double format

They are values in which the implied unit bit is 1. Normalized num-bers are interpreted as follows:

NUK = (-1)" x 2E x (1.fraction)

where s is the sign, E is the unbiased exponent, and 1.fraction is the sig-nificand, which is composed of a leading unit bit (implied bit) and a frac-tion part.

The ranges covered by the magnitude (M) of a normalized floating-point number are approximately equal to:

Single Format:

1.2x10-38 ::;; M::;; 3.4xl038 Double Format:

2.2x10-308 ::;; M ::;; 1.8xl0308 Zero values (± 0)

These are values that have a biased exponent value of zero and a fraction value of zero. Zeros can have a positive or negative sign. The sign of zero is ignored by comparison operations (i.e., comparison regards +O as equal to -0).

Denormalized numbers (±DEN)

These are values that have a biased exponent value of zero and ,a nonzero fraction value. They are nonzero numbers smaller in magnitude than the representable normalized numbers. They are values in which the implied unit bit is 0. Denormalized numbers are interpreted as follows:

DEN= (-1)⁸ x 2Emin x (O.fraction)

where Emin is the minimum representable exponent value (-126 for sin-gle-precision, -1022 for double-precision).

Infinities ^{(± oo )}

These are values that have the maximum biased exponent value:

255 in the single format 204 7 in the double format

and a zero fraction value. They are used to approximate values greater in magnitude than the maximum normalized value.

Infinity arithmetic is defined as the limiting case of real arithmetic, with restricted operations defined among numbers and infinities. Infinities and the real numbers can be related by ordering in the affine sense:

-oo < every finite number < +oo

Arithmetic on infinities is always exact and does not signal any excep-tion, except when an exception occurs due to the invalid operations as described in Section 4.4.1, "Invalid Operation Exception," on page 155.

Not a Numbers (NaNs)

These are values that have the maximum biased exponent value and a nonzero fraction value. The sign bit is ignored (i.e., NaNs are neither pos-itive nor negative). If the high-order bit of the fraction field is 0 then the NaN is a Signalling NaN; otherwise it is a Quiet NaN.

Signalling NaNs are used to signal exceptions when they appear as operands of computational instructions.

Quiet NaNs are used to represent the results of certain invalid opera-tions, such as invalid arithmetic operations on infinities or on NaNs, when Invalid Operation Exception is disabled (FPSCRVE=O). Quiet NaNs propagate through all floating-point operations except ordered compari-son, Floating Round to Single-Precision, and conversion to integer. Quiet NaNs do not signal exceptions, except for ordered comparison and con-version to integer operations. Specific encodings in QNaNs can thus be preserved through a sequence of floating-point operations, and used to convey diagnostic information to help identify results from invalid opera-tions.

When a QNaN is the result of a floating-point operation because one of the operands is a NaN or because a QNaN was generated due to a dis-abled Invalid Operation Exception, then the following rule is applied to determine the NaN with the high-order fraction bit set to 1 that is to be stored as the result.

if (FRA) is a NaN then FRT ~ (FRA) else if (FRB) is a NaN

then if instruction is frsp then FRT ~ (FRB)o:34

II

²⁹0 else FRT ~ (FRB)

else if (FRC) is a NaN then FRT ~ (FRC) else if generated QNaN

then FRT ~generated QNaN

If the operand specified by FRA is a NaN, then that NaN is stored as the result. Otherwise, if the operand specified by FRB is a NaN (if the instruction specifies an FRB operand), then that NaN is stored as the

result, with the low-order 29 bits of the result set to 0 if the instruction is

frsp.

Otherwise, if the operand specified by FRC is a NaN (if the instruc-tion speclfie~ ~n FR_C 0pe!."~!!d}, th~~ tha~ ~~a~~ i~ ~iu1cJ. as [he resuir.

Otherwise, if a QNaN was generated due to a disabled Invalid Operation Exception, then that QNaN is stored as the result. If a QNaN is to be generated as a result, then the QNaN generated has a sign bit of 0, an exponent field of all ls, and a high-order fraction bit of 1 with all other fraction bits 0. Any instruction that generates a QNaN as the result of a disabled Invalid Operation must generate this QNaN (i.e., Ox7FF8_0000_0000_0000).

A double-precision NaN is considered to be representable in single format if and only if the low-order 29 bits of the double-precision NaN's fraction are zero.

Dans le document BUSl, ~ESS (Page 178-181)