Floating-Point Status and Control Register

The Floating-Point Status and Control Register (FPSCR) controls the handling of floating-point exceptions and records status resulting from the floating-point operations. Bits 0:23 are status bits. Bits 24:31 are con-trol bits.

The exception bits in the FPSCR (bits 0:12, 21:23) are sticky, with the exception of Floating-Point Enabled Exception Summary (FEX) and Floating-Point Invalid Operation Exception Summary (VX). That is, once set, the sticky bits remain set until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsbO instruction.

FEX and VX are simply the ORs of other FPSCR bits. Therefore these two bits are not listed among the FPSCR bits affected by the various instructions.

FPCSR

0 31

Figure 24. Floating-Point Status and Control Register

The format of the FPSCR is:

Bit(s) Description

0 Floating-Point Exception Summary (FX)

Every floating-point instruction, except mtfsfi and mtfsf, implicitly sets FPSCRpx to 1 if that instruction causes any of the floating-point exception bits in the FPSCR to change from 0 to 1. mcrfs, mtfsfi, mtfsf, mtfsbO, and mtfsb1 can alter FPSCRpx explicitly.

1 Floating-Point Enabled Exception Summary (FEX)

This bit indicates whether any enabled exceptions have occurred.

It is the OR of all the floating-point exception bits masked by their respective enable bits. mcrfs, mtfsfi, mtfsf, mtfsbO, and mtfsb1 can-not alter FPSCRFEX explicitly.

2 Floating-Point Invalid Operation Exception Summary (VX) This bit indicates whether any invalid operation exceptions have occurred. It is the OR of all the Invalid Operation exception bits.

mcrfs, mtfsfi, mtfsf, mtfsbO, and mtfsb1 cannot alter FPSCRvx ex-plicitly.

3 Floating-Point Overfiow Exception (OX)

See Section 4.4.3, "Overflow Exception," on page 159.

4 Floating-Point Underfiow Exception (UX)

See Section 4.4.4, "Underflow Exception," on page 160.

5 Floating-Point Zero Divide Exception (ZX)

See Section 4.4.2, "Zero Divide Exception," on page 158.

6 Floating-Point Inexact Exception (XX)

See Section 4.4.5, "Inexact Exception," on page 162.

FPSCRxx is a sticky version of FPSCRFI (see below). Thus the following rules completely describe how FPSCRxx is set by a given instruction.

• If the instruction affects FPSCRpr, the new value of FPSCRxx is obtained by ORing the old value of FPSCRxx with the new value of FPSCRFI.

• If the instruction does not affect FPSCRFI, the value of FPSCRxx is unchanged.

7 Floating-Point Invalid Operation Exception (SNaN) (VXSNAN) See Section 4.4.1, "Invalid Operation Exception," on page 155.

8 Floating-Point Invalid Operation Exception (oo - oo) (VXISI) See Section 4.4.1, "Invalid Operation Exception," on page 155.

9 Floating-Point Invalid Operation Exception (oo + oo) (VXIDI) See Section 4.4.1, "Invalid Operation Exception," on page 155.

10 Floating-Point Invalid Operation Exception (0 + 0) (VXZDZ) See Section 4.4.1, "Invalid Operation Exception," on page 155.

11 Floating-Point Invalid Operation Exception (oo x 0) (VXIMZ) See Section 4.4.1, "Invalid Operation Exception," on page 155.

12 Floating-Point Invalid Operation Exception (Invalid Compare) (VXVC)

See Section 4.4.1, "Invalid Operation Exception," on page 155.

13 Floating-Point Fraction Rounded (FR)

The last Arithmetic or Rounding and Conversion instruction that rounded the intermediate result incremented the fraction. See Sec-tion 4.3.6, "Rounding," on page 149. This bit is not sticky.

14 Floating-Point Fraction Inexact (FI)

The last Arithmetic or Rounding and Conversion instruction either rounded the intermediate result (producing an inexact fraction) or

caused a disabled Overflow Exception. See Section 4.3.6, "Round-ing," on page 14 9. This bit is not sticky.

See the definition of FPSCRxx, above, regarding the relationship between FPSCRp1 and FPSCRxx·

15:19 Floating-Point Result Flags (FPRF)

This field is set as described below. For arithmetic, rounding, and conversion instructions, the field is set based on the result placed into the target register, except that if any portion of the result is un-defined then the value placed into FPRF is unun-defined.

15 Floating-Point Result Class Descriptor (C)

Arithmetic, rounding, and conversion instructions may set this bit with the FPCC bits, to indicate the class of the result as shown in Figure 25 on page 140.

16:19 Floating-Point Condition Code (FPCC)

Floating-point Compare instructions set one of the FPCC bits to 1 and the other three FPCC bits to 0. Arithmetic, rounding, and con-version instructions may set the FPCC bits with the C bit, to indi-cate the class of the result as shown in Figure 25 on page 140. Note that in this case the high-order three bits of the FPCC retain their relational significance indicating that the value is less than, greater than, or equal to zero.

16 Floating-Point Less Than or Negative (FL or<) 17 Floating-Point Greater Than or Positive (FG or >) 18 Floating-Point Equal or Zero (FE or=)

19 Floating-Point Unordered or NaN (FU or?) 20 Reserved

21 Floating-Point Invalid Operation Exception (Software Request) (VXSOFT)

22

23

This bit can be altered only by mcrfs, mtfsfi, mtfsf, mtfsbO, or mtfsb1. See Section 4.4.1, "Invalid Operation Exception," on page 155.

Floating-Point Invalid Operation Exception (Invalid Square Root) (VXSQRT)

See Section 4.4.1, "Invalid Operation Exception," on page 155.

Floating-Point Invalid Operation Exception (Invalid Integer Convert) (VXCVI)

Programming Note If the implementation does not support the Floating Square Root instruction or the Floating Reciprocal Square Root Estimate instruction, software can simulate the instruction and set FPSCRvxSQRT to

Result Flags

--

--c

1 0 0 0 1 Quiet NaN

0 1 0 0 1 -Infinity

0 1 0 0 0 -Normalized Number

1 1 0 0 0 -Denormalized Number

1 0 0 1 0 -Zero

0 0 0 1 0 +Zero

1 0 1 0 0 +Denormalized Number

0 0 1 0 0 +Normalized Number

0 0 1 0 1 +Infinity

Figure 25. Floating-Point Result Flags

24 Floating-Point Invalid Operation Exception Enable (VE) See Section 4.4.1, "Invalid Operation Exception," on page 155.

25 Floating-Point Overflow Exception Enable (OE) See Section 4.4.3, "Overflow Exception," on page 159.

26 Floating-Point Underflow Exception Enable (UE) See Section 4.4.4, "Underflow Exception," on page 160.

27 Floating-Point Zero Divide Exception Enable (ZE) See Section 4.4.2, "Zero Divide Exception," on page 158.

28 Floating-Point Inexact Exception Enable (XE) See Section 4.4.5, "Inexact Exception," on page 162.

29 Floating-Point Non-IEEE Mode (NI)

If this bit is set to 1, the remaining FPSCR bits may have meanings other than those given in this document, and the results of floating-point operations need not conform to the IEEE standard. If the IEEE-conforming result of a floating-point operation would be a denormalized number, the result of that operation is 0 (with the same sign as the denormalized number) if FPSCRNr=l and other requirements specified in the Book IV, PowerPC Implementation

Features for the implementation are met. The other effects of set-ting this bit to 1 are described in Book IV and may differ between implementations.

30:31 Floating-Point Rounding Control (RN) See Section 4.3.6, "Rounding," on page 149.

00 Round to Nearest 01 Round toward Zero 10 Round toward +Infinity 11 Round toward -Infinity