RESET BY CLEAR

Figure 3-22. P-Register Inputs and Enabling Signals

901 1 72 A. 68

SDS 901172

DIO-REGISTER (DIOO/1-DI047/1). The DIO-register holds di rect input or output data and addresses duri ng read direct and write direct instruction execution. Flip-fiops DlOO/l through DI031/1 contai n the data, and are loaded from the direct input/output lines during read direct opera-ti on and from the sum bus during write direct operaopera-tion.

Flip-flops DI032/1 through DI047/1 contain the address and are loaded from the B-register. The data outputs of the DIO-register are gated onto the sum bus during read direct operation and onto the direct input/output lines duri ng wri te di rect operati on.

The inputs to the DIO-register and their enabling signals are shown in figure 3-23.

Me-REGISTER (MCa-MC7). The Me-register, or macro-counter, is used to keep track of the number of words for multiple-word instructions, the number of shifts for shift instructions, and the number of iterations for multiplication and division instructions. The counter is decremented by one each time the count is to be changed.

The macro-counter is loaded from the P-regi ster during shi ft instructions, from the condition code register during stack and multiple instructions, and from the sum bus during the

move to memory control i nstructi on. The outputs of the counter are transferred to the A-register or are applied directiy in control equotium.

The inputs to the macro-counter and their enabling signals are shown in fi gure 3 -24 •

CONDITION CODE FLIP-FLOPS (CC1-CC4). The con-dition code flip-flops are part of the program status doubleword, occupyi ng bi t posi tions 0 through 3 of PSW1.

These flip-flops are used as a 4-bit register in some opera-tions. In other operations the flip-flops store bits repre-senting the results of certain calculations. Only the register function will be discussed in this section.

During read and write direct internal mode operati on, the condition code flip-flops are used to store the states of the four processor control panel sense switches, KSSl through KSS4. When a trap occurs during program status double-word operati on, the CC

fI

ip-f1ops store the contents of the trap accumulator register, TRACCi through iRACC4. Dur-ing interpret and program status doubleword operation, bits a through

3

of the sum bus are loaded into the condition code flip-flops, and during the load conditions and floating control instruction, 524 through 527 are loaded into CCl through CC4.

50-531 (SUM BUS) I

DIOXS

DIOO-DI031 (DIRECT I/O LINES) I

DIOXDlO DIO-REGISTER (DATA)

DIOX

I

ZEROS

B 18- B31 (B- REGISTER) I

DIOXB

DlO-REGISTER (ADDRESS)

DlOXB

I

ZEROS

Figure 3-23. DIO-Register Inputs and Enabling Signals

901172A.69

SO-57 (SUM BUS) I MCXS

DOWNCOUNT SET INPUTS

I ,

jr--M-C ... D-C-3---,' jr---M

-C"-D-C-7---"

CCZ, CC1-CC4 (CONDITION CODE) I

AXCC

NP26-NP30 (P-REGISTER), FUSF NP31, FUSF

I

MCXNPL1 P26-P31 {P-REGISTER}

,

r-\---FADIV PRE3 r--FAMULNH PRE3

-FUMH PRE3

(SjMC7)

=

MACRO-COUNTER 011121314151617

MCX

I

ZEROS

I MCDC3 ^{I I} MCDC7 ^I

I I

DOWNCOUNT RESET INPUTS

FAST PRE3 N06

901172A.70

Figure 3-24. Macro-Counter Inputs and Enabling Signals The inputs to the condition code flip-flops when used as a register are shown with their enabling signals in figure 3-25.

ADDER. The adder performs the basic arithmetic and logic operati ons of the computer. All adder inputs are taken from the A- and D-registers, and the sum bus, SO through S31, is the common output for all of the results obtained in the adder.

The operations performed in the adder are listed in table 3-1. The gati ng terms at the top of the table are used to develop the generate and propagate signals used for parallel addition and subtraction. The enabling signals are the results of instruction decoding and are used to form the gating terms.

In parallel addition, all the bits of both arguments enter the adder at once, and all the bits of the sum or difference are formed at once. Typical addition logic is shown in figure 3-26:, usi ng bits 27 through 31 as an example. The generate terms, G

rt

the propagate terms, PRn' and the sum bits, Sn' are formed as follows:

A f.j:\ D

n\..!.l n

The outputs to the sum bus are gated by enabling term SXADD. The carry terms, Kn, are generated as shown in the figure.

The arrowheads pointing to each K term block represent an OR gate whose output is the appropriate carry term. Each continuous line, touching the

K

and

PR

term biocks, repre-sents an AND gate containing the terms touched by the line and with its output at the arrowhead. From each group of four adder stages a hi gher order carry, represented in the figure by K27, is developed, and this term is used as the carry into the next group of four stages. The truth table for the A plus D operation is shown in table 3-2.

In the A minus D operation, the generate and propagate terms are developed as follows:

G _n PR _n

A ND

A D + NA ND

KSS1-KSS4 CCXRWD

I

I

TRACC 1- TRACC4 I

S24-S27 I

CCXSj3

SO-S3

I

CCXSjO

CC FLIP-FLOPS

1

J

2 1314

R/CC

I

ZEROS 901172A. 71

Figure 3-25. Condition Code Flip-Flop Register Inputs and Enabling Signals

LI 23 A-REGISTER 0

D-REGISTER 1

~

^G28

I::lI

^G28-G31

^I

I P~7 I ^I

^K27

^{1 I} P~8

I I I 1 I II

~\v'---.~....--J

PR28-PR31 I

SUM

o

I

SOS 901172

29 ^'m

0 0

0 1

G29 G30

0 0

K30

o o

Figure 3-26. A Plus D Adder Logic

Table 3-1. Adder Operations

GATING TERM

OPERA TION ENABLING SIGNAL PRXAD PRXAND PRXNAD PRXNAND GXAD

AD A ND NA D NA ND AD

A+D S/SXAPD X X X

A+D+l

*

X X X

A-D S/SXAMD X X

A-D-l t X X

D-A S/SXDMA X X

D-A-l S/SXDMAMl X X

AnD S/PRXAD X

NAnD S/PRXNAD X

AnND S/PRXAND X

AnD S/SXAORD X X X

AGD S/SXAEORD X X

A S/SXA X X

D S/SXD X X

I I

NA S/SXNA X X

(Conti nued)

31

G31

flfl

^I

_/\;\/\/\

^{I I}

_{)) ) }}

^{I 1\}

o

901172A.

n

GXAND GXNAD K31

AND NA D

X

X X

X

X X

V r,

I

Table 3-1. Adder Operations (Cont.)

f---.

Dans le document SIGMA 5 (Page 75-79)