REGISTER LOGIC CARD, A3 (Refer To Figure 3.14.)

Delay Line Register, DLR (Refer to Dwg. 2144558 Sht. 2.)

The DLR is an eleven stage shift register, the contents of which are parallel transferred to the Display Register (DR). The function of the DLR is to act as the input register for the Delay Line Memory, A7. During normal recirculation of stored data, the Delay Line Memory output is amplified, shaped, stretched, and applied to the input stage of the DLR. After being parallel shifted into the DR, the character bits are again serially shifted back into the Delay Line Memory.

3-21

Display Register, DR (Refer to Dwg. 2144558 Sht. 2.)

The DR functions as a storage buffer between the DLR and the Selection Amplifier, A8. This allows storage of each character for one full character time (13.02 microseconds) in the DR while the next character's bits are being serially shifted out of the delay line and into the DLR, and the previous character's bits are being shifted back into the delay line for recirculation. During this storage time, the character bits stored in the. DR are applied to the Selection Amplifier, A8, and D/A converters which convert the X and Y deflection bits into equivalent gross positioning voltages for selection of the proper character on the monoscope

character stencil.

The Display Register also has a set of input AND gates connected to the set ter-minal of the seven flip-flops (DR1 through DR7), which are used to enter the seven character bits from the keyboard microswitches during keyboard entry.

Delay Line Register Entry Circuit (Refer to Dwg. 2144558 Sht. 2.)

The delay line entry circuit, located on card A3, consists of an inverter-ampli-fier 58C1A, the DELAY LINE STRETCH (DLS) flip-flop, and the DELAY LINE REGISTER INPUT flip-flop (DLRIN) (Figure 3-3).

The DLR entry circuit receives the 225 nanosecond output of the keyboard filter one shot, which is the amplified Delay Line Memory output DLOUT-P. The DELAY LINE STRETCH flip-flop (DLS) stretches the one shot signal and applies i t to the DELAY LINE REGISTER INPUT flip-flop (DLRIN). The TBB clock pulse controls the shifting of the data into the DLR.

Keyboard Parity Generator (Refer to Dwg. 2144558 Sht. 1.)

The PARITY GENERATOR flip-flop (KBP) monitors the output of the Display Register stage CR1. When a character has been entered into the DR from the keyboard micro-switches, the character bits are serially shifted to the Delay Line Memory input circuits through gate 58C6B. During the transfer of the character bits, the out-put of the KEYBOARD PARITY GENERATOR flip-flop is ANDed with BT8B-P. When the number of "l's" counted by the KBP flip-flop is an odd number, the AND circuit enters an additional "I" bit into the delay line input circuit to make the total character "1" bit count an even number.

Keyboard Parity Checker (Refer to Dwg. 2144558.)

When the character bits exit the delay line and enter the DL~ the parity count (number of "1" bits) is monitored by the DISPLAY PARITY CHECK flip-flop, DPC (58A8A). When the DPC flip-flop parity count ("l's") is an even number, the character in the DR is displayed. When the parity count ("l's") detected by the DPC is an odd number, the logic causes a bright square block to be displayed in place of the faulty character.

Normal Recirculation of Stored Data

Figure 3-14 shows the normal recirculation path of data stored in the Delay Line Memory. Stored character bits are shifted serially into the Delay Line Register from the Delay Line Memory, through a 225 nanosecond one shot pulse shaper, located in the keyboard filter (A21), and through the DLR input circuit, located on card A3.

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L _______________________________________ J ~ ________________________________________ ~

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TBB serial shifts the DLR every 1.302 microseconds; therefore the bit rate is 768,000 bits per second. When a character is shifted into the DLR, the least significant bit is the first to shift from the delay line into DLRMN (Mark Now) flip-flop. The first bit per character is shifted in at BT1B. At BT~OB the complete ten bit character is in the DLR. The least significant ASCII character bit is in DLR1 and the most significant bit is in DLR7. The parity bit is in DLRP, and the mark bit is in DLRMN. The format bit will be set to "1" in DLRF only for a format character.

Parallel Shift of Data From DLR to DR

The parallel shift is enabled by DLR ENABLE (DLREN) from 58C8B. The DLREN signal is present at time BT1A·BT10B, during the second 651 nanoseconds of dT10B. During this gating period the DLR contents are enabled through AND gates to set the character bits into the Display Register where they are held for one character period, or 13.02 microseconds. The serial shift of the DLR is continuous; the character shifts out of the DLR into the delay line input for memory recirculation.

The next character from the delay line is similarly shifted into the DLR.

Delay Line Memory Entry Circuit (Refer to

Dwg.

The delay line entry circuit consists of an OR gate (58B6A and B) through which data is routed from six sources and stored in the Delay Line Memory, A7

(Figure 3-15).

DTDLM Generation

To standardize the input signal to the delay line memory, all input signals are routed from the delay line entry OR circuit to the AND circuit 58B6C, where the input signal is ANDED with the 768 KHz square wave and the output of the 130 nanosecond delay line (DL1). The AND circuit generates a standardized pulse 521 nanoseconds wide and delayed 130 nanoseconds from the leading edge of the TBA pulse. This standardized pulse is DISPLAY TO DELAY LINE MEMORY (DTDLM-P), which is the "1" bit entered into the Delay Line Memory for each "1" bit of data to be stored.

Normal Recirculation

The normal recirculation path from the Delay Line Register (DLR) output stage is routed to the OR circuit (through other gating logic) to pin 4 of 58B6B. During normal recirculation, all data displayed is recirculated at a 60 Hz rate to con-stantly refresh the viewer screen phosphor.

Keyboard Entry

When the operator selects a new character at the VDT Keyboard, the character bits are entered into the Display Register, and serially shifted from the DR output stage (DR1-P) through gating logic to the OR circuit input at 58B6B pin 2.

PARITY G E N E R A T I O N . . . r ' -KEYBOARD ENTRY - - - - ( : l

REMOTE DATA FROM PROCESSOR

SYNC PULSE ENTRY

10/7&2-01111

Remote Data Entry

768 KHz _---I

SEMC'--~

58B6C Z39

58B7A Z45

~_~D~TD~LM~-~P_~70

DL1 130 n Sec.

'---651 n s e c . - I :

-58B6C-5 768 KHz ___

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I I

I I

1130nl-- I

58B6C-4 DELAYED ~ ^Sec. I

768 KHz I I

I I

I I

_ _ _ _ ... L521 n sec.-I

58B6D-8 DTDLM-P

! .... _________ _

figure 3-U. Delay Line Entry, Block Diagram

When data is being received from the Basic Processor Unit, whether it is remotely located or at the local installation, the received data is routed from the Input-Output Registers (in units Al and A2) through gating logic by the BUFFER TO DISPLAY signal (BTD) and applied to the OR circuit at 58B6B pin 1.

3-26

Note

The received data is shifted into the I/O registers at the 1200 bit rate of the Data Set and shifted out of the I/O registers at the 768 KHz rate of the delay U.'1e.