The Bit Counter is a self-correcting type in that on initial start-up the states of the counter are not determinable but after a few counts the reset will correct the count. For example, when the BCNT4 and BCNT5 flip-flops contain the "O:!."
count, the BCNT1 and BCNT2 flip-flops are reset. In one case the count could be
"00101". The next counts then would be 00010 and 10001: then the first two stages would again be reset to provide the counter state of 00001. The counter would then proceed to count as shown in Figure 3-8.
Bit Time Decoding
The "A" bit times (BT1A-BT10A) are formed by ANDing the BIT COUNTER flip-flop outputs to decode the desired counts.
The output of the "B" BIT COUNT flip-flop is applied to AND logic along with the outputs of the Bit Counter to produce the bit times BT1B thru BT10B. The "B"
BIT COUNT flip-flop (BBCNT) is triggered by the second timing clock, TBB-N, which occurs 651 nanoseconds later than TBA. The "B" bit times trail the "A"
bit times by 651 nanoseconds, as shown in Figure 3-9. Note that many of the bit times are not decoded.
Character Counter, CHC1-CHC6 (Refer to Dwg. 2144556 Sheet 2.)
The Character Counter, located on the A5 board, is a standard six stage binary counter with 64 counts. Each count corresponds to one of the 64 character posi-tions on one line of the viewer 20 line raster. The Character Counter is trig-gered by CHARACTER COUNT TRIGGER, CHCT (56B7A-SH3), which occurs· once each char-acter time. The Character Counter outputs in conunction with the Line Counter outputs generate the following signals (Figure 3-10):
BOL = Beginning-of-Line EOL End-of-Line
BOP
=
Beginning-of-Page IOBP=
I/O Beginning-of-Page COEOP=
Center-or-end-of-page EOP=
End-of-PageV SYNC
=
Vertical SYNC .H SYNC=
Horizontal SYNCFor example, the logic decodes character count 55, and this count is ANDed with BT10B to produce the END-OF-LINE (EOL) pulse, which triggers the Line Counter.
1'4
DATA DISPLAY TIMEfigure 3-10. C"aracter Counter Timing
Line Counter, LC1-LC5 (Refer to Dwg. 2144556 Sht. 2.>
1 2 3 4 5 6 7 8 910111213141516171819202122232425262728293031323334353637.'£394041424344
LC3(P)~1 I I 11 00
oo~ ru u J
u-LC4(P)~1 I I I I I I 110 01
U U U
-LC5(P)1o 00 0 0 o 000 01
L
I ..
I PAGE TIME.1
figure 3· JJ • Line Counter Timing
3.4.3 DELAY LINE MEMORY, A7
The Delay Line Memory unit used in the 70/752 VDT is manufactured by two ve~dors.
The first type is manufactured by Laboratory for Electronics, Inc. (Figure 3-12.) The second type is the unit manufactured by Digital Devices, Inc. (Figure 3-13.) The theory of operation of each type is covered in the following paragraphs.
Laboratory For Electronics Delay Line Memory
The Delay Line is a magnetostrictive type with a delay time of 16,703 ±27 micro-seconds. This storage time provides storage of one complete page of information
(1080 characters, each 13.02 microseconds in duration, plus 200 character times utilized as flyback time, for a total of 1280 character times). Since each char-acter contains ten bits of data of 1.302 microseconds duration each, the Delay Line can contain 12,800 data bits in addition to a start character (sync bits), and several NUL (all zero) characters.
The data inserted into the Delay Line is in the return-to-zero format; that is, a "1" bit is applied to the delay line as a positive pulse while a "0" bit re-quires no pulse at all. The total length of the Delay Line varies with tempera-ture and affects the total Delay Line storage time. The variance in the delay time makes it necessary to resync the timing at the end of each displayed page.
This resync cycle is controlled by the WAIT-HOLD-START logic, which is explained in paragraph 3.3.4.
The magnetostrictive Delay Line consists of a metal wire, about 160 feet long.
The input transducer, on one end of the delay wire, launches a torsional wave into the wire. This wave propagates in the wire with a velocity of about 100 microseconds per foot. At the other end of the wire, the output transducer
translates the torsional wave into an electric signal. With an output current of about 30 milliamps, the output voltage will be about two millivolts. Because of the small output signal an amplifier is provided. The amplifier output signal is reshaped in the detector and will then resemble the input signal. The driver provides the current to the Delay Line input transducer.
Circuit Description (Refer to Figure 3-l2.)
The electrical portion of the Delay Line Memory is divided into three parts:
the driver, the amplifier, and the detector.
The input signal turns on 01 enabling current flow through the input transducer.
This current is limited by R3, a resistor inside the Delay Line. When 01 turns off, the storage energy in the transducer is absorbed through CR2 by R3. If no input signal. is connected, CRl limits the negative base-emitter voltage of 01.
The output amplifier consists of three stages (03, 04, and 05) providing a gain of about 76 db. An emitter follower 02 is provided to make the delay output termination less dependent on the input impedance of the amplifier.
voltage line
The gain of the amplifier is, in part, determined by the signal developed in the ratio of collectors to emitter resistors of 03, 04, and 05. To provide a gain control, the emitter resistor (R15) of 05 is variable and can change the gain by about 6 db. Emitter follower Q6 isolates the detector from the amplifier and provides the signal for the test pOint. A test point at the amplifier output
allows observation of the signal-to-noise ratio and the signal amplitude.