Upon receiving an RWR frame addressed to this station, the TBC will store it into the appropriate receive queue and perform the following steps:
• The source address of the received frame is stored into the destination address field of the FD pointed to by the response destination address pointer. This pointer resides in the ini-tialization table at offset 84 and must have been previously initialized by the host to point to a valid FD.
• If the frame is not a retry, then the TBC loads the pointer to the received RWR frame's FD into the RWR pointer field located in the initialization table at offset 8C. The received RWR frame bit in interrupt status word
o
will then be set and an interrupt will be generated if enabled.A retry is defined as an RWR frame addressed to this TBC that arrives immediately after another RWR frame which was addressed to it. If another valid frame such as a protocol frame, a non-RWR data frame, or a data frame not addressed to this station arrives in between two non-RWR frames, then the second RWR frame is considered to be a new frame and not a retry.
The response is sent by the TBC according to the steps defined below:
• Ifthe TBC is in predefined response mode, set by the host through the SET MODE 1 command, then the pointer stored by the host in the response pointer field in the initialization table (offset 88) is considered valid, and the response is transmitted immediately after the token bus goes to silence. The TXRDF bit (transmitted response data frame) in interrupt status word
o
is also set and an interrupt is generated if enabled.MOTOROLA
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MC68824 USER'S MANUAL
• If the TBC is not in predefined response mode, then the TBC must wait for the command RESPONSE READY from the host before sending out the response. Before issuing the RE-SPONSE READY command, the host must prepare a response and update the response pointer field located in the initialization table (offset 88) if necessary. If this command is issued within two slot times, then the TBC will transmit the response prepared by the host.
However, if the host issues the command later than two slot times but before the TBC receives the next RWR retry frame, the TBC will still transmit the previously prepared response as a response to the current retry of the RWR frame. The TXRDF bit (transmitted response data frame) in !nterrupt status word 0 is also set and an interrupt is generated if enabled.
Note that if the host still owes a previous response to the TBC, the TBC will neither update the RWR pointer field nor change the status of RXRWR in interrupt'status word O.
The following four paragraphs describe the relationship between two of the pointers residing in
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the initialization table at offset 84 and 88 which are used to implement the RWR mechanism.
Case 1:
The TBC is in predefined response mode and the DA of the response frame must be identical to the SA of the received RWR frame.
• The response destination address pointer (offset 84) should have been previously set by the host to the same value as the response pointer (offset 88).
• The TBC will set DA equal to SA of received frame in the FD pointed to by the response destination address pointer (offset 84).
Case 2:
The TBC is in predefined response mode and the DA of the response frame must be different from the SA of the received RWR frame.
• The response destination address pointer (offset 84) should have been previously set by the host to point to a dummy FD.
• The response pointer (offset 88) should have been previously set by the host to point to the response frame's FD where the host has set DA as required.
Case 3:
The TBC is in non-predefined mode and the DA of the response frame must be identical to the SA of the received RWR frame.
• The response destination address pointer (offset 84) should have been previously set by the host to the same value as the response pointer (offset 88).
• The response pointer (offset 88) must be a constant, i.e., always point to the same FD.
• The TBC will set DA equal to SA of received frame in the FD pointed to by the response destination address pointer (offset 84).
Case 4:
The TBC is in non-predefined response mode and the DA of the response frame must be different from the SA of the received RWR frame.
• The response destination address pointer (offset 84) should be set by the host to point to a dummy FD.
• The response pointer (offset 88) is set by the host to point to the response frame's FD where the host has set DA as required upon getting the RXRWR interrupt (this bit could also be polled).
NOTE
Cases 2 and 4 describe operations which are inappropriate for IEEE 802.4.
MC68824 USER'S MANUAL MOTOROLA
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WARNING
The TBC may send a response to a previous RWR frame as a response to a new RWR frame in the following cases:
• If a second, new RWR frame arrives immediately after a RWR frame whose response was not ready within two slot times from its arrival (this new frame is considered to be a retry) .
• If the response from the host is issued to the TBC at the same time as a second RWR frame arrives, even if a non-RWR frame addressed to this station arrived previously. In this case, the RESPONSE READY command is executed only after complete reception of the RWR frame. Thus, the response is considered a valid response to the second request and will be transmitted. This scenario also can take place if the response was ready to be transmitted but, due to high load on the bus, the TBC was not able to execute the RESPONSE READY command prior to receiving the second RWR frame.
Note that in these cases, the host did not respond in time to the last retry of a RWR frame, while according to the 802.4 standard, the host should respond in time to the first one. Thus, these situations should not occur.
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SECTION 5 SIGNALS
This section contains a description of the input and output signals for the MC68824 Token Bus Controller.
NOTES
The terms assertion and negation will be used extensively. This is done to avoid con-fusion when dealing with a mixture of "active low" and "active high" signals. The term
"assert" or "assertion" is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term "negate" or "ne-gation" is used to indicate that a signal is inactive or false.
The TBC has two modes of bus operation, the master mode and the slave mode. In the master mode, the TBC has control of the address and data bus and is performing memory liD. In the slave mode, the TBC is acting as a peripheral and is being accessed by the host. Refer to 6.1 HOST PROCESSOR OPERATION MODE and 6.2 DMA OPERATION for further details.
Input and output signals are functionally organized into the groups shown in Figure 5-1. Each of these groups is discussed in the following paragraphs.