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The following patents were recently issued to Digital Equipment Corporation. Titles and names supplied by the U.S. Patent and Trademark Office are reproduced as they appear on the original published patent.
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Robert T. Faranda and Bradford G. Chapin
Hamid R. Soleimani, Brian Doyle, and Ara Philipossian
Richard I. Mellitz and Michael V. Dowd
Henry S. Yang, Donald L. Post, and Wcn-Yi Huang
Philippe Klein, David W. Maruska, and Kevin W. Ludlam
David B. Lomet
Ricky S. Palmer and Larry G. Palmer Robert R. K'lndo and Paul L. Goctin
Janos Farkas, Rahul Ja.irath, Matt SteU, and Sing-Mo Tzeng
Ani! K Jain, John H. Edmondson, and Peter J. Ba1mon
Dale R. Doncbin Steven M. Jenness
Vincent G. Gavin, Michael J. Seaman, Neal A. Crook, and Bipin Misu-y
David B . Krakauer, Ka.izad Mistry, Steven Butler, and Hamid Partovi
Cuneyt M. Ozveren, Hallam
G.
Murray, Jr., Gregory M. Waters, and Robert J. Simcoe Ram Sudama, David M. Griffin,Brad Johnson, Dexter Sealy,
James Shelhamer, and Owen H. Tallman
Simon C. Steely, Jr. , David J. Sager, and David B. Fire, Jr.
Robert L. Travis, Jr., Andrew P. Wilson, Neal F. Jacobson, and Michael J. Renzullo 76 Digital Technical Journal Vol . 9 No. 4 1 997
Notebook personal computer
Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation
Continuous motion electrical circuit intercormect test method and apparatus
Automatic network speed adapter
Method and apparan1s for testing high speed busses using gray-code data
Method for performing private lock management Video teleconferencing for networked workstations Adapter for intercoimecting single-ended and differen
tial SCSI buses to prevent 'busy' or 'wired-or' glitches from being passed from one bus to the other
Method of using additives witl1 silica-based slurries to enhance selectivity in metal CMP
Method for increasing system bandwidtl1 through an on-chip add ress lock register
Pattern recognition device
Object oriented computer architecture using ctirectory objects
Data transfer system for buffering and selectively manipu lating the size of data blocks being transferred between a processor and a system bus of a computer system
Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps
Flow control witl1 smootl1 limit setting for multiple virtual circuits
Method for providing a security facility for a network of management servers utilizing a database of trust relations to verifY mutual trust relations between management servers
Memory reference tagging
Method and apparatus for object-oriented invocation of a server application by a client application
5,621 ,678
Michael J. Barnaby and James W. Brissette
Bruce E. Mann, Darrell J . Duffy, Anthony G. Lauck, and
William D. Su·ecker
Peter Lucas and Jeffrey A. Senn Larry G. Palmer and Ricky S. Palmer
Hoe T. Cho, Maw
Z.
Jau, and W. H ugh DurdanDavid M. Fenwick, Daniel Wissel!, Richard Watson, and Denis Foley Bevin R. Brett
Gilbert M. Wolrich, Timothy C. Fischer, and John A. Kowaleski, Jr.
Joseph H. Brown and Dilip K. Bhavsar
Michael C. Adler, Steven 0. Hobbs, and Paul G. Lowney
William R. Hamburgen, John S. Fitch, and Norman P. Jouppi
Nitin D. Godiwala, Kurt M. Thaller, Jeffrey A. Metzger, and Barry A. Maskas Wayne M. Cardoza, Jeffrey M. Diewald, Jeffrey E. Nelson, Steven D. DiPirro, James R. Goddard, Wendell B. Fisher, Jr. , Anne E . McElearney, and Richard Sayde Peter J. Bannon, Ruben vV. Castelino, and Chandrasekhara Somanathan David A. Orbits, Kenneth D . Abramson, and H. Bruce Butts, Jr.
Rodney Gamache, Stuart Farnham, Michael Harvey, William A. Laing, Kathleen Morse, and Michael Uhler James B. Saxe
Michael Ben-Nun, Simoni Ben-Michael, Simcha Perl, and Kadangode K.
Ramakrishnan
Scott G. Robinson, Richard L. Sites, and Richard T. Witek
William F. McCarthy, Colin E. Brench, and Daniel M . Snow
Programmable memory controller for power and noise reduction
Local area network with server and virtual circuits
Three dimensional document representation using strands
Audio/video storage and retrieval for multimedia work
stations by interleaving audio and video data in data file Apparatus and method for adapting a computer system to different architectures
Clock architecture for synchronous system bus which regulates and adjusts clock skew
Using sorting to do match up in smart recompilation Floating point unit data path alignment
Architecture for system-wide standardized intra-module and inter-module fault testing
Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination High powered die with bus bars
Fault management scheme for a cache memory
Method and apparatus for testing software on a computer network
Autonomous pipeline reconfiguration for continuous error correction for fills from tertiary cache or memory Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses
Controlling requests for access to resources made by multiple processors over a shared bus
Method and apparatus for generating and implementing smooth schedules for forwarding data flows across cell
based switches
Local memory buffers management for an ATM adapter implementing credit based flow control
Semiconductor process, power supply voltage and tem
perature compensated integrated system bus termination Software mechanism for accurately handling exceptions generated by speculatively scheduled instructions Disk cache management techniques using non-volatile storage
System and method for preserving instruction state
atomicity for translated program Enclosure for electronic modules
Digital Technical Journal Vol . 9 No. 4 1997 77
78 Jeng-Wei Pan, and Nicholas L.
Rethman
Nicholas Ilyadis and Richard Graham
Martin Edward Griesmer, Parayath Gopal Krishnakumar, and David Benson Richard Lee Sites
Henry Sho-Che Yang, Anthony G. Lauck, Kadangode K Ramakrishnan, and William R. Hawe
Mark A. Herdeg, James A. Wooldridge, Scott G. Robinson, Ronald F. Brender, and Michael V. lies
Richard Lee Sites
Joseph P. Coyle and Willian1 B . Gist
Joel J. Grodstein, Nicholas L. Rethman, and Jeng-Wei Pan
Keith Waters and Thomas M. Levergood William B . Gist and Joseph P. Coyle
Richard Lary, Robert Willard, Cathari.ne van Ingen, David Thiel, VVilliam Watson, Barry Rubinson, and Verell Boaen
Neal F. Jacobson
DigitJJ Technical Journal Vol. 9 No. 4 1997
Apparatus and method for accessi.ng SMRAM in a com
puter based upon a processor employing system manage
ment mode
Turbotable: apparatus tor directing address and commands between multiple consumers on a node coupled to a pipelined system bus
Apparatus for message fi l tering in a network using domain class
Low inductance electrical resistor terminator package Static timing verification in the presence oflogically false paths
Inter-module interconnect for simultaneous use with distributed LAN repeaters and stations
Apparatus and method for maintaining forwarding information in a bridge or router using multiple free queues having associated free space sizes
Translating, executing, and re-translating a computer program for finding and translating program code at unknown p rogram addresses
Method and apparatus for use in a network of the ethernet type, to i mprove fairness by controlling col lision backofftimes in the event of channel capture Method and apparatus for producing a software test system using complementary code to resolve external dependencies
Precision broadcast of composite programs including secondary program content such as advertisements Mechanism for screeni.ng commands issued over a communications bus for selective execution by a processor
System for interleaving memory modules and banks
System for executing and debugging multiple codes in a multi-architecture environment using jacketing means tor jacketing the cross-domain calls
Alternate execution and interpretation of computer pro
gram having code at unknown locations due to transfer instructions having computed desti nation addresses Reduced system bus receiver setup time by latching unamplified bus voltage
Timing verification using synchronizers and timing constraints
Method and apparatus for producing audio-visual synthetic speech
Semiconductor process power supply voltage and temperature compensated integrated system bus driver rise and fall time
Dual addressing arrangement for a communications interface architecture
Method of recording, playback, and re -execution of of concurrently running application progran1 operational commands using global time stamps
5,658 , 1 66
Mike Freeman, Stuart Keith Morgan, and Mike Romm
Paul M. Goodwin, David A. Tatosian, and Donald Smelser
Clark E. Lubbers, Susan G. Elkington, and Richard F. Lary
Dennis Joseph Murphy and Robert Neil Faiman, Jr.
Alexander Stein and William Grundmann Frank Samuel Caccavale
Edward S. Lowry
Mark F. Amberg, William K. Miller, Frank M. Nemeth, and
Dwayne H. Swanson Charles William Kautlnan Peter C. Hayden
David M . Fenwick, Denis ]. Foley, Stephen R. Van Doren, David W. Hartwell, Elbert Bloom, and Ricky C. Hetherington Rajendra K. Jain, K. K. Rama.krishnan, and Dah -Ming Chiu
Donald F. Hooper, Dave M. Tonge!, and Michael B. Evans
Clark E. Lubbers and Susan G. Elkington
Shawn Gallagher, James Scott Hiscock, Dahai Ding, Scott D ' Edwine Lawrence Rajendra K. Jain, K. K. Ramakrishnan, and Dah-Ming Chiu
Jeffrey Clifford Mogul
Wendell Burns Fisher, Jr. and Richard Sayde
J i.irgen Bertels
John Edmondson and Scott Taylor Mark A. Herdeg and Michael V. Iles David J. Sager
Jeffrey R. Harrow and Fred P. Messinger
Chester Walenry Pawlowski, Nicholas Alien Warchol, David Gerard Conroy, and R. Stephen Polzin
James P. Ellis, Mike Kantrowitz, and Will Sherwood
Modular coupler arrangement for use in a building wiring clistTi bu tion system
Memory stream buffer with variable-size prefetch depending on memory interleaving configuration Skip list data structure enhancements
I nterface for symbol table construction in a multi
language optimizing compiler
Topology independent system for state element conversion Phase-space surface representation of server computer performance in a computer network
Data processing system having a data structure with a single, simple primitive
System for reconfiguring addresses of SCSI devices via a device address bus independent of the SCSI bus
Method and apparatus for cryptographic authentication Method and apparatus for detecting and executing cross-domain cal ls in a computer system
Distributed data bus sequencing for a system bus with separate address and data bus protocols
Avoiding congestion system for reducing traffic load on selected end systems which utilizing above their allocated f:'lir shares to optimize throughput at intermecliate node Distributed interactive multimedia service system
Data structure enhancements for in -place sorting of a singly linked list
Method and apparatus tor interconnecting network devices in a networking h u b
System for setting congestion avoidance flag at intermediate node to reduce rates of transmission on selected end systems which uti lizing above their allocated fair shares
Cache memory system and method for selectively removing stale aJiased entries
Metl1od and apparatus for remotely booting a computer system
Method and apparatus tor multiscript access to entries in a directory
Method for testing an on-chip cache for repair Simulator system for code execution and debugging within a multi-architecture environment
Low delay means of communicating between systems on clifferent clocks
Method and device tor monitoring, manipulating, and viewing system information
System for checking tl1e acceptance of i/0 request to an interface using software visible instruction which provides a status signal and performs operations in response tJ1ereto
Apparatus and method tor improving tllC efficiency and quality of fl.mctional verification
Digital Technical Journal Vol . 9 No. 4 1 997 79
80
William B. Gist and Joseph P. Coyle
Norman Pau l Jouppi Mark A. Shand
Gerald J. B rand and Don L. Drin kwater
GiJ bert iYI . Wol rich, Timothy C. Fischer, and John A. Kowaleski , Jr.
Michel Gangnct and Jean-Manuel Van Thong
Rah u l Razdan and Gabriel B ischoff
Robert AUison Hart and Richard Harry Plourde
Larry D . Seiler, Robert S . McNamara, Christopher C. Gianos, and
Joel J . McCormack
Rah u l Razdan, Bill Grundmann, and Michael D. Smith
Colin Edward B rench Yoav Raz
Yeshayahu Artsy
Stephen Michael Birch, Gerard
Michel Gavrel , and Zaftar Iqbal Memon Hoe To Cho and Ming Huann Yuan Nitin Dhiroobhai God iwala, And re\v Myer Ebert, and Chester Walenty Pawlowski John Anthony DeRosa, Jr., Benn Lee Schreiber, Peter Chapman Hayden, and Scott Wade Apgar
Jeffrey P. Copeland and Dennis Ro binson Russel l Iknaian and Richard B. Watson, Jr.
David J. Sager
David Lomet and Betty Salzberg
Steven A. Kirk, William Barabash, and WiJliam S . Yerawnis
Michael Burrows
Michael Ben-Nun, Simoni Ben- Michael, and Moshe De- Leon
Digiral Technical Journal Vol . 9 No. 4 1 997
System for generating error signal to indicate mismatch in commands :md preven ting processi ng data associated with the received com mands when mismatch command has been determined
Semicond uctor process, power supply and temperature compensated system bus integrated i nterface architec
ture with precision receiver
Memory system and method for selective m u lti-level caching using a cache level code
Configurable d igital signal interface using field programmable gate array to reformat data
Uninterruptible power supply with fau lt tolerance in a high voltage environment
Rou nding adder for floating point processor
Method and apparatus for automatic gap closing in computer aided drawing
Using pre-analysis and a 2 -state optimistic model to reduce computation in transistor circuit simulation Probe card shipping and handling system
Method for quickly painting and copying shal low pixels on a deep fi·anlC buffer
Dynamically programmable reduced i nstruction set computer with programmable processor load ing on pro
gram number field and program number register contents Two part closely coupled cross polarized EMI shield Distributed m u lti-version commitment ordering protocols for guaranteeing serializability d uring transaction processing
Rou ting objects on action paths i n a distributed computing system
Method of manutacture of an interconnect stress test coupon
Programmable interrupt signal router
Test methodology for exceeding tester pin cou nt for an asic device
Method and apparatus for configuring a computer system
Board mounting system with self guiding interengagement Low skew remote absolute delay regulator cbip
Method and apparatus for parallel execution of com puter programs using intormation providi ng for recon
struction of a logical sequential program
Concurrency a nd recovery for index trees with nodal updates using mu ltiple atomic actions
Method of rule execution i n an expert system usi ng equival ence cl asses to group data base objects Method for encoding delta values
Traffic shaping system for asynchronous transfer mode networks
ISSN 0898 -90 1 X
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