interface design
6-7. RAM ACCESS
The 9002 system bus, see Figure 4-1, consists of a 16.bit address lines and 8-bit data lines, along with timing and control signal lines. The address and data lines operate at TTL data levels, open collector. The polarity of the signals is ground true; OV
=
logic 1, and +5V=
logic O.The address and data bus timing is structured around the RAM memory cycles.
The three clocks required for a memory cycle are Clock 1, Clock 2, and Clock 3.
Referring to Figure 6-4 a memory cycle is defined as an interval from the lagging edge of Clock 3 to the lagging edge of the next Clock 3. Any device may read from or write in the RAM bysputting the address on the bus during a memory cycle which is not being used by any other device along with a Read Data signal or a Write Data signal. A bus priority structure exists to infonn the user when the bus is free.
The CPU has first priority and whenever the CPU is using the bus, it outputs CPU Bus Request signal on the bus in the same memory cycle as it outputs Read Data or Write Data. The CPU Bus Request signal informs all other users to relinquish that cycle.
Second priority is assigned to the Memory Refresh Request signal. This signal is issued to refresh the MOS RAM integrated circuits and all peripheral users must relinquish the bus during its presence.
The third priority item is Character Refresh. During this time, all peripheral users must relinquish the bus. Character Refresh may occur up to 80 memory cycles in a row, and thus uses approximately 20 percent of the available memory cycles (see also Figure 4-5).
All users accessing the RAM must output a Peripheral Bus Request, along with a Read Data or Write Data signal. To resolve contention among users, a priority scheme exists. Figure 6-5 shows a circuit for resolving bus priorities. This circuit allows any peripheral device to use any memory cycle during which the bus is not occupied by a higher priority circuit. If one peripheral in a slot to the left of the
200 200 1 00 200
I_nr I nr " ~~~c 1
S( ,~T'I' ~~~c '"I
CLOCKT
L-J I I LJ L
~III
L-J~---~L-J
CLOCK 3
I
CLOCK 3 GATE
1==
13 "SEC MEMORY CYCLE - - - - IADDRESS BUS - - - -...
X
1..----DATA BUS (READ FROM RAMI
DATA BUS X X
(WRITE TO RAM OR COMMAND 1101 _ _ _ _ _ _ _ _ _ --J I.. _ _ _ _ _ _ _ _ _ _ ---J 1.. _ _ _ _
CPU BUS REQUEST MEMORY REFRESH REOUEST CHARACTER REFRESH PERIPHERAL BUS REQUEST READ DATA
WRITE DATA COMMAND 110
PiNT Figure 6-4. Timing Diagram of Interface Signals.
second peripheral (when viewing the card cage from the front, as in Figure 6-1) transmits a Peripheral Bus Request signal, the second peripheral interface circuit must pass this signal through pin A48 to the next card. If the first peripheral does not transmit a Peripheral Bus Request, the second may use the bus and must generate a Peripheral Bus Request of its own to output on pin A48 to the next card.
In the 9002 system, slot 5 is reserved for the system timing card, and its peripheral circuit (RS-232C interface) has the lowest priority. The peripheral priorities in ascending order are: slot 5, 4, 3, 2, 7, and 6, see Figure 6-1. Slot 1 is reserved for the video/RAM card and has no peripherals interfaces on it. Slot 3 is reserved for the microprocessor card and the Peripheral Bus Request on this card is a straight wire from pin A38 to A48. Any user designed card not using the Peripheral Bus Request (such as a card using only Command I/O) must pass the Peripheral Bus Request through in a like manner.
In order to use the bus, the user must apply the Address, Peripheral Bus Request and Read Data or Write Data signals, all for one entire memory cycle. If it is a write data operation, the data must be applied to the bus for the entire interval.
If it is a Read Data operation, the data is not be valid until just prior to the lagging edge of clock 2 and remains valid until just past the lagging edge of clock 3.
6-10
A31 CPU BUS REQUEST
A39 >-'::~;:;'~A~M~::-:-:'::':;T==:,=,~F:':'RR:::::;=:::~'::':E~~~Q::,;U;;.:E:::.;ST'----<A----"'" BUS BUSY TO
A40 r.P';':Ee'RI:;::PH~E;":RA;':':L"'::B';;':US:':'R:;;:E=:::Q;""UE""'ST=""""IN---a 7420
)--....:;;:=:;;;.;,.---
INTERNALA38 r-=..:.:!:.!==:..:..:.:;.=~:..:.,-__<:L~ CIRCUITS
Figure 6-5. Logic Diagram of Bus Request, Address, and Data Circuits.
6-8. COMMAND INPUT/OUTPUT OPERATION.
A19
A26
A34
The user may make use of the Command Input/Output instructions of the 9002 CPU. When the CPU executes a Command Input/Output instruction, as a result of a users Command I/O Interrupt, it outputs CPU bus request, along with Com-mand I/O signal (see Figure 6-4). The user must decode bits 12 and 13 of the address bus to determine if it is a CPU input or an output.
When the user has received Command I/O and has decoded bits 12 and 13 and determined that a CPU input command exists, bits 10 through Is must be decoded to determine if the command is for the user's device. If it is, the data shall be returned to the CPU via the data bus all during the Command I/O time.
Note that address bus bits 0 through 7 are the contents of the accumulator at the time the input command is executed. Care must be taken to load the accumulator with the proper value before starting the Command I/O operation, because bits 7 and 6 are part of the device number.
ADDRESS BUS BITS
13 12 11 10 9 8 7 6 5 4 10
r
0 115I
14 13 12 11 110 1 X X-..---00 = INPUT DEVICE NUMBER
12=1 for 9002 CPU
DATA BUS BITS
7 6 5 4 3 2
DATA TO CPU Shown below is the format for the output command:
ADDRESS BUS
3 X
2 X
LSB
o
13 12 11 10 9 8 7 6 5 4 3 2
~
OUTPUT =1= 00
v
DEVICE NUMBER 00 = 1 for 9002 CPU
LSB 0 X X
1
o
1 . . 1
When a Command I/O is received by the user, and bits 12 and 13 are not both zero, it is a ZPU output command and the user must decode 00 through Os to determine if the command is for his device. If it is, the data from the CPU is on bits 0 through 7 of the address bus. The data is stable well before the leading edge of clock 1 and remains stable until after the lagging edge of clock 3.
6-9. INTERRUPT.
The interrupt capability is presently not used in the 9002 system. It can be implemented by the user to perform a one-wrod interrupt (usually restart). To
6-12
use the interrupt, the user must set the outgoing interrupt line (pin ASO) synchro-nously with the lagging edge of clock 3. When a signal called PINT is received, the user must reset the interrupt line and send the interrupt instruction over the data bus during the PINT interval. For users not using interrupt, the card must feed through the interrupt signal from pin A37 to pin ASO.