AND TIMER
The Intel 8155 is made up of the following opera-tional areas:
a. 256 x 8 Static RAM.
b. 14 bit Timer.
c. Two 8-bit 110 ports (one input and one output) and one 6-bit I/O input port.
3-37. 8155 I/O PORT PROGRAMMING The parallel I/O port, which is controlled by the Intel 8155 PPI chip, is designed to interface directly with a Bell Model 801 Automatic Calling Unit (ACU). The PPI chip has two 8 bit parallel ports (Port A which is an output port, and Port B which is an input port) and a 6-bit parallel input port (Port C). The follow-ing table is a list of the signals interfaced to the PPI chip.
Port A Outputs Port B Inputs Port C Inputs
NB1orSTXDO RIO (PortO) PNDorSRXDO
NB2orSTXD1 RI1 (Port 1) COSorSRXD1 NB4orSTXD2 RI2 (Port 2) DLOor SRXD2 NB8orSTXD3 RI3 (Port 3) ACR orSRXD3 PGRST (For 8251 COO (PortO) FINT
USARTS)
Reset for INT FLOPS CD1 (Port 1) PFS
CRa C02 (Port 2)
DPR CD3 (Port 3)
NOTES
1. RI and CD signals are connected to interrupt circuit.
2. RI and CD are from serial 110 ports.
A,20H OE6H
;NON-SPECIFIC EOI
3-38. ADDRESSING OF 1/0 PORTS. The I/O section of the 8155 consists of a Command/Status Register (C/S) and one register for each of the three I/O ports. Addresses for these four registers are pro-vided in table 3-2.
3-39. INITIALIZATION. The 8155 is reset when power is initially applied to the system. However an initialize routine must be generated for the 8155 in order to set up the ACU interface, and to remove the reset condition from the USAR TS and from the RINT and PINT interrupt flops. Table 3-18 is a typical initialize routine.
3-40. COMMAND REGISTER FORMAT. The Command Register consists of eight I-bit latches.
Bits 0-3 define the mode of Port A, B, and C, bits 4 and 5 enable or disable Port A and B interrupts, and bits 6 and 7 are used for the Timer portion of the 8155. Figure 3-10 shows the Command Register for-mat.
The Command Register can be altered at any time by performing an 110 write command to port E8. Table 3-19 is a typical Command Register Load routine.
3-41. STATUS REGISTER FORMAT. The Sta-tus Register consists of seven I-bit latches. Bit 0-5 define the status of the ports, and bit 6 defines the status of the timer. The Status Register format is shown in figure 3-11.
The contents of the Status Register can be obtained at any time by performing an I/O read to port E8.
Programming Information iSBCS44
3-20
6 5 4 3 2 0
L
TIMERCOMMAND---I"~
DEFINES PORT A
I
0 = INPUTDEFINES PORT B 1 = OUTPUT
{
00 = ALT1 11 :: ALT2 DEFINES PORT C 01 = ALT3 10 = ALT4
INTERRUPT 1 = ENABLE ENABLE PORT A }
ENABLE PORT B 0 = DISABLE
INTERRUPT
00 = NOP - DO NOT AFFECT COUNTER OPERATION
01 = STOP - NOP IF TIMER HAS NOT STARTED: STOP COUNTING IF TIMER IS RUNNING 10 = STOP AFTER TC - STOP
IMMEDIATELY AFTER PRESENT TC IS REACHED (NOP IF TIMER HAS NOT STARTED)
11 = START - LOAD MODE AND CNT LENGTH AND START IMMEDIATELY AFTER LOADING (IF TIMER IS NOT PRESENTLY RUNNING). IF TIMER IS RUNNING, START THE NEW MODE AND CHT LENGTH IMMEDIATELY AFTER PRESENT TC IS REACHED.
Figure 3-10. Command Register Format
Table 3-18. Typical 8155 Initialize Routine
;INTAUX INITIALIZES THE 8155 PARALLEL I/O
;PORT CHIP. THE DATA IN REG C IS PUT OUT
;ON PORT A. THE TIMER IS STOPPED.
PUBLIC INTAUX
INTAUX: MVI A,41H ;PORT A OUT; PORTS B + C
IN; STOP TIMER
OUT OE8H
MOV A,C ;GET PORT A DATA
OUT OE9H
RET END
NOTE
Register C must be loaded with the correct bit configuration to set up the ACU interface and to reset the USARTS, and the Ring Indicator and Carrier Detect Interrupt flops. A typical bit configuration would be COHo
iSBC 544 Programming Information
Table 3-19. Typical Command Register Load Routine
;INTAUX INITIALIZES THE 8155 PARALLEL I/O PORT CHIP. THE DATA IN REG
;C IS PUT OUT ON PORT A. THE TIMER IS STOPPED.
INTAUX;
PUBLIC EXTRN MVI OUT MOV OUT RET END
INTAUX BASAD A,41H E8H A,C E9H
;PORT A OUT; PORTS B&C IN; STOP TIMER
;GET PORT A DATA
AD7 ADs ADs AD4 AD3 AD2 AD1 ADo
PORT A INTERRUPT REQUEST ' - - _ - - - . PORT A BUFFER FULUEMPTY
(INPUT/OUTPUT)
' - - - . PORT A INTERRUPT ENABLE ' - - - . PORT B INTERRUPT REQUEST ' - -_ _ _ _ _ _ _ ---. PORT B BUFFER FULUEMPTY
(INPUT/OUTPUT)
L-.. _ _ _ _ _ _ _ _ _ - - - . PORT B INTERRUPT ENABLED L-.. _ _ _ _ _ _ _ _ _ _ _ - - - . TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN TERMINAL COUNT IS REACHED, AND IS RESET TO
LOW UPON READING OF THE CIS REGISTER OR STARTING NEW COUNT.)
Figure 3-11. Status Register Format 3-42. PORT A PROGRAMMING
Port A is an output port, and is written to by the CPU. Data is written to Port A, or a call is placed with the ACU, by performing a write to E9.
The status of the previous bits written to Port A can be obtained by performing a read to E9.
Figure 3-12 shows the bit definitions for Port A.
3-43. PORT BAND C PROGRAMMING Data from Port B and Port C is read by performing a read of EA and EB, respectively. Bit definitions for Ports Band C are given in figure 3-13.
Typical routines for programming Ports A, B, and C are shown in table 3-20.
3-44. 8155 TIMER PROGRAMMING The 8155 Timer is a 14-bit down counter that counts the timer input pulses (1.2288 MHz) and provides an output of a square wave or pulse when terminal count (TC) is reached. The timer output (TINTO) is connected by a jumper to the RST 7.5 inut on the on-board 8085A CPU. By connecting the timer output to the RST 7.5 input of the CPU, the CPU can be in-terrupt driven at an interval desired for serial I/O communications. The count lengths required for various baud rates are given in table 3-21.
3-45. ADDRESSING. The 8155 Timer has two I/O addresses associated with it. One address (BC) is for the low order byte (least-significant bits of count
Programming Information
3-22
D5
PORTA
NUMBER BIT NB1 (LSR): 1 = TRUE
L - - _ _ NUMBER BIT NB2: 1 = TRUE
L - . _ _ _ _ _ NUMBER BIT NB4: 1 = TRUE
L....-_ _ _ _ _ _ _ NUMBER BIT N88 (MSB): 1 = TRUE L . . . . - _ _ _ _ _ _ _ _ _ USART RESET: 1 = TRUE L....-_ _ _ _ _ _ _ _ _ _ _ INTERRUPT RESET: 1 = TRUE
L - . _ _ _ _ _ _ _ _ _ _ _ _ _ DIGIT PRESENT ON NUMBER BIT LINES: 0 = TRUE
' - - - CALL REQUEST: 0 = TRUE
Figure 3-12. PPI Port A Bit Definitions
Table 3-20. Typical I/O Port Programming Routines
;AOUT OUTPUTS THE DATA IN REG C TO PORT A OF THE 8155.
;USES-C DESTROYS-A
AOUT:
PUBLIC MOV OUT RET END
AOUT A,C OE9H
;GETDATA
;AIN READS PORT A OF THE 8155 INTO REG A.
;USES-NOTHING DESTROY8-A
AIN:
PUBLIC AIN
IN RET END
OE9H
;BIN READS PORT B OF THE 8155 INTO REG A.
;USES-NOTHING DESTROYS-A
BIN:
PUBLIC BIN
IN RET END
OEAH
;CIN READS PORT C OF THE 8155 INTO REG A.
;USES-NOTHING DESTROYS-A.
CIN:
PUBLIC EXTRN IN RET END
CIN BASAD OEBH
iSBCS44
iSBC S44 Programming Information
D6 DS PORTC
PRESENT NEXT DIGIT: 0 = TRUE
CALL COMPLETE, LINE TRANSFERRED TO MODEM:
0= TRUE
DATA LINE OCCUPIED: 0 = TRUE
ABANDON CALL & RETRY: 0 = TRUE FLAG INTERRUPT: 1 = TRUE POWER FAIL SENSED: 1 = TRUE
PORTB
DO
RING INDICATOR, PORT 0: 0 = TRUE
L - -_ _ _ RING INDICATOR, PORT 1: 0 = TRUE ' - - - RING INDICATOR, PORT 2: 0 = TRUE ' - - - RING INDICATOR, PORT 3: 0 = TRUE
L..-_ _ _ _ _ _ _ _ _ _ CARRIER DETECT, PORT 0: 0 = TRUE
L..-_ _ _ _ _ _ _ _ _ _ _ _ CARRIER DETECT, PORT 1: 0 = TRUE
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ CARRIER DETECT, PORT 2: 0 = TRUE
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CARRIER DETECT, PORT 3: 0 = TRUE
Figure 3-13. Port Band C Bit Definitions
length), and the other address (ED) is for the high order byte (most-significant bits of count length and
timer mode). Figure 3-14 shows the timer format. 1171 161 151 141 131"121 111 10
I AD~~ESS
I ,
3-46. COUNT LENGTH REGISTER LOADING AND READING. The timers 1/0 addresses serve a dual purpose. During an 110 Write operation, the count length (bits 0-13) and mode (bits 14-15) are loaded into the 16 bit Count Length Register; during an 1/0 Read operation, the present count (the count at the time of the 110 Read operation) and the mode bits are read. To ensure that the correct count is read, it is preferable to stop counting, read the counter, and then reload the counter and continue counting.
Table 3-21. Baud Rates Vs Count Lengths
Baud Rate Decimal Count
4800 256
2400 512
1200 1024
600 2048
110 11171
75 16384
i
LSB OF CNT LENGTH