PCI·TO-PC CARD16 CONTROLLER UNIT - Solutions Integrated

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PCI·TO-PC CARD16 CONTROLLER UNIT

SCPS008 - FEBRUARY 1996

3-20 PCLK

PCIBUS PARAMt:TER MEASUREMENT INFORMATION

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Figure 5. PCLK Timing Waveform

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Figure 6. RSTIN Timing Waveforms

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Figure 7. Shared Signals Timing Waveforms

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INSTRUMENTS

: POST OFFICE BOX 665303 • DALlAS, TEXAS 76285

PC Card cycle timing

The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and 1/0 window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and holci times and the PC Card command active interval. This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput.

The PC Card address setup and hold times are a function of the wait-state bits. Table 6 shows address setup time in PCLKcycles and nanoseconds for 1/0 and memory cycles. Tables 7 and 8 show command active time in PCLK cycles and nanoseconds for I/O and memory cycl~s. Table 9 shows address hold time in PCLK cycles and nanoseconds for 1/0 and memory cycles.

Table 6. PC Card Address Setup Time, tsu(A), 8-Blt and 16-Blt PCI Cycles WAIT-STATE BITS TS1-0 = 01

(PCLK/ns)

1/0 3190

Memory WS1 0 2/60

Memory WS1 1 4/120

Table 7. PC Card Command Active Time, telA), 8-Blt PCI Cycles

WAIT-STATE BITS TS1-0 = 01

WS ZWS (pCLK/ns)

0 0 19/570

110 1 X 231690

0 1 71210

00 0 19/570.

01 X 231690

Memory 10 X 231690

11 X 231690

00 1 71210

Table 8. PC Card Command Active Time, te(A), 16-Blt PCI Cycles

WAIT-STATE BITS TS1-0 =01

WS ZWS (PCLK/ns)

0 0 71210

1/0 1 X 11/330

0 1 N/A

00 0 91270

01 X 131390

Memory 10 X 171510

11 X 21/630

00 1 51150

Table 9. PC Card Address Hold Time, theA), 8-Blt and 16-Blt PCI Cycles WAIT-STATE BITS TS1-0 =01

(PCLK/ns)

I/O 2/60

Memory WS1 0 2/60

Memory WS1 1 3190

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INSTRUMENTS

POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 3-21

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PCI·TO·PC CARD16 CONTROLLER UNIT

SCPS008 - FEBRUARY 1996

timing requirements over recommended ranges of suppl.y voltage and operating free-air.

temperature, memory cycles (for 100-ns common memory) (see Note 6 and Figure 8)

ALTERNATE

MIN MAX UNIT SYMBOL

tsu Setup time, 00 and CE2 before WEIOE low T1 60 ns

tsu -Setup time, CA25-CAObefore WEIOE low T2 tsu(A) +2PCLK ns

tsu Setup time, REG before WEIOE low T3 90 ns

tpel Propagation delay time, WEIDE low to WAIT low T4 ns

tw Pulse duration, WEIDE low T5 200 ns

th Hold time, WEIDE low after WAIT high T6 ns

th Hold time, CE1 and CE2 after WEIOE high T7 120 ns

tsu Setup time (read), CDATA15-CDATAO valid before OE high T8 ns

th Hold time (read), CDATA15-CDATAO valid after OE high T9 0 ns

th Hold time, CA25-CAO and REG after WEIDE high T10 - theA) + 1 PCLK ns

tsu Setup time (write), CDATA15-CDATAO valid before WE low T11 60 ns

th Hold time (write), CDATA15-CDATAO valid after WE low T12 240 ns

NOTE 6: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle type (read/write, memory 11/0) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.

timing requirements over recommended ranges of supply voltage and operating free-air temperature, 1/0 cycles (see Figure 9)

ALTERNATE

MIN MAX UNIT SYMBOL

tsu Setup time, REG before 10RD/IOWR low T13 60 ns

tsu Setup time, CEl and CE2 before IORD/IOWR low T14 60 ns

tsu . Setup time, CA25-CAO valid before IORDliOWR low T15 tsu(AI+2PCLK ns

ted Propagation delay time, 10lS16 low after CA25-CAO valid T16 35 ns

tpel Propagation delay time, lORD low to WAIT low T17 35 ns

tsu Setup time (read), CDATA 15-CDATAO valid before lORD high T23 10 ns

th Hold time (read), CDATA15-CDATAO valid after lORD high T24 0 ns

tsu Setup time (write), CDATA15-CDATAO valid before IOWR low T25 90 ns

th Hold time (write), CDATA15-CDATAO valid after 10WR high T26 90 ns

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see Figure 10)

-PARAMETER ALTERNATE

MIN MAX UNIT SYMBOL

BVD2 low to SPKROUT low 30

BVD2 high to SPKROUT high T27

tpd Propagation delay time 30

IREQ to IRQ15-IRQ3 ns

3-22 POST OFFICE SOX 655303 • DALlAS. TEXAS 75265

PC CARD PARAMETER MEASUREMENT INFORMATION

CA25-CAO

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CDATA15-CDATAO (read)

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Figure 8. PC Card Memory Cycle

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Figure 9. PC Card 1/0 Cycle

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INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-23

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SCPSO08 - FEBRUARY 1996

3-24

PC CARD PARAMETER MEASUREMENT INFORMATION

BVD2 _ _ _ _

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SPKROUT _ _

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---11'---

I4-T28~

IRQ15-IRQ3 _ _ _ _ _ _ _ _ _ _

*----Figure 10. Miscellaneous PC Card Delay Times

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INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

• 3.3-Y Core Logic With Universal PCI Interface Compatible With 3.3-Y or 5-Y PCI Signaling Environments

• Supports PCI Local Bus Specification 2.1

• Mix and Match 3.3-V15-Y PC Card16 Cards and 3.3-Y CardBus Cards

• Supports Two PC Card™ or CardBus Slots With Hot Insertion and Removal

• 1995 PC Card Standard Compliant

• Low-Power Advanced Submlcron CMOS Technology

• Uses Serial Interface to Texas Instruments (TI) TPS2202A Dual Power Switch

• System Interrupts Can Be Programmed as PC I-Style or ISA IRQ-Style Interrupts

• ISA IRQ Interrupts Can Be Serialized Onto a Single IRQSER Pin

• Independent Read and Write Buffers for Each Direction

• Supports Burst Transfers to Maximize Data Throughput on the PCI and CardBus Bus

• Multifunction PCI Device With Separate Configuration Spaces for Each Socket

• Five PCI Memory Windows and Two 1/0 Windows Available to Each PC Card16 Socket

• Two 1/0 Windows and Two Memory Windows Available to Each Card Bus Socket

• CardBus Memory Windows Can Be Individually Selected Prefetchable or Nonprefetchable

• Exchangeable Card (ExCATM)-Compatible Registers Are Mapped In Memory and I/O Space

• TI Extension Registers Are Mapped In the PCI Configuration Space

• Intel™ 82365SL-DF Register Compatible

• Supports 16-Bit Distributed Direct Memory Access (OM A) on Both PC Card Sockets

• Supports PCIPCI DMA on Both PC Card Sockets

• Supports Zoom Yldeo Mode

• Supports Ring Indicate

• Packaged In 20S-Pin Thin Plastic Quad Flatpack (PDV)

Table of Contents

Description ... 4-4 DMA Registers . . . 4-104 Functional Block Diagram - 16-B~ PC Card Interface. . . . .. 4-5 Absolute Maximum Ratings ... 4-109 Functional Block Diagram - CardBus Card Interface ... 4-6 Recommended Operating Conditions ... 4-109 Terminal Assignments - PCI-to-PC Card (16 Bit) . . . .. 4-7 Recommended Operating Conditions for PCllnterface ... 4-109 Terminal Assignments - PCI-to-CardBus ... 4-8 Recommended Operating Conditions for PC Cards A and B . 4-110 Signal Name/Terminal Number Sort Tables ... 4-9 Electrical Characteristics ... : ... 4-110 Terminal Functions ... 4-13 PCI Clock/Reset Timing Requirements ... 4-110 Architecture ... 4-22 PCI Timing Requirements ... 4-111 PC Card DMA and Distributed DMA . . . .. 4-41 Parameter Measurement Information ... 4-112 Ring Indicate ... 4-45 PClbus Parameter Measurementinformation ... 4-113 Zoom Video ... ; ...•... 4-46 PCI Card Cycle Timing ... 4-114 Power Management ... ; ... 4-47 Timing Requirements ... 4-115 PCI Configuration Headers ... 4-50 Switching Characteristics ... 4-115 ExCA Registers ... 4-76 PC Card Parameter Measurement Information ... 4-116 CardBus Socket Registers . . . .. 4-95

ExCA and PC Card are trademarks of Personal Computer Memory Card International ASSOCiation (PCMCIA).

PCI·TO-PC CARD16 CONTROLLER UNIT

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