PC I· TO-PC CARDTM CONTROLLER UNIT

SCPS001 F - OCTOBER 1994 - REVISED MARCH 1996

miscellaneous function 1 register PCI address (hex): OC

Thi~ 32-bit register contains the 8IST, header type, latency type, and cache line fields.

Bit 31

I

³⁰

POST OFFICE BOX 655303 • OAU;AS. TEXAS 75265

I

base-address registers 0-0

PCI addresses (hex): 10,14,18, 1C, 20, 24

Base-address register

°

determines the 110 address of the index/data register pairs used to access the Intel 82365SL-DF-compatible registers. The base register is programmed with the address of the index register. The data register is mapped at the next higher byte address. Base-address registers 1-5 are reserved.

Bit 31

I

³⁰

I

²⁹

I

²⁸

I

²⁷

I

²⁶

I

²⁵

I

²⁴

Name Base Address

Default 0

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

Bit 23

I

^.22

I

²¹

I

²⁰

I

¹⁹

I

¹⁸

I

¹⁷

I

¹⁶

Name Base Address

Default 0

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

Bit 15

I

¹⁴

I

¹³

I

¹²

I

¹¹

I

¹⁰

I

⁹

I

⁸

Name Base Address

Default 0

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

Bit 7

I

⁶

I

⁵

I

⁴

I

⁰

Name Base Address

Default 0

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

BIT NAME ACCESS DESCRIPTION

31-2 Base Address R/W Base registers

1 R Reserved

o

R 1/0 indicator bit. Hardwired to 1.

~1ExAs

IJlfSTRUMENTS

POST OFFICE .BOX 655303 • DALlAS. TEXAS 75265 2-45

SCPSOOl F - OCTOBER 1994 - REVISED MARCH 1996

expansion ROM base address register

PCI address (hex): 30PCI address (hex): 30

PCI provides this 32-bit register to allow software remapping of device-expansion ROM. The PCI1 050 does not implement this feature.

Bit Name Default Bit Name Default Bit Name Default Bit Name Default BIT 31-0

2·46

I

J

I

NAME Expansion ROM Base Address

30 0 22 0 14

0 6 0

I

²⁹

I

²⁸

I

²⁷

I

²⁶

I

²⁵

I

²⁴

Expansion ROM Base Address

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

²¹

I

²⁰

I

¹⁹

I

¹⁸

I

¹⁷

I

¹⁶

Expansion ROM Base Address

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

¹³

I

¹²

I

¹¹

I

¹⁰

I

⁹

I

⁸

Expansion ROM Base Address

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

J

⁵

I

⁴

I

L

^{' 1}

J

⁰

Expansion ROM' Base Address

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

I

⁰

ACCESS DESCRIPTION

R Not implemented

-!111ExAs

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

miscellaneous function 2 register PCI address (hex): 3C

This 32-bit register contains the MAX_LAT, MAX_GNT, INT PIN, and INT LINE fields.

Bit 31

I

³⁰

I

²⁹

I

²⁸

I

²⁷

I

²⁶

I

²⁵

I

²⁴

BIT NAME ACCESS DESCRIPTION

31-24 MAX LAT R 0 • Target only 23-16 MAX GNT R 0 = Target only

15-8 INTPIN R Interrupt routing is programmable in the interrupt register. Hardwired to 1.

Used to communicate interrupt line routing but does not affect device function. Field is written to by 7-0 INT LINE RNJ the host software after resource allocation and is available to be read by device drivers and

operating systems.

PCI header reserved registers

PCI addresses (hex): 28, 2C, 34, 38

These 32-bit registers are defined by PCI as reserved and are read only with a hardwired value of O.

Bit 31 30

PCI-TO-PC CARDTM CONTROLLER UNIT

SCPSOO1 F - OCTOBER 1994 - REVISED MARCH 1996

TI extension registers

The TI extension registers are accessible only in PCI configuration space arid are used to control features not found in the Intel 82365SL-DF. The six registers are listed in Table 7.

Table 7. TI Extension Registers

NAME PCIADDRESS

SOCKET A SOCKETB

Initialization register 40h 44h

Write buffer control register 41h 45h

Miscellaneous register 42h 46h

Memory window page register 43h 47h

Interrupt-mode register 1 48h

Interrupt-mode. register 2 49h

Initialization register

PCI addresses (hex): Socket A: 40 Socket B: 44

This register controls device I/O addressing and software reset.

Bit 7 6 5 4 3 2 1 0

Name

- -

^TS1 ^TSO

-

^DEVID ^SRES

-Default 0 0 0 0 0 0 0 0

BIT NAME ACCESS DESCRIPTION

7-6 RJW Reserved

PCI clock frequency. Bits 5-4 are programmed at power up to indicate the fraquency of the PCI clock. The PC Card cycle generator uses PCI clock for waveform timing and needs to knoW the frequency.

5-4 TS1-TSO RJW TS1 TSO PCI Clock Frequency

0 0 25 MHz

0 1 33 MHz

1 0 Reserved

1 1 Reserved

3 RJW Reserved

Device number

2 DEVID RJW

o -

Valid index range is OOh to 3Fh for socket A and 40h to 7Fh for socket B.

1 - Valid index range Is SOh to BFh for socket A and COh to FFh for socket B.

Soft reset SRES RJW 0= Normal operation

1. Reset PC11050

0 RJW Reserved

:111EXAS

INSTRUMENTS

2-48 POST OFFICE BOX 655303- DALlAS. TEXAS 75266

write buffer control register

PCI addresses (hex): Socket A: 41 Socket B: 45 This register controls the internal write buffer.

Bit 7 6 6 4 3 2 1 0

Name

- - -

^IOBUF ^FDEP ^FEN ^FULL ^EMPTY

Default 0 0 0 0 0 0 0 1

BIT NAME ACCESS DESCRIPTION

7~ R/W Reserved

Write buffer cycle select

4 10BUF R/W

o.

Memory writes only to wrHe buffer 1. Memory and I/O wrHes to write buffer WrHe buffer depth

3 FDEP R/W O. Fourdeep

1. One deep

WrHe buffer eneble/disable

2 FEN R/W

o.

Write, buffer off

1 • Write buffer on WrHe buffer full FULL R

o.

Write buffer not full

1 -WrHe buffer full

When read, EMPTY indicates write buffer status.

Read 0 • WrHe buffer not empty 0 EMPTY R/W Read 1 • Write buffer empty

When written to, EMPTY allows software to fl\lsh the wrHe buffer.

Write 0 -No change WrHe 1 • Flush write buffer

:illExAs' .

INSTRUMENTS

POST OFFICE BOX ~. DALLAS. TElWl75265 2-49

SCPS001F-OCTOBER 1994-REVISED MARCH 1996

miscellaneous register

Bit

PCI addresses (hex): Socket A: 42 Socket B: 46

This register controls socket PC Card ring indicate, speaker,and card-voltage detection.

7 6 6 4 3 2 1 0

Name

- - -

^ATAEN'

- -

^SPKEN ^BIFG

Default 0 0 0 0 0 0 1 0, ,

BIT NAME ACCESS

7-5 RNI

4 ATAEN 'RNV

3-2 RNV

SPKEN RNV

o BIFG RNV

Reserved

ATA special feature enable

o -

Normal operation

DESCRIPTION

1 - 1/0 window addresses 3F7h and 377h are read only. Input FOC_07 is routed to A031 during reads iroml/O 3F7h and 3nh.

Reserved

Speaker-to-speaker out enable o - SPKR routing to SPKROUT disabl8d 1 -SPKR routing to SPKROUT enabl~

Card-interrupt flag. BIFG is set when the card asserts IREa. Writing a 1 to this b~ clears the flag.

O. 'Clear '

-1 = Card interrupt has occurred.

memory window page register

Bit

PCI addresses (hex): Socket A: 43 . Socket ~: 47

This register contains an 8-bit page number that is compared with PCI address signals AD31LAD24 during memory cycles. If the page bits P7 -PO match AD31-AD24, the PCI1 050 memory-window-decode logic is enabled. This allows the memory windows to be located above the first 16M bytes of system address space, which is a limitation of the ISA bus. By using the page register, the programmer can locate the PC Card memory windows in any of the 256 separate 16M-byte pages that comprise the 4G bytes of PCI address space.

7 6 6 4 3 2 1 0

Name P7 P6 P5 P4 P3 P2 P1 PO

Default 0

BIT NAME

7-0 P7-PO

2-50

0 0 0 0

ACCESS DESCRIPTION

RNV Memory window page register

~ 1ExAs . ".; ,

INS1RlJMENTS ..

POST OFFice BOX 655303'. DALLAS. TEXAS 75265

0 0 0

Interrupt-mode register 1 PCI address (hex): 48

This register determines whether interrupts I R03/INTA, IR04/INTB, IR05/INTC, and IR07/INTD· are configured as totem-pole or open-drain outputs.

Bit 7 6 5 4 3 2 1 0

Name

- - - -

ÎRQ7 ÎRQ5 ÎRQ4 ÎRQ3

Default 0 0 0 0 0 0 0 0

BIT NAME ACCESS DESCRIPTION

7-4 FWI Reserved

Bit 3 configures IRQ7/1NTD as an open-draln output for connection to PCI bus interrupts.

3 IRQ7/INTD FWI

o •

Open-drain PC I-type interrupt 1 = Totem-pole ISA-type output

BR 2 configures IRQ5IINTC as an open-drain output for connection to PCI bus interrupts.

2 IRQ5/INTC FWI

o

= Open-drain Pel-type interrupt 1 a Totem-pole ISA-type output

Bit 1 configures IRQ4/INTB as an open-drain output for connection to PCI bus Interrupts.

IRQ4/INTB FWI

o

= Open'-cirain PCI-type Interrupt 1 = Totem-pole ISA-type output

Bit 0 configures IRQ3/INTA as an open-drain output for connection to PCI bus Interrupts.

0 IRQ3/INTA FWI

o

= Open-drain PC I-type interrupt 1 _ Totem-pole ISA-type output

="'~

INS1RUMENTS

POST OFFICE BOX 665303 • DAUAS. TEXAS 75265 2-51

SCPSO01 F - OCTOBER 1994 - REVISED MARCH 1996

Interrupt-mode register 2

PCI address (hex): 49

This register determines whether interrupts IRQ9, IRQ10, IRQll, IRQ12, IRQ14, and IRQ15 are configured as totem-pole or open-drain outputs.

Bit 7 6 5 4 3 2 1 0

Name

-

- ÎR015 ÎR014 ÎRQ12 ÎROll ÎROla ÎR09

Default a a a 0 a a 0 a

BIT NAME ACCESS DESCRIPTION

7~ R/W Reserved

Bit 5 configures I R015 as an open-draln output for connection to PCI bus interrupts.

5 IR015 R/W a • Open-drain PCI-type interrupt 1 - Totem-pole ISA-type output

Bit 4 configures IR014 as an open-draln output for connection to PCI bus interrupts.

4 IR014 R/W a - Open-drain PCI-type Interrupt 1 = Totem-pole ISA-type output

Bit 3 configures IR012 as an open-draln output for connection to PCI bus interrupts.

3 IR012 R/W a - Open-draln PCI-type Interrupt 1 - Totem-pole ISA-type output

Bit 2 configures IR011 es an open-drain output for connection to PCI bus interrupts.

2 IROll R/W a - Open-draln PCI-type interrupt 1 - Totem-pole ISA-type output

Bit 1 configures IROl a as an open-draln output for connection to PCI bus interrupts.

IROla R/W a = Open-drain PCI-type Interrupt 1 = Totem-pole ISA-type output

Bit a configures IRQ9 as an open-drain output for connection to PCI bus Interrupts.

a IRQ9 RJW a = Open-drain PCI-type Interrupt

1 _ Totem-pole ISA-type output

~1ExAs

INSTRUMENTS

2-52 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted}t

Supply voltage range, Vee ... -0.5 V to 6 V Input voltage range, VI: Standard ... -0.5 V to Vee + 0.5 V Fail safe ... . . . • . . . • . . • . . . .. -0.5 V to 6.5 V Output voltage range, Vo: Standard ... -0.5 V to Vee + 0.5 V Fail safe ... -0.5 V to 6.5 V Input clamp current, 11K (VI < 0 or VI > Vee> (see Note 1) ..•... ±20 rnA Output clamp current, 10K (Vo < 0 or Vo > Vee) (see Note 2) ... ±20 rnA Storage temperature range, Tstg ... :... -65°C to 150°C Virtual junction temperature, T J ... 150°C t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating condHions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabilHy.

NOTES: 1. Applies to extemal input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals.

2. Applies to external output and bidirectional buffers. Vo > V

cc

does not apply to fail-safe tenminals.

recommended operating conditions

MIN NOM MAX UNIT

tt Input transition (rise end fall) time CMOS compatible 0 25 ns

TA Operating free-air temperature Commercial 0 25 70 ·C

TJI: Virtual Junction temperature Commercial 0 25 115 ·C

.. . .

:j: These Junction temperatures reflect Simulation conditions. Customer Is responsible for venfylng Junction temperature .

recommended operating conditions for PCI Interface

MIN NOM MAX UNIT

VCCE Supply voltage for control Interface Commercial 4.75 5 5.25 V

VCORE Core voltage Commercial 4.75 5 5.25 V

VCCP PCI supply voltage Commercial 4.75 5 5.25 V

VI Input voltage 0 VCCP V

Vo§ Output voltage 0 VCCP V

VIHll High-level input voltage CMOS compatible 0.7VCCp V

VILll Low-level Input voltage CMOS compatible 0.2 VCCP V

§ Applies to extemal output buffers

11 Applies to external Input and bidirectional buffers without hysteresis

~1ExAs

INSTRUMENTS

POST OFFICE eox 655303 • DALLAS. TEXAS 75265 2-53

Dans le document Solutions Integrated (Page 61-71)