CARDTM CONTROLLER UNIT - Solutions Integrated

SCPS001F-OCTOBER 1994-REVISEDMARCH 1996

I/O window 0 end-address hIgh-byte regIster PCI addresses (hex): Socket A: 8B

Socket B: CB

ExCA offset (hex): Socket A: DB Socket B: 4B

This register contains the high-order address bits used to determine the ena address of 1/0 address window O.

Bit 7 6 5 4 3 2 1 0

Name EA15 EA14 EA13 EA12 EA11 EA10 EA9 EAB

Default 0 0 Q 0 0 0 0 0

BIT NAME ACCESS DESCRIPTION

7-{J EA15-EAB RJW . 1/0 1/IInoow 0 eno address A 15-A8

1/0 window 1 configuration registers

System I/O window 1 register functions duplicate I/O window O. The addresses of each of these registers are

shown below. .

I/O window 1 start-afldress low-byte register PCI addresses (hex): Socket A: 8C

SocketB: CC I/O window 1 B;tart-address high-byte register

PCI addresses (hex): Socket A: 8D Socket B: CD I/O wIndow 1 end-address low-byte regIster PCI addresses (hex): Socket A: 8E Socket B: CE I/O window 1 end-address high-byte register

PCI addresses (hex): Socket-A: 8F Socket B: CF

ExCAoffset (hex): Socket A: DC Socket B: 4C

ExCA offset (hex): Socket A: OD Socket B: 4D

ExCA offset (hex): Socket A: DE Socket B: 4E

ExCA offset (hex): Socket A: OF Socket B: 4F

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INSTRUMENTS

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memory window registers

memory window 0 start-address low-byte register

Bit

PCI addresses (hex): Socket A: 90 ExCA offset (hex):

Socket B: DO

Socket A: 10 Socket B: 50

This register contains the low-order address bits used to determine the start address of the corresponding system memory address mapping window. This provides a minimum memory-mapping window of 4K bytes.

A memory PC Card is selected when the following conditions are satisfied:

• Memory window is enabled.

• PCI address bits A23-A 12 are greater than or equal to the memory window start address.

• PCI address bits A23-A 12 are less than or equal to the memory window end address.

• PCI address bits A031-A024 are equal to the memory window page register value (default is 0).

The system memory address mapping windows can be configured by software to be used independently, or used together to perform mapping for special memory-mapping requirements such as LIM/EMS (Lotus@-lntelrM-Microsoft@/extended memory specification) or XIP (execute in place).

7 6 5 4 3 2 1 0

Name SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12

Default 0 ,0 0 0 0 0 0 0

BIT NAME ACCESS DESCRIPTION

7-0 SAl9-SA12 RJW System memory window start address Al9-A12 memory window 0 start-address high-byte register

Bit

PCI addresses (hex): Socket A: 91 ExCA offset (hex):

Socket B: 01

Socket A: 11 Socket B: 51

This register contains the high-order address bits used to determine the start address of the corresponding system memory address mapping window. Each system memory window'has a datapath size associated with it that is controlled by a bit in this register.

7 6 5 4 3 2 1 0

Name DSIZE ZWS SCRATCH SCRATCH SA23 SA22 SA21 SA20

Default 0

BIT NAME

7 DSIZE

6 ZWS

5-4 SCRATCH

3-0 SA23-SA20

0 0 0 0 0 0 0

ACCESS DESCRIPTION

Memory window data size RJW 0 = Window data width is 8 bits.

RJW

RJW RIW

1 = Window data width is 16 bits.

Window 0 zero wait state. The PCl1 050 emulates the ISA wait-state mechanism used by the Intel 82365SL-DF to control PC Card cycle timing.

0= The 16-bit and 8-bit memory cycles have standard length.

1 _ The 8-bit memory cycles are reduced to equivalent of three ISA clock cycles; the l6-bit memory cycles are reduced to equivalent of two ISA clock cycles.

Scratch bits. General-purpose storage and retrieval.

System-memory window start address A23-A20

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INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 2-35

SCPSOOI F -OCTOBER 1994 - REVISED MARCH 1996

memory window 0 end-address low-byt~ register

PCI addresses (hex): Socket A: 92 ExCA offset (hex):

Socket B: 02

Socket A: 12 Socket B: 52 .

This register contains the low-order address bits used to determine the end address of the corresponding system memory address mapping window. This provides a minimum memory-mapping window ,of 4K bytes.

Bit 7 6 ⁵ ⁴ 3 2 1 0

Name EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12

Default 0 0 0 0 0 0 0 0

BIT NAME ACCESS DESCRIPTION

7-0 EA19-EA12 R/W System memory window end address A 19-A 12 memory window, 0 end-address high-byte register

PCI addresses (hex): Socket A: 93 ExCA offset (hex):

Socket B: 03

Socket A: 13 Socket B: 53

This register contains the high-order address bits used to determine the end address of the corresponding system memory address mapping window.

Bit 7 6 5 4 3 2 .1 0

Name WS1 WSO

- -

ÊA23 ÊA22 ÊA21 ÊA20

Default 0 0 0 0 0 0 0 0

BIT NAME ACCESS DESCRIPTION

Window wait state. The PCI1050 emulates the ISA wait-state mechanism used by the Intel

7-13 ^WS1-WSO ^RIW 82365SL-OF to control PC Card cycle timing. WSI and WSO determine the number of equivalent ISA wait states added to 16-bit memory cycles (8-bit memory cycles are unchanged).

5-4 R/W Reserved

3-Q EA23-EA20. R/W System memory window end address A23-A20

memory window Ooffset-address low-byte register

PCI addresses (hex): Socket A: 94 ExCA offset (hex):

Socket B: 04

Socket A: 14 Socket B: 54

This register contains the low-order address bits that are added to the system address bits A 19-A 12 to generate the memory address for the PC Card.

Bit 7 6 5 4 3 2 1 0

Name OF19 OF18 OF17 OF16 OF15 OF14 OF13 . OF12

Default 0 0 0 0 0 0 0 0

BIT NAME ACCESS DESCRIPTION

7-0 OF19-0F12 RIW Card memory offset address A 19-A 12

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INSTRUMENTS

2-36 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

memory window 0 offset-address high-byte register

PCI addresses (hex): Socket A: 95 ExCA offset (hex):

Socket B: D5

Socket A: 15 Socket B: 55

This register contains the high-order address bits that are added to the system address bits A23-A20 to generate the memory address for the PC Card. The software write protect of the PC Card memory for the corresponding system memory window is controlled by this register. This register also controls whether the corresponding system memory window is mapped to attribute or common memory in the PC Card.

Bit 7 6 5 4 3 2 1 0

Name WP REG OF25 OF24 OF23 OF22 OF21 OF20

Default 0 0 0 0 0 0 0 0

BIT NAME ACCESS DESCRIPTION

\ Write protect. Write operations to the PC Card through the corresponding system memory window

7 WP R/W are controlled by WP.

o

⁼Write operations allowed 1 = Write operations inhibited

6 REG R/W 0= Accesses common memory on the PC Card

1 = Accesses attribute memory on the PC Card 5-0 OF25-0F20 R/W Card memory offset address A25-A20 memory windows 1-4 configuration registers

System memory windows 1-4 register functions duplicate memory window O. The register addresses of each of these registers are shown below.

memory window 1 s,tart-address low-byte register

PCI addresses (hex): Socket A: 98 ExCA offset (hex):

Socket B: D8 memory window 1 start-address high-byte register

PCI addresses (hex): Socket A: 99 ExCA offset (hex):

Socket B: D9 memory window 1 end-address low-byte register

PCI addresses (hex): Socket A: 9A ExCA offset (hex):

Socket B: DA memory window 1 end-address high-byte register

PCI addresses (hex): Socket A: 9B ExCA offset (hex):

Socket B: DB memory window 1 offset-address low-byte register

PCI addresses (hex): Socket A: 9C ExCA offset (hex):

Socket B: DC memory window 1 offset-address high-byte register

PCI addresses (hex): Socket A: 9D ExCA offset (hex):

Socket B: DD

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INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Socket A: 18 Socket B: 58

Socket A: 19 Socket B: 59

Socket A: 1A Socket B: 5A

Socket A: 1B Socket B: 5B

Socket A: 1C Socket B: 5C

Socket A: 1 D Socket B: 5D

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SCPSOOl F -OCTOBER 1994 -REVISED MARCH 1996

memory window 2 start-address low-byte register

PCI addresses (hex): Socket A: AO ExCA offset (hex): Socket A: 20

Socket B: EO Socket B: 60

memory window 2 start-address high-byte register

PCI addresses (hex): Socket A: A 1 ExCA offset (hex): Socket A: 21

Socket B: E1 Socket B: 61

memory window 2 end-address low-byte register

PCI addresses (hex): Socket A: A2 ExCA offset (hex):

Socket B: E2

Socket A: 22 Socket B: 62 memory window 2 encJ-address high-byte register

PCI addresses (hex): Socket A: A3 ~ ExCA offset (hex):

Socket B: E3

Socket A: 23 Socket B: 63 memory window 2 offset-address low-byte register

PCI addresses (hex): Socket A: A4 . ExCA offset (hex): Socket A: 24

Socket B: E4 Socket B: 64

memory window 2 offset-address high-byte register

PCI addresses (hex): Socket A: A5 ExCA offset (hex); Socket A: 25

Socket B: E5 Socket B: 65

memory window 3 start-address low-byte register

PCI addresses (hex): Socket A: A8 ExCA offset (hex): Socket A: 28

SocketB:E8 Socket B: 68

memory window 3 start-address high-byte register

PCI addresses (hex): Socket A: A9 ExCA offset (hex): Socket A: 29

Socket B: E9 . Socket B: 69

memory window 3 encJ-address low-byte register

PCI addresses (hex): Socket A: AA ExCA offset (hex): Socket A: 2A

Socket B: EA Socket B: 6A

memory window 3 encJ-address high-byte register

PCI addresses (hex): Socket A: AB ExCA offset (hex): Socket A: 2B

Socket B: EB Socket B: 6B

memory window 3 offset-address low-byte register

PCI addresses (hex): Socket A: AC ExCA offset (hex): Socket A: 2C

SocketB: E C ' Socket B: 6C

memory window 3 offset-address high-byte register

PCI addresses (hex): Socket A: AD ExCA offset (hex): Socket A: 20

Socket B: ED Socket B: 60

memory window 4 start-address low-byte register

PCI addresses (hex): Socket A; BO ExCA offset (hex): Socket A: 30

Socket B: FO Socket B: 70

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INSTRUMENTS.

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memory window 4 start-address high-byte register

PCI addresses (hex): Socket A: B1 ExCA offset (hex): . Socket A: 31

Socket B: F1 Socket B: 71

memory window 4 end-address low-byte register

PCI addresses (hex): Socket A: B2 ExCA offset (hex): Socket A: 32

Socket B: F2 Socket B: 72

memory window 4 end-address high-byte register

PCI addresses (hex): Socket A: B3 ExCA offset (hex): Socket A: 33

Socket B: F3 Socket B: 73

memory window 4 offset-address low-byte register

PCI addresses (hex): Socket A: B4 ExCA offset (hex):

Socket B: F4 memory window 4 offset-address high-byte register

PCI addresses (hex): Socket A: B5 ExCA offset (hex):

Socket B: F5 PCI configuration header$

Socket A: 34 Socket B: 74

Socket A: 35 Socket B: 75

The PCI configuration headers and configuration registers are listed in Table 6.

Table 6. PCI Configuration Headers

NAME PCIADDRESS

Device identification.1 register OOh

Command register 04h

Device identification 2 register 08h

Miscellaneous function 1 register OCh

Base address registers Q-5 10h,14h,18h,1Ch,20h,24h Expansion ROM base liddress register 30h

Miscellaneous function 2 register 3Ch PCI header reserved registers 28h, 2Ch, 34h, 38h

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INSTRUMENTS .

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 2-39

PCI· TO-PC CARDTM CONTROLLER UNIT

SCPS001 F - OCTOBER 1994 - REVISED MARCH 1996

configuration header

2-40

The PCI supports the PCI-defined 64-byte header. Reads from registers thaI are reserved or that are not implemented return to O.

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10 9 8 7 6 5 4 3 2

o

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Defaults as Shown 110 Space Enable

·1 = Enabled 0= Disabled

L--__

Memory Space Enable 1 = Enabled O=Dlaabled

L--____

Bus Master Enable Not Implemented

L... _ _ _ _ _ Special Cycle Enable Not Implemented ' - - - Memory Write/Invalidate

Not Implemented

L... _ _ _ _ _ _ _ _ VGA Pallet Snoop Not Implemented

1...-_ _ _ _ _ _ _ _ _ Parity Error (PERR) Enable 1 = Enabled

0= Disabled

' - - - Address/Data Stepping Control Not Implemented

L... _ _ _ _ _ _ -,--_ _ _ _ _ Signaled System Error (SERR) Enabla 1 = Enabled

0= Disabled

L... _ _ _ _ _ _ _ _ _ _ _ _ _ _ Fast Back.t~Back Control Not Implemented I...---~~--- Resarwd

PCI Command Register

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configuration header (continued)

18 21 22 23 24 25 28 27 28 29 30 31

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Defaults as Shown

Dans le document Solutions Integrated (Page 51-58)