Front-side (or processor-to-chipset) overclocking is the best way to maximize system performance, especially when it can be combined with multiplier overclocking. If your system lacks multiplier adjustment capabilities, you must rely solely on bus
overclocking at the motherboard level. The difficulty lies in the fact that overclocking the front-side bus can affect the rates of all buses throughout the system.
Figure 4-5: Front-side bus configuration example
The front-side bus rate is linked with other bus rates in most x86 systems. The
peripheral component interconnect bus, or PCI, the accelerated graphics port bus, or AGP, and the various memory buses, are examples of this design paradigm. Each of the system's interconnect buses serve to connect various devices to the processor, and each operates at a rate fractional to the operating rate of the front-side bus.
While not all motherboard chipsets offer identical capabilities, most follow industry design specifications for compatibility reasons.
The Memory Bus
The memory bus can operate in one of two modes, synchronous or asynchronous.
Synchronous operation means that the memory bus operates at the same base frequency as the front-side bus. The synchronous memory bus is the simplest architecture to manipulate, though it may not be best for maximizing overclocking potential. Asynchronous operation allows the memory bus to function at a different rate than the front-side bus. Asynchronous designs can be based on incremental
frequency changes related to the front-side bus frequency or entirely on independent rates.
Many motherboards are able to operate in either synchronous or asynchronous memory access modes. The ability to change the front-side bus frequency depends on the memory access mode in use. Quality memory, capable of stable operation at extended frequencies, is preferred. As expected, different platforms react differently to memory overclocking.
Old designs using 30- or 72-pin single inline memory modules (SIMMs), like fast-page or extended data out (EDO) memory, tend to become unstable at relatively low operating speeds during overclocking. The older 30-pin designs can rarely scale beyond 40 MHz, while 72-pin designs generally reach their maximum around 83 MHz. The need for asynchronous bus operation with such architectures became evident as processor-to-chipset rates began to outpace memory capabilities.
Figure 4-6: RAMBUS memory example
Asynchronous memory operation became even more necessary with the adoption of SDRAM, DDR RAM, and RAMBUS memory technologies. Early PC-66 memory modules were, at best, suspect for overclocking. Later fabrication techniques allowed successful scaling to higher operating speeds, up to 166+ MHz with the PC-166 modules. Asynchronous operation does insert longer latencies in the chipset-to-memory pipeline; however, the benefits of greater bandwidth commonly outweigh such penalties. For this reason most non-Intel-based motherboards allow users to raise or lower the memory bus speed in relation to the front-side bus speed.
Figure 4-7: Common bus rates The PCI Bus
The PCI bus speed is derived from the front-side bus speed. The PCI 2.x
specification defines 33 MHz as the default bus frequency, though most of today's
better components can scale to 40 MHz and beyond. In most systems, the PCI bus speed is a fraction of the front-side bus speed. For example, the Pentium IIIe uses a 100-MHz front-side bus. A 1/3 factor is introduced into the PCI timing process to produce the default 33-MHz PCI bus speed.
Certain crossover points in PCI to front-side bus ratios can create stability problems.
The most common risky frequencies are those approaching 83 and 124 MHz for the front-side bus. Due to a ½ divider limit at the 83-MHz range, the PCI rate is extended to 41.5 MHz, well beyond its 33-MHz default specification. The 124-MHz front-side bus rate leads to a similar scenario, as the 1/3 divider forces a 41.3-MHz PCI rate.
Some motherboard designs allow users to refine the divider value, but this feature is not common in production-level boards.
PCI components with the highest risk of failure at 40+ MHz are storage drives, especially early-model IDE drives. SCSI drives do not usually exhibit this problem due to their more exacting specifications. Stability issues can often be resolved by lowering the drive-transfer signaling speed by one level. This results in lower bandwidth, though the performance gains realized through overclocking the processor or the front-side bus may negate any loss. Benchmarking utilities are needed to ascertain performance differences.
The AGP Bus
The AGP bus is similarly limited during front-side bus overclocking. Problems again arise at 83 and 124 MHz for nearly all chipset designs. Some motherboard
architectures also suffer instability or high failure rates at 100+ MHz due to limitations in early AGP bus implementations. For example, Intel's popular BX chipset can support proper 133 MHz front-side bus operation for all system buses except the AGP. The BX features only 1/1 and 2/3 AGP divider functions, and thus a 133-MHz front-side bus rate leads to a problematic 88.6-MHz AGP rate.
Figure 4-8: AGP bus configuration
Many of the latest AGP graphics accelerators can operate effectively at extended levels, often up to 90 MHz. For maximum stability, it may be necessary to lower AGP
transfer speeds by one level (that is, 4x to 2x) or to disable AGP side-band addressing. Those with older AGP video cards or motherboard-level integrated graphics chipsets need to analyze stability closely through long-term testing. Even if an AGP card seems stable, additional frequency loads can damage the graphics accelerator over time. Failure may come after several weeks of operation or problems may never surface. AGP overclocking is a gamble; it requires extreme care, especially when it introduces problematic front-side bus rates into the graphics pipeline.
USB or IEEE 1394 Firewire connections do not usually suffer under front-side bus overclocking. These well-designed implementations can handle the extended operating frequencies involved. Older buses, like ISA, can be problematic. Systems with peripherals based on such architecture would likely see greater benefit from upgrading than from overclocking.