COP420L/COP421 L Instruction Set
OPERATIONAL SYMBOLS
+
PlusMinus ---+ Replaces
~ Is exchanged with Is equal to
A
The ones complement of A E9 Exclusive-ORRange of values
o
""C~ N
o
r-...
o o
""C
~ N
...
... r-o o
""C
~
N N
r-...
o o
""C W N o ...
r-o o
""C W N
...
...
r-o o
""C W N N
r-III
..J N N Cf)
a..
o o
'"
..J
....
N Cf)
a.. o o '"
..J
o
N Cf)
a..
o o
::=i
N N
~
a..
o o
::=i
....
N ~
a.. o
o ::=i
o
Nl o
o
Instruction Set
(Continued)TABLE II. COP420L/421L Instruction Set Hex Machine
Mnemonic Operand Code Language Code DataFlow Skip Conditions (Binary)
ARITHMETIC INSTRUCTIONS
ASC 30 10011100001 A + C + RAM(8) -+ A Carry Carry -+ C
ADD 31 1001110001
I
A + RAM(8) -+ A NoneADT 4A 1010011010
I
A + 1010 -+ A NoneAISC y 5- 10101
I
Y..I
A+y-+A CarryCASC 10 10001100001 A + RAM(8) + C -+ A Carry Carry -+ C
CLRA 00 10000100001 O-+A None
COMP 40 10100100001 A-+A None
NOP 44 10100101001 None None
RC 32 10011100101 "0" -+ C None
SC 22 10010100101 "1" -+ C None
XOR 02 10000100101 A E9 RAM(8) -+ A None
TRANSFER OF CONTROL INSTRUCTIONS
JID
FF
11111111111 ROM (PC9:B, A,M) -+ NonePC7:0
JMP a 6- 101101001 a9'a 1 a -+ PC None
-- I
a7:0I
JP a
--
11I
a6:0 1 a -+ PC6:0 None(pages 2,3 only)
--
111I
or as:o 1 a -+ PC5:0 (all other pages)JSRP a
--
110I
as:o 1 PC + 1 -+ SA -+ None S8 -+ SC0010 -+ PC9:6 a -+ PCs:o
JSR a 6- 101101101a9:sl PC + 1 -+ SA -+ None
-- I
a7:0 1 S8 -+ SC a -+ PCRET 48 10100110001 SC -+ S8 -+ SA -+ PC None
RETSK 49 10100110011 SC -+ S8 -+ SA -+ PC Always Skip on Return
1-150
Description
Add with Carry, Skip on Carry
Add RAMtoA Add Ten to A Add Immediate, Skip on Carry(y'* 0)
Compliment and Add with Carry, Skip on Carry Clear A
Ones complement of A to A No Operation
ResetC SetC
Exclusive-OR RAM with A
Jump Indirect (Note 3)
Jump
Jump within Page (Note 4)
Jump to Subroutine Page (NoteS)
Jump to Subroutine
Return from Subroutine Return from Subroutine then Skip
Instruction Set
(Continued)TABLE II. COP420L/421L Instruction Set (Continued)
Hex Machine
Mnemonic Operand
Code Language Code Data Flow Skip Conditions
(Binary) MEMORY REFERENCE INSTRUCTIONS
CAMO 33 10011 10011
I
A ---+ 07:4 None3C 10011111001 RAM (B) ---+ 03:0
COMA 33 10011100111 07:4 ---+ RAM (B) None
2C 10010111001 03:0 ---+ A
LD r -5 100lrl01011 RAM (B) ---+ A None
Br Ell r ---+ Br
LDD r,d 23 10010100111 RAM(r,d) ---+ A None
--
1001 r 1 d 1LOID BF 11011 11111 1 ROM(PC9:B,A,M) ---+ 0 None SB ---+ SC
RMB 0 4C 10100111001
o
---+ RAM(B)o None1 45 1010010101
I o
---+ RAM(B)1 2 42 10100100101o
---+ RAM(B)2 3 43 10100100111o
---+ RAM(Bb5MB 0 40 10100111011 1 ---+ RAM(B)o None
1 47 10100111011 1 ---+ RAM(Bh 2 46 10100101101 1 ---+ RAM(B)2 3 4B 10100110111 1 ---+ RAM(Bb
STII y 7- 10111 1 y
I
y ---+ RAM (B) NoneBd
+
1 ---+ BdX r -6 100
I
rl 0110 1 RAM (B) ~ A NoneBr Ell r ---+ Br
XAD r,d 23 10010100111 RAM(r,d) ~ A None
--
110 1 rI
d 1XDS r -7 100 1 r
I
0111 1 RAM (B) ~ A Bd decrements past 0 Bd - 1 ---+ BdBr Ell r ---+ Br
XIS r -4 100 1 r
I
0100 1 RAM (B) ~ A Bd increments past 15 Bd+
1 ---+ BdBr Ell r ---+ Br
Description
Copy A, RAM to 0
Copy Q to RAM, A
Load RAM into A, Exclusive-OR Br with r Load A with RAM pOinted to directly by r,d Load Q Indirect (Note 3)
Reset RAM Bit
Set RAM Bit
Store Memory Immediate and Increment Bd Exchange RAM with A, Exclusive-OR Br with r Exchange A with RAM pointed to directly by (r,d) Exchange RAM with A and Decrement Bd, Exclusive-OR Br with r Exchange RAM with A and Increment Bd, Exclusive-OR Br with r
o
.""'"
I\) Q
r-...
o o
."
"'"
I\) -"
...
r-o o
."
"'"
I\) I\)
r-...
o o
."
W I\) Q
r-...
o o
."
W I\) -"
C o
o
."W I\) I\)
r-...I C\I C\I C")
o a..
o ...
...I
...
C\I C")
o a..
... o
...I
o
C\I C")o a..
o ...
...I C\I C\I
~
a..
o o ...
...I
...
C\I ~
o a..
o ...
...I
o
C\I~
a..
o o
Instruction Set
(Continued)TABLE II. COP420L/421L Instruction Set (Continued) Hex Machine
Mnemonic Operand
Code Language Code DataFlow Skip Conditions
(Binary) REGISTER REFERENCE INSTRUCTIONS
CAB 50 10101100001 A ---+ Bd None
CBA 4E 1010011110 1 Bd ---+ A None
LBI r,d
--
100Irl(d-1)1 r,d ---+ B Skip until not an LBI(d=0,9:15) or 33 10011100111
--
110 1 r 1 d 1 (any d)LEI y 33 10011100111 y ---+ EN None
6- 10110 1 'i 1
XABR 12 10001100101 A ~ Br (0,0 ---+ A3.A2) None TEST INSTRUCTIONS
SKC 20 10010100001 C = "1"
SKE 21 10010100011 A = RAM(B)
SKGZ 33 10011100111 G3:0 = 0
21 10010100011
SKGBZ 33 10011100111 1st byte
0 01 10000100011
} 2nd byte
Go = 0
1 11 10001100011 G1 = 0
2 03 10000100111 G2 = 0
3 13 10001100111 G3 = 0
SKMBZ 0 01 10000100011 RAM(B)o = 0
1 11 10001100011 RAM(B)1 = 0
2 03 10000100111 RAM(B)2 = 0
3 13 10001100111 RAM(B)a = 0
SKT 41 10100100011 A time-base counter
carry has occurred since last test
1-152
Description
Copy A to Bd CopyBd toA Load B Immediate with r,d (Note 6)
Load EN Immediate (Note 7)
Exchange A with Br
Skip if C is True Skip if A Equals RAM Skip if G is Zero (all 4 bits) Skip if G Bit is Zero
Skip if RAM Bit is Zero
Skip on Timer (Note 3)
Instruction Set
(Continued)TABLE II. COP420L/421L Instruction Set (Continued) Machine
Mnemonic Operand Hex
Code Language Code Data Flow Skip Conditions Description
(Binary) INPUT IOUTPUT INSTRUCTIONS
ING 33 10011 10011 1 G~A None Input G Ports to A
2A 10010110101
ININ 33 10011 10011 1 IN ~ A None Input IN Inputs to A (Note 2)
28 10010110001
INIL 33 10011100111 IL3, CKO, "0", ILa ~ A None Input IL Latches to A (Note 3)
29 10010110011
INL 33 10011100111 L7:4 ~ RAM(B) None Input L Ports to RAM, A
2E 10010111101 L3:a ~ A
OBD 33 10011 10011 1 Bd ~ D None Output Bd to D Outputs
3E 10011 11110 1
OGI y 33 10011100111 y~G None Output to G Ports Immediate
5- 10101 1 y 1
OMG 33 10011100111 RAM(B) ~ G None Output RAM to G Ports
3A 10011110101
XAS 4F 1010011111 1 A ~ SIO,C ~ SKL None Exchange A with SID
(Note 3)
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: The ININ instruction is only available on the 26-pin COP420L as the other devices do not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP may not jump to the last word in page 2.
Note 6: LBI is a single-by1e instruction if d = 0,9,10,11,12,13,14, or 15. The machine code for the lower 4 bits equals the binary value of the "d'" data minus 1, e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 6 (10002)' To load 0, the lower 4 bits of the LBI instruction should equal 15 (11112)'
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Description of Selected Instructions
The following information is provided to assist the user in understanding the operation of several unique instructions and to provide notes useful to programmers in writing COP420L/421 L programs.
XAS INSTRUCTION
XAS (Exchange A with SID) exchanges the 4-bit contents of the accumulator with the 4-bit contents of the SID register.
The contents of SID will contain serial-in/serial-out shift reg-ister or binary counter data, depending on the value of the EN register. An XAS instruction will also affect the SK out-put. (See Functional Description, EN Register, above.) If
SID is selected as a shift register, an XAS instruction must be performed once every 4 instruction cycles to effect a continuous data stream.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction, transferring program control to a new ROM location pointed to indirectly by A and M. It loads the lower 8 bits of the ROM address register PC with the contents of ROM addressed by the 1 O-bit word, PC9:8, A, M. PCg and PCa are not affected by this instruction.
Note that JID requires 2 instruction cycles to execute.
o
"'1J01:1-o N
...
r-o o
"'1J 01:1-N
...
...
r-o o
"'1J 01:1-N N
r-
...o o
"'1J W N o
r-
...o o
"'1J
w
N...
r-
...o o
"'1J W N N
r-•
-J r---~
N N C")
a. o
o ::J
~
N
a.
Cf)o o
' --J
o
N C")o a.
o ::J
N N ~
o a.
o
' --J~
N
~
a.
o o
' --J
o
N~
a.
o o
Description of Selected Instructions
(Continued) INIL INSTRUCTIONINIL (Input IL Latches to A) inputs 2 latches, IL3 and ILo (see Figure 8) and CKO into A. The IL3 and ILo latches are set if a low-going pulse ("1" to "0") has occurred on the IN3 and INa inputs since the last INIL instruction, provided the input pulse stays low for at least two instruction times. Execution of an INIL inputs IL3 and ILo into A3 and AO respectively, and resets these latches to allow them to respond to subse-quent low-going pulses on the IN3 and INa lines. If CKO is mask programmed as a general purpose input, an INIL will input the state of CKO into A2. If CKO has not been so programmed, a "1" will be placed in A2. A "0" is always placed in A 1 upon the execution of an INIL. The general purpose inputs IN3-INa are input to A upon execution of an ININ instruction. (See Table II, ININ instruction.) INIL is use-ful in recognizing pulses of short duration or pulses which occur too often to be read conveniently by an ININ instruc-tion. IL latches are not cleared on reset.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the 8-bit Q register with the contents of ROM pointed to by the 1 O-bit word PCg, PCa, A, M. LQID can be used for table lookup or code conversion such as BCD to seven-segment. The LQID instruction
"pushes" the stack (PC
+
1 ----+ SA ----+ SB ----+ SC) and replaces the least significant 8 bits of PC as follows: A ----+PC7:4, RAM (B) ----+ PC3:a, leaving PCg and PCa un-changed. The ROM data pointed to by the new address is fetched and loaded into the Q latches. Next, the stack is
"popped" (SC ----+ S8 ----+ SA ----+ PC), restoring the saved value of PC to continue sequential program execu-tion. Since LQID pushes SB ----+ SC, the previous contents of SC are lost. Also, when LQID pops the stack, the previ-ously pushed contents of SB are left in SC. The net result is that the contents of SB are placed in SC (SB ----+ SC). Note the LQID takes two instruction cycle times to execute.
INoIIN3
COP420l/421l
ININ
1.
INll
TLlDD/8825-21 FIGURE 8. INIL Hardware Implementation
1-154
SKT INSTRUCTION
The SKT (Skip On Timer) instruction tests the state of an internal 10-bit time-base counter. This counter divides the instruction cycle clock frequency by 1024 and provides a latched indication of counter overflow. The SKT instruction tests this latch, executing the next program instruction if the latch is not set. If the latch has been set since the previous test, the next program instruction is skipped and the latch is reset. The features associated with this instruction, there-fore, allow the COP420Ll421 L to generate its own time-base for real-time processing rather than relying on an ex-ternal input signal.
For example, using a 2.097 MHz crystal as the time-base to the clock generator, the instruction cycle clock frequency will be 65 kHz (crystal frequency + 32) and the binary coun-ter output pulse frequency will be 64 Hz. For time-of-day or similar real-time processing, the SKT instruction can call a routine which increments a "seconds" counter every 64 ticks.
INSTRUCTION SET NOTES
a. The first word of a COP420Ll421 L program (ROM ad-dress 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one in-struction cycle time is devoted to skipping each byte of the skipped instruction. Thus all program paths except JID and LQID take the same number of cycle times whether instructions are skipped or executed. JID and LQID instructions take 2 cycles if executed and 1 cycle if skipped.
c. The ROM is organized into 16 pages of 64 words each.
The Program Counter is a 10-bit binary counter, and will count through page boundaries. If a JP, JSRP, JID or LQID instruction is located in the last word of a page, the instruction operates as if it were in the next page. For example: a JP located in the last word of a page will jump to a location in the next page. Also, a LQID or JID located in the last word of page 3, 7, 11, or 15 will access data in the next group of four pages.
Option List
The COP420L/421 L mask-programmable options are assigned numbers which correspond with the COP420L pins.
The following is a list of COP420L options. When specifying a COP421 L chip, Options 9, 10, 19, and 20 must all be set to zero.
When specifying a COP422L chip, options 9,10, 19, and 20 must all be set to zero; options 21 and 22 may not be set to one, three or five; and option 2 may not be set to one. The options are programmed at the same time as the ROM pattern to provide the user with the hardware flexibility to interlace to various 1/0 components using little or no external circuitry.
The Option Table should be copied and sent in with your EPROM or disc.
Option 1
=
0: Ground Pin-no options available Option 19: INo InputOption 2: CKO Output same as Option 9
= 0: clock generator output to crystal/resonator (0 not Option 20: IN3 Input allowable value if Option 3 = 3) same as Option 9
= 1: pin is RAM power supply (VR) input (not available on Option 21: Go I/O Port
the COP422L) = 0: very-high current standard output
= 2: general purpose input with load device to Vee = 1: very-high current open-drain output
= 3: general purpose input, Hi-Z = 2: high current standard output
= 3: High current TRI-STATE push-pull output same as Option 21
= 4: Low-current LED direct segment drive output Option 27: D1 Output
= 5: Low-current TRI-STATE push-pull output same as Option 21
Option 6:
La
Driver Option 28: Do Output Option 34: CKO Input Levels(CKO
=
input; Option 2=
2,3) Option 36: Internal Initialization Logic=
0: normal operation= 1: no internal initialization logic
o
"ar-..J National along with the EPROM.
OPTION DATA
TEST MODE (Non-Standard Operation)
The SO output has been configured to provide for standard test procedures for the customer-programmed COP420L.
With SO forced to logic "1", two test modes are provided, depending upon the value of SI:
a. RAM and Internal Logic Test Mode (SI = 1) b. ROM Test Mode (SI
=
0)These special test modes should not be employed by the user; they are intended for manufacturing test only.
APPLICATIONS # 1: COP420L General Controller Figure 9 shows an interconnect diagram for a COP420L
2. The 03-00 outputs drive the digits of the multiplexed dis-play directly and scan the columns of the 4 x 4 keyboard matrix.
3. The IN3-INo inputs are used to input the 4 rows of the keyboard matrix. Reading the IN lines in conjunction with the current value of the 0 outputs allows detection, de-bouncing, and decoding of anyone of the 16 keyswitch-es. Keep-Alive option description).
5. SI is selected as the input to a binary counter input. With SIO used as a binary counter, SO and SK can be used as general purpose outputs.
6. The 4 bidirectional G 1/0 ports (G3-GO) are available for use as required by the user's application.