INTRODUCTION
NOTE
This is not the complete LSI-11 bus specifi-cation. The next printing of this document will contain greater detail in a number of areas. The goal is to permit users to design and implement typical interfaces to the LSI-11 bus.
The processor, memory and I/O devices communicate via 38 bi-directional signal lines that constitute the LSI-11 bus. Addresses, data, and control information are sent along these signal lines, some of which contain time-multiplexed information. The lines are functionally divided as follows:
18 Data/address tines-· BDAL<17:00>
6 Data transfer control Iines-BBS7, BDIN, BDOUT, BRPLY, BSYNC, BWTBT
3 Direct memory access controllines-BDMG, BDMR, BSACK 6 Interrupt control lines-BEVNT, BIAK, BIR04, BIROS,
BIR06, BIR07
S System control lines-BDCOK, BHAL T, BINIT, BPOK, BREF Most LSI-11 bus signals are bidirectional and use terminations for a negated (high) signal level. Devices connect to these lines via high-impedance bus receivers and open collector drivers. The asserted state is produced when a bus driver asserts the line low.
Although bidirectional lines are electrically bidirectional (any point along the line can be driven or received), certain lines are functionally unidirectional. These lines communicate to or from a bus master (or signal source), but not both. Interrupt Acknowledge (BlACK) and Direct Memory Access Grant (BDMG) signals are physically unidirectional in a daisy-chain fashion. These signals originate at the processor output signal pins. Each is received on device input pins (BIAKI or BDMGI) and conditionally retransmit-ted via device output pins (BIAKO or BDMGO). These signals are received from higher priority devices and are retransmitted to lower priority devices along the bus.
Master/Slave Relationship
Communication between devices on the bus is asynchronous. A master/slave relationship exists throughout each bus transaction.
97
At any time, there is one device that has control of the bus. This controlling device is termed the "bus master." The master device controls the bus when communicating with another device on the bus, termed the slave. The bus master (typically the processor or a DMA device) initiates a bus transaction. The slave device sponds by acknowledging the transaction in progress and by re-ceiving data from, or transmitting data to, the bus master. LSI-11 bus control signals transmitted or received by the bus master or bus slave device must complete the sequence according to bus protocol.
The processor controls bus arbitration (i.e., who becomes bus master at any given time). A typical example of this relationship is the processor, as master, fetching an instruction from memory (which is always a slave). Another example is a disk, as master, transferring data to memory as slave. Theoretically, any device can be master or slave depending on the circumstances. Com-munication on the LSI-11 bus is interlocked so that for each control signal issued by the master device, there must be a re-sponse from the slave in order to complete the transfer. It is the master/slave signal protocol that makes the LSI-11 bus asyn-chronous. The asynchronous operation precludes the need for synchronizing with clock pulses.
Since bus cycle completion by the bus master requires response from the slave device, each bus master must include a timeout error circuit that will abort the bus cycle if the slave device does not respond to the bus transaction within 10 microseconds.
The actual time before a timeout error occurs must be longer than the reply time of the slowest peripheral or memory device on the bus.
The signais and pin assignments are tabulated in Tabie 2-1. The pin nomenclature is for reference and is only required when ex-amining DIGITAL modules and circuit schematics. Table 2-2 con-tains a functional description of the LSI-11 bus pins and signals.
Table 2-1
Categories of LSI-11 Bus Signal Lines
Number Functional (Name)
of Pins Category DIG.ITAL's Nomenclature (Pin)
18 Data/Address BDALO, BDAL1, BDAL2 • BDAL15, BDAL16, BDAL"l7
AU2 AV2 BE2 ..,BV2 AC1 AD1
6 Data BDOUT, BRPLY, BDIN, BSYNC, BWTBT, BBS7
Control AE2 AF2 AH2 AJ2 AK2 AP2
6 Interrupt BIR07, BIR06, BIR05, BIR04, BIAKO, BIAKI
Control BP1 AB1 AA1 AL2 AN2 AM 2.
4 DMA BDMR, BDMGO, BDMGI, BSACK
Control AN1 AS2 AR2 BN1
~ ~ 6 System BHALT, BREF, BOCOK, BPOK, BEVNT, BINIT
Control AP1 AR1 BA1 BB1 BR1 AT2
3 +5Vdc AA2, BA2, BV1
2 +12 Vdc AD2, BD2
2 -12 Vdc AB2, BB2
2 +12B (battery) AS1, BS1
1 +5B (battery) AV1, (AE1, AS1 alternates)
8 GND AC2, AJ1, AM1, AT1, BC2, BJ1, BM1, BT1 8 S SPARES AE1, AF1, AH1, BC1, 801, BE1, BF1, BH1 4 M SPARES AK1 - AL1, BK1 - BL1 (pairs connected)
2 P SPARES AU1, BU1
72
Bus
Address line 16 during addressing proto-col; memory error line during data trans-fer protocol.
Address line 17 during addressing proto-col; memory error enable during data transfer protocol.
Special spare-not assigned or bused in DIGITAL cable or backplane assemblies;
available for user connection. Optionally, this pin may be used for +5 V battery
Special spare-not assigned or bused in DIGITAL cable or backplane assemblies;
available for user interconnection. In the highest priority device slot, the processor may use this pin for a signal to indicate its RUN state.
Special spare-not assigned nor bused in DIGITAL cable or backplane assemblies;
available for user interconnection.
Ground-System signal ground and dc
Direct Memory Access (OMA) Request-device asserts this signal to request bus mastership. The processor arbitrates bus mastership between itself and all DMA devices on the bus. If the processor is
Table 2-2 Functional Descriptions (Cont.)
Memory refresh-used to refresh dy-namic memory devices. The LSI-11 pro-cessor microcode features automatic re-fresh control. BREF L is asserted during this time to override memory bank selec-tion decoding. Interrupt requests and BBS7 are blocked out during this time.